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At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology, will present a process flow for a complementary FET (CFET) device for nodes beyond N3. The proposed CFET can eventually outperform FinFETs and meet the N3 requirements for power and performance. It offers a potential area scaling of both standard cells (SDC) and memory SRAM cells by 50%.

The CFET is a further evolution of the vertically stacked gate all around nanowire transistor. Instead of stacking either n-type or p-type devices, it stacks both on top of each other. Imec’s proposed flow consists of stacking an n-type vertical sheet on a p-type fin. This choice exploits the FinFET process flow and benefits from the potential for strain engineering in the bottom pFET. Based on TCAD analysis, the proposed CFET can meet the N3 targets for power and performance, where it will outperform FinFETs. However, the dominant parasitic resistance of the deep vias needs to be reduced. This can be achieved by introducing advanced Middle of Line (MOL) contacts using e.g. ruthenium.

A design-technology co-optimization (DTCO) analysis reveals that the CFET device used in either an SDC or SRAM cell has the potential of 50% area reduction. The SDC area is mostly driven by accessing the transistor terminals. Consequently, the area gain using CFETs will not lie in the reduction of the active footprint, but rather in the considerable simplification of the transistor terminal access. By fully benefiting from the CFET architecture, it is possible to reduce the SDC to three routing tracks whereas the most advanced FinFET libraries today need six. For SRAM cells, the same area reduction is possible thanks to a new cross-coupling scheme that allows us to scale the cell height from T6 to T4.

“Given its excellent characteristics and scaling potential, the CFET device is an excellent contender for the new device architecture we need for nodes beyond N3, pushing the horizon for Moore’s Law farther out,” stated Julien Ryckaert, distinguished member of the technical staff at imec.”

These results will be presented on June 21 at the VLSI Technology Symposium, in session T13: FET performance and scaling. This research is performed in cooperation with equipment companies TEL Coventor and Lam Research and with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

One of the leading challenges for autonomous vehicles is to ensure that they can detect and sense objects–even through dense fog. Compared to the current visible light-based cameras, infrared cameras can offer much better visibility through the fog, smoke or tiny particles that can scatter the visible light.

Artist’s rendering of light interacting with BaTiS3 crystals. Credit: Talia Spencer

Within the air, infrared light –within a specific range called mid-wave infrared– scatter much less compared to other visible or other infrared light waves. Infrared cameras can also see more effectively in the dark, when there is no visible light. However, currently the deployment of infrared cameras is limited by their heavy cost and scarcity of effective materials. This is where materials, which possess unique optical properties in the infrared and can be scalable, might make a difference in providing better object identification in several technologies including autonomous vehicles.

A new material developed by scientists at the USC Viterbi School of Engineering and the University of Wisconsin along with researchers from Air Force Research Laboratories, University of Missouri, and J.A. Woollam Co. Inc, might show promise for such infrared detection applications as autonomous vehicles, emergency services and even manufacturing.

The research group of Jayakanth Ravichandran, an assistant professor of materials sciences at the USC Viterbi School of Engineering has been studying a new class of materials called chalcogenide perovskites. Among these materials is Barium titanium sulfide (BTS), a material rediscovered and prepared in large crystal form by Shanyuan Niu, a doctoral candidate in the Materials Science program at the USC Mork Family Department of Chemical Engineering and Materials Science. Ravichandran’s research group collaborated with the research groups of Mikhail Kats, an assistant professor of electrical and computer engineering at University of Wisconsin-Madison and Han Wang, an assistant professor of electrical engineering and electrophysics in USC’s Ming Hsieh Department of Electrical Engineering to study how infrared light interacts with this material. These researchers discovered that this material interacted differently with light in two different directions.

“This is a significant breakthrough, which can affect many infrared applications,” says Ravichandran.

This direction dependent interaction with light is characterized by an optical property called birefringence. In simple terms, birefringence can be viewed as light moving at different speeds in two directions in a material. Much like sunglasses with polarized lenses block glare, BTS has the ability to block or slow down light depending on the direction in which it travels in the material. The researchers maintain that their material, barium titanium sulfide, has the highest birefringence among known crystals.

“The birefringence is larger than that of any known solid material, and it has low losses across the important long-wave infrared spectrum,” says Kats.

How BTS could improve infrared vision:

The BTS material can be used to construct a sensor to filter out certain polarizations of light to achieve better contrast of the image. It could also help filter light coming from different directions to enable sensing of a remote object’s features. This could be particularly important for improving infrared vision used in autonomous vehicles, which need to see the entire landscape around them even in low visibility conditions.

“The hope is that in the future, a BTS-enhanced sensor in a car would function as retinas do to the human body,” says Niu.

The authors believe these infrared-responsive materials can extend human perception. Beyond autonomous vehicles, there are other possible heat sensing or temperature measurement applications. One application could be in the creation of imaging tools used by firefighters to generate an instant temperature map outside a burning building to assess where a fire is spreading and where emergency responders need to rescue trapped individuals.

At present, the cost of infrared equipment makes it too expensive for all fire stations to have such equipment. BTS, which is made of elements readily abundant in earth crust–could make infrared equipment more affordable and effective. In addition, such materials are safer for the user and the environment, as well as easier to dispose of than the materials that are used now, which contain hazardous elements such as mercury and cadmium.

These materials could also be useful in devices that sense harmful molecules, gases, even biological systems. The applications range from heat sensing, pollution monitoring to medicine.

“To date, the constraint of existing mid-IR materials is a big bottleneck to translate many of these technologies,” says USC’s Wang.

The researchers hope that intense research in this area will make several of these technologies a reality in the near future.

The research on BTS is documented in “Giant optical anisotropy in a quasi-1D crystal” featured in Nature Photonics.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology presented considerable progress in enabling germanium nanowire pFET devices as a practical solution to extend scaling beyond the 5nm node. In a first paper, the research center unveiled an in-depth study of the electrical properties of strained germanium nanowire pFETs. A second paper presents the first demonstration of vertically-stacked gate-all-around highly-strained germanium nanowire pFETs.

“With a number of scaling boosters, the industry will be able to extend FinFET technology to the 7- or even 5nm node,” says An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the FinFET process steps. But one important challenge of using lateral nanowires is the significant decrease of the channel cross-section compared to conventional FinFETs. To improve the drive per footprint, several nanowires have to be stacked, but this comes with a serious penalty of increased parasitic capacitance and resistance. A solution is to replace the silicon nanowires by a high-mobility channel material such as germanium (Ge), providing the necessary current boost per footprint”, adds Steegen, “These new studies show that solution is indeed feasible, reaching the cost, area and performance requirements for nodes beyond 5nm.”

The first study of high-performing strained Ge nanowire pFETs gives insight in the device performance these new devices may offer for high-end analog and high-performance digital solutions. One conclusion is that dedicated optimizations of key process steps make these devices a serious contender for the GAA technology. The second paper reports on Ge GAA FETs with single nanowires, achieving a performance that matches state-of-the-art SiGe and Ge FinFETs. Moreover, for the first time, strained p-type Ge GAA FETs with stacked nanowires were demonstrated on a 14/16nm platform. The GAA nanowire technology appears as a promising high-performance solution for future nodes, provided that the junctions are further optimized.

“These complimentary studies establish germanium GAA nanowire technology as a valid contender for the sustained scaling that will be required to fulfill the requirements for the data-driven IoT-era requiring huge computational power,” concludes Steegen.

These results will be presented on June 20 at the VLSI Technology Symposium, in session T8: Advanced FinFET and GAA. This research is performed in cooperation with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

An international team of scientists, including NUST MISIS’s Professor Gotthard Seifert, have made an important step towards the control of excitonic effects in two-dimensional van der Waals heterostructures. In the future, this research will help to create electronics with more controlled properties. The research has been published in Nature Physics.

The creation of two-dimensional semiconductor materials is one of the most important areas of modern materials science. These materials can be the basis for elements needed to create the next generation of electronics.

One two-dimensional material with suitable electronic characteristics is two-dimensional molybdenum disulfide (MoS2), which has a single-layer structure (one atom layer) of molybdenum located between two sulfur layers: this material has a high charge mobility and high on/off in the transistor element.

In 2017, Professor Gotthard Seifert described the mechanism of defect germination in the structure of two-dimensional molybdenum disulfide as a process that will make it possible for scientists to capitalize on two-dimensional MoS2’s full potential use in microelectronics. This work was published in the leading journal, ACS Nano.

The study of other two-dimensional materials’ properties for their application in electronics has become the next step in this field. Monolayers of molybdenum disulfide (and, for example, wolframite diselenides–WSe2) have shown exceptional optical properties due to excitons: tightly bound pairs of electron-hole (quasiparticles acting as a carrier of a positive charge).

At the same time, the creation of the MoS2/WSe2 heterostructure by laying separate monolayers on each other leads to the appearance of a new type of exciton in it, where the electron and the hole are spatially divided into different layers.

Scientists have shown that interlayer excitons give a very specific optical signal display when layered. This allow scientists to study quantum phenomena, making it ideal for experiments in volitronics (a field of quantum electronics, «valley», or the local minimum of an element’s conduction zone) to control electrons in the «valleys» of semiconductors. In the future, these breakthroughs could lead to the most effective way to code information (by placing an electron in one of these valleys).

“Thanks to the use of spectroscopic methods and quantum-chemical calculations from the first principles, we have revealed a partially charged electron-hole in MoS2/WSe2 heterostructures, as well as [the electron-hole’s] location. We have managed to control the radiation energy of this new exciton by changing the relative orientation of the layers”, commented Professor Gotthard Seifert, one of NUST MISIS`s leading scientists.

According to Seifert, this result is an important step towards understanding and controlling exciton effects in Van der Waals heterostructures (where these distance-dependent atomic interactions occur). The research team is continuing to study the effect of layer rotations on the material’s electronic properties. In the future, this will allow for the creation of unique new materials for solar panels or electronics.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the world-leading research and innovation hub in nanoelectronics and digital technology, demonstrates for the first time the possibility to fabricate spin-orbit torque MRAM (SOT-MRAM) devices on 300mm wafers using CMOS compatible processes. With an unlimited endurance (>5×1010), fast switching speed (210ps), and power consumption as low as 300pJ, the SOT-MRAM devices manufactured in a 300mm line achieve the same or better performance as lab devices. This next-generation MRAM technology targets replacement of L1/L2 SRAM cache memories in high-performance computing applications.

SOT-MRAM has recently emerged as a non-volatile memory technology that promises a high endurance and low-power, sub-ns switching speed. With these properties, it can potentially overcome the limitations of spin-transfer torque MRAM (STT-MRAM) for L1/L2 SRAM cache memory replacement. But so far, SOT-MRAM devices have only been demonstrated in the lab. Imec has now for the first time proven full-scale integration of SOT-MRAM device modules on 300mm wafers using CMOS-compatible processes.

At the core of the SOT-MRAM device is a magnetic tunnel junction in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. Similar as for STT-MRAM operation, writing of the memory is performed by switching the magnetization of this free magnetic layer, by means of a current. In STT-MRAM, this current is injected perpendicularly into the magnetic tunnel junction, and the read and write operation is performed through the same path – challenging the reliability of the device. In an SOT-MRAM device, on the contrary, switching of the free magnetic layer is done by injecting an in-plane current in an adjacent SOT layer – typically made of a heavy metal. Because of the current injection geometry, the read and write path are de-coupled, significantly improving the device endurance and read stability.

Imec has compared SOT and STT switching behavior on one and the same device, fabricated on 300mm wafers. While switching speed during STT-MRAM operation was limited to 5ns, reliable switching down to 210ps was demonstrated during SOT-MRAM operation. The SOT-MRAM devices show unlimited endurance (>5×1010) and operation power as low as 300pJ. In these devices, the magnetic tunnel junction consists of a SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized stack, using beta-phase tungsten (W) for the SOT layer.

“STT-MRAM technology has a high potential to replace L3 cache memory in high-performance computing applications”, says Gouri Sankar Kar, Distinguished Member of Technical Staff at imec. “However, due to the challenging reliability and increased nergy at sub-ns switching speeds, they are unsuitable to replace the faster L1/L2 SRAM cache memories. SOT-MRAM technology will help us to expand MRAM operation into the SRAM application domain. By moving this next-generation MRAM technology out of the lab, we have now demonstrated the maturity of the technology.” Future work will focus on further reducing the energy  consumption, by bringing down current density and by demonstrating field-free switching operation.

These results will be presented at the VLSI Circuits Symposium on June 20 in the session C8 Emerging Memory. Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Micron, Qualcomm, Sony Semiconductor Solutions, TSMC and Western Digital.

FormFactor, Inc. (NASDAQ:FORM), a electrical test and measurement supplier to the semiconductor industry, has extended its Contact Intelligence technology. With Contact Intelligence, FormFactor’s advanced probe systems automatically and autonomously adapt in real time to changes in the testing environment, enabling customers to collect large amounts of RF data faster. As the race to bring 5G devices to market heats up, this addresses the need for higher productivity, to reduce time to market.

FormFactor’s Contact Intelligence technology combines smart hardware design and innovative software algorithms to provide accurate probe-to-pad alignment and electronic recalibrations in engineering labs and many production applications. With the introduction of its new RF solution, FormFactor now has specialized Contact Intelligence applications for RF, DC and Silicon Photonics (SiPh) testing.

FormFactor is best known for it’s probe card business, but with its acquisition of Cascade Microtech in 2016, it became more involved in the design and characterization side of chip-making, including RF and silicon photonic devices (probe cards are primarily used at the end of wafer manufacturing, testing the devices before they are packaged).

Mike Slessor, CEO of FormFactor, said with upcoming infrastructure changes — such as 5G, more mobile communications and IoT — RF is an important place to be. “The Cascade Microtech acquisition gave us an engineering systems business. These are pieces of customized capital equipment that help people very early on in their development and R&D — even early pathfinding — to figure out how their next device is going to perform, to characterize it and to improve its yield,” he said. That systems business grew saw a double digit growth rate last year.

Slessor said the new Contact Intelligence technology is designed to help customers in the systems business get a lot of data faster. He said the push to improve yield, along with new materials and new devices, is driving a tremendous amount of data collection. “What Contact Intelligence really is positioned to do is to help people easily and efficiently collect that data. You can think of it as bringing almost production automation to the engineering lab. We’re helping people do it autonomously over wide ranges of temperatures,” he said. He said it enables engineering tools to be upgraded. Customers can “set it up, push a button and walk away for 48 hours, 96 hours even more and come back and have a hundreds of thousands of individual characterization data points.”

New high frequency ICs, such as 5G (with multiple high frequency bands from sub-6 to more than 70 GHz) and automotive communication devices, need the highest quality process design kits (PDK’s) to ensure working devices at first iteration.

Traditional systems and methods require engineers to invest significant time for recalibration when the system invariably drifts, or to reposition probes with intentional changes in test temperatures. At higher frequencies, calibrations and measurements are more sensitive to probe placement errors and there is more calibration drift, so recalibration is required more often.Over time and temperature, Contact Intelligence automatically makes these adjustments with no operator intervention, resulting in more devices tested in less time, for more accurate PDK’s and faster time to market.

Slessor says the push to 5G brings many design and test challenges due to the significant increase in carrier frequencies – 10 times higher than 4G. “Although there are different bands and the carriers and the countries are still ironing out where they’re going to operate, there are bands as high as 72 gigahertz,” Slessor said. “Electrical signal propagation gets much, much more challenging as you go up in frequency. All kinds of new engineering and physics challenges emerge because you’ve got things that are radiating a good deal of power and there’s a whole bunch of cross talk on the chip. There are all kinds of interesting phenomena that appear that make the designers and the test engineer’s job much more difficult just because of these higher frequencies.”

In an RF front end, instead of modems or radios communicating, a wide variety of a BAW and SAW  filters are used to do the frequency band management and make sure that only the individual bands that are supposed to be used or being effectively used.

In addition to RF, Contact Intelligence is also designed for use in autonomous DC testing and for silicon phototonics.

In DC applications, Contact Intelligence automatically senses preset temperatures, and responds by waiting the correct amount of time until the system is stabilized. This allows lengthy test routines to be conducted over multiple temperatures without an operator present. Contact Intelligence also provides dynamic probe-to-pad alignment, even on pads as small as 25 µm, employing a combination of smart software, probe tip recognition algorithms and advanced programmable positioners.

FormFactor’s integrated SiPh solution allows sub-micron manipulation of optical fibers positioned above the wafer, automatically optimizing fiber coupling position.  Contact Intelligence uses machine vision technology to automate Theta X, Y and Z axis calibrations and alignments enabling measurements out of the box, reducing what used to take days or weeks to a matter of minutes.When combined with autonomous DC and RF, measurement options expand from Optical-Optical to include Photo-Diodes, Optical Modulators and more.

For more information, visit http://www.formfactor.com/contactintelligence.

pSemi™ Corporation (formerly known as Peregrine Semiconductor), a Murata company focused on semiconductor integration, announces the availability of the PE29101 gallium nitride (GaN) field-effect transistor (FET) driver for solid-state light detection and ranging (LiDAR) systems. The PE29101 boasts the industry’s fastest rise times and a low minimum pulse width. This high-speed driver enables design engineers to extract the full performance and switching speed advantages from GaN transistors. In solid-state LiDAR systems, faster switching translates into improved resolution and accuracy in the LiDAR image.

“As GaN is proving its relevance in applications like solid-state LiDAR, design engineers are using pSemi high-speed drivers to maximize the fast switching benefits of GaN,” says Jim Cable, chief technology officer of pSemi. “Because of its rise and fall speed, the PE29101 enables the highest possible resolution imagery—something the industry needs for LiDAR to reach its fullest potential.”

LiDAR operates on the same principles as radar but instead uses pulsed lasers to precisely map surrounding areas. Traditionally used in high-resolution mapping, LiDAR is now used in advanced-driver assistance programs (ADAS) and is widely seen as an enabling technology to fully autonomous vehicles. Furthermore, solid-state LiDAR has emerged as the future leader in the commercialization of LiDAR systems, largely due to its affordability, reliability and compact size compared to mechanical sensors.

In LiDAR systems, the pulse laser’s switching speed and rise time directly impacts the measurement’s accuracy. To improve resolution, the current must switch as quickly as possible through the laser diode. GaN technology offers LiDAR systems superior resolution and a faster response time because of its very low input capacitance and its ability to switch significantly faster than metal-oxide semiconductor field-effect transistors (MOSFETs).

GaN FETs must be controlled by a very fast driver to maximize their fast-switching potential. Increasing the switching speed requires a driver with fast rise times and a low minimum output pulse width. The PE29101 offers these key performance specifications, enabling GaN technology to improve LiDAR resolution.

Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys’ IC Validator has been certified by Samsung Foundry for signoff of all designs using its 7-nanometer (nm) Low Power Plus (LPP) process with Extreme Ultraviolet (EUV) lithography technology. The signoff-certified runsets, including design rule checking (DRC), layout-versus-schematic (LVS) and metal fill technology files, are available immediately from Samsung Foundry. Samsung Foundry 7LPP customers can now use IC Validator’s modern distributed processing in conjunction with runsets from Samsung Foundry to achieve faster physical verification turnaround time with the highest level of accuracy.

“We are building a customer-friendly design enablement ecosystem for 7LPP, our first EUV-based process technology,” said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. “Synopsys’ IC Validator is a great solution for our mutual customers to make the next generation of SoCs, which will lead the fourth industrial revolution with maximized power and performance benefit based on 7LPP process technology.”

IC Validator, a key component of the Synopsys Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (PERC), fill, and DFM enhancement capabilities. IC Validator is architected for high performance and scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than a thousand CPUs.

“Our partnership with Samsung Foundry has been focused on delivering high-quality and high-performance physical signoff solutions for today’s leading-edge designs,” said Christen Decoin, senior director of business development, Design Group at Synopsys. “This certification brings the proven benefits of IC Validator physical verification to Samsung Foundry 7LPP customers.”

Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung Foundry has certified the Synopsys Design Platform with Fusion Technology for 7-nanometer (nm) Low Power Plus (LPP) process with Extreme Ultraviolet (EUV) lithography technology. The Synopsys Design Platform provides comprehensive full-flow 7LPP support for EUV single-exposure-based routing and via stapling to ensure maximum design routability and utilization while minimizing IR-drop. Synopsys’ SiliconSmart® library characterization tool was key to developing the foundation IP used for this certification process and reference flow. Samsung Foundry has certified Synopsys Design Platform tools and the reference flow, which is compatible with the Lynx Design System with scripts for automation and design best practices. The reference flow is available through the Samsung Advanced Foundry Ecosystem (SAFE™) program.

“Built through deep collaboration with Synopsys, this certification and reference flow for our 7LPP process will enable our mutual customers to achieve the best power, performance, and area for their designs,” said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. “Our foundry customers can confidently ramp their designs to volume production on our most advanced EUV-based process using the proven Synopsys Design Platform with Fusion Technology.”

“Our tools and reference flow collaboration with Samsung Foundry is focused on enabling designers to get the optimum quality of results with the highest confidence on Samsung Foundry’s latest 7LPP process with EUV,” said Michael Jackson, corporate vice president of marketing and business development for Synopsys’ Design Group. “This scalable 7LPP reference flow based on the Synopsys Design Platform with Fusion Technology will allow designers to easily achieve their desired design and schedule targets.”

The 64-bit Arm Cortex-A53 processor, based on the ARMv8 architecture, was used for quality of results (QoR) optimization and flow certification. Key tools and features of the Synopsys Design Platform 7LPP reference flow include:

  • IC Compiler II place-and-route: EUV single-exposure-based routing with optimized 7LPP design rule support, and via stapling to ensure maximum design routability and utilization while minimizing IR-drop
  • Design Compiler Graphical RTL synthesis: Correlation, congestion reduction, optimized 7LPP design rule support, and physical guidance for IC Compiler II
  • IC Validator physical signoff: High-performance DRC signoff, LVS-aware short-finder, signoff fill, pattern matching, and unique dirty data analysis with Explorer technology, as well as in-design verification for automated DRC repair and accurate timing-aware metal fill within IC Compiler II
  • PrimeTime timing signoff: Near-threshold ultra-low voltage variation modeling, via variation modeling, and placement rule-aware engineering change order (ECO) guidance
  • StarRC™ parasitic extraction: EUV single pattern-based routing support, and new extraction technologies such as coverage-based via resistance
  • RedHawk™ Analysis Fusion: ANSYS® RedHawk™-driven EM/IR analysis and optimization within IC Compiler II including via insertion and power grid augmentation
  • DFTMAX™ and TetraMAX® II test: FinFET-based, cell-aware, and slack-based transition testing for higher test quality
  • Formality® formal verification: UPF-based equivalence checking with state transition verification

The certified, scalable reference flow compatible with Synopsys’ Lynx Design System is available through the SAFE™ program. The Lynx Design System is a full-chip design environment that includes innovative automation and reporting capabilities to help designers implement and monitor their designs. It includes a production RTL-to-GDSII flow that simplifies and automates many critical implementation and validation tasks, enabling engineers to focus on achieving performance and design goals. The SAFE™ program provides extensively tested process design kits (PDKs) and reference flows (with design methodologies) that are backed by Samsung Foundry’s certification.

WIN Semiconductors Corp (TPEx:3105), the world’s largest pure-play compound semiconductor foundry, has expanded its portfolio of highly integrated GaAs technologies with the release of a new pHEMT technology. The PIH0-03 platform incorporates monolithic PIN and vertical Schottky diodes with WIN’s high performance 0.1um pseudomorphic HEMT process, PP10. This integrated technology, PIH0-03, adds a highly linear vertical Schottky diode with cut-off frequency over 600GHz, as well as multi-function PIN diodes while preserving the state-of-the-art mmWave performance of the PP10 technology. The availability of monolithic PIN and Schottky diodes with a high performance mmWave transistor enables on-chip integration of a wide range of functions, including mixers, temperature/power detecting, limiters, and high frequency switching, and supports power, low noise and optical applications through100 GHz.

This integrated technology provides users with multiple pathways to add on-chip functionality and reduce the overall die count of complex multi-chip modules used in a variety of end-markets. In addition to high frequency switching, the monolithic PIN diodes can be used for low parasitic capacitance ESD protection circuits, and as an on-chip power limiter to protect sensitive LNAs in phased array radars. The vertical Schottky diodes enable numerous detecting and mixing functions and can be combined with the PIN diodes in unique limiter applications.

“Today’s complex systems and highly competitive markets require increased mmWave performance and more functionality per chip. The PIH0-03 platform is the latest example of how WIN Semiconductors is addressing these critical market needs by offering high performance GaAs technologies with new levels of multifunction integration. To meet the ever-increasing demands of next generation mobile user equipment, wireless infrastructure, fiber optics and military applications, WIN Semiconductors continues to commercialize advanced, highly integrated GaAs solutions and provide our customers a clear technology advantage,” said David Danzilio, Senior Vice President of WIN Semiconductors Corp.