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Kulicke and Soffa Industries, Inc. (NASDAQ: KLIC) today announced it has entered into a licensing agreement with Idaho, US based Rohinni LLC (Rohinni), to facilitate the design, commercialization and distribution of next-generation micro and mini LED solutions.

Next-generation LED technologies have the potential to further enhance performance, improve efficiency and reduce the size of existing lighting technologies. Significant high-volume end-markets including automotive, display, consumer electronics and general lighting are anticipated to drive adoption and benefit from this emerging technology. While micro and mini LED benefits are compelling, high-volume production challenges must be addressed prior to widespread market adoption of these emerging lighting solutions.

Rohinni has developed promising solutions that directly address production challenges and have enabled greater design flexibility in end-use applications. In parallel, Rohinni has also established a network of partnerships in several key segments poised to benefit from this technology.

Kulicke & Soffa’s existing market positions, R&D competencies, supply chain and manufacturing capabilities provide scale to further extend Rohinni’s leadership and its effort in driving adoption of new LED technologies.

“K&S has recently taken a much more proactive approach in targeting and identifying complementary partnerships with a clear path to value creation,” stated Chan Pin Chong, Senior Vice President of Wedge Bond and EA/APMR Business Unit. “We are very excited to work together with Rohinni’s talented team to commercialize this high-potential and innovative technology.”

“Our team has spent the past several years developing precise, high-speed placement technologies for micro and mini LED products,” stated Matt Gerber, Rohinni’s CEO. “This agreement with K&S provides capabilities to quickly scale development and global production for our customers. This is really an exciting moment for designers to be able to produce lighting products that haven’t been possible with existing production technologies.”

LCD displays incorporating these latest developments in LED backlighting technologies deliver an unparalleled High-Dynamic-Range (HDR) viewing experience and are significantly brighter than OLEDs. To produce an HDR LCD display with over 10,000 LEDs in a backlight assembly requires a completely new generation of high speed production technologies. With an estimated 220 million square meters of flat-panel displays estimated to be produced in 2018, the growth potential of new backlighting technologies is significant. The unique and highly-complementary contributions of both organizations are anticipated to accelerate the global adoption of leading micro and mini LED-based solutions.

The 64th annual IEEE International Electron Devices Meeting(IEDM), to be held at the Hilton San Francisco Union Square hotel December 1-5, 2018, has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Wednesday, August 1, 2018. Authors are asked to submit four-page camera-ready papers. Accepted papers will be published as-is in the proceedings. A limited number of late-news papers will be accepted. Authors are asked to submit late-news papers announcing only the most recent and noteworthy developments. The late-news submission deadline is September 10, 2018.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics gather to participate in a technical program consisting of more than 220 presentations, along with a variety of panels, special sessions, Short Courses, a supplier exhibit, IEEE/EDS award presentations and other events highlighting leading work in more areas of the field than any other conference.

This year, special emphasis is placed on the following topics:

  • Neuromorphic computing/AI
  • Quantum computing devices and links
  • Devices for RF, 5G, THz and mmWave
  • Advanced memory technologies
  • More-than-Moore devices and integrations
  • Technologies for advanced logic nodes
  • Non-charge-based devices and systems
  • Sensors and MEMS devices
  • Package-device level interactions
  • Electron device simulation and modeling
  • Advanced characterization, reliability and noise
  • Optoelectronics, displays and imaging systems

Overall, papers in the following areas of technology are encouraged:

  • Circuit and Device Interaction
  • Characterization, Reliability and Yield
  • Compound Semiconductor and High-Speed Devices
  • Memory Technology
  • Modeling and Simulation
  • Nano Device Technology
  • Optoelectronics, Displays and Imagers
  • Power Devices
  • Process and Manufacturing Technology
  • Sensors, MEMS and BioMEMS

Further information

For more information, interested persons should visit the IEDM 2018 home page at www.ieee-iedm.org.

Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV.

BY SANTOSH KUMAR, Yole Développement, Lyon-Villeurbanne, France

The memory market is going through a strong growth phase. The total memory market grew by >50% YoY to more than US$125 billion in 2017 from US$79.4 billion in 2016. [1] RAM and NAND dominate the market, representing almost 95 % of standalone memory sales. There is a supply/demand mismatch in the market which is impacting on the ASP of memory devices, and as a result the large memory IDMs are reaping record profits. The memory industry has consolidated with the top five players – Samsung, SKHynix, Micron, Toshiba and Western Digital – accounting for 90% of the market.

The demand for memory is coming from all sectors but the mobile and computing (mainly servers) market is showing particularly strong growth. On average, the DRAM memory capacity per smartphone will rise more than threefold to reach around 6GB by 2022. DRAM cost per smartphone represents >10% of the bill of materials of the phone and is expected to increase further. The NAND capacity per smartphone will increase more than fivefold to reach >150GB by 2022. For servers, the DRAM capacity per unit will increase to a whopping 0.5TB by 2022, and the NAND capacity per SSD for the enterprise market will be in excess of 5TB by 2022. The growth in these markets is led by applications like deep learning, big-data, networking, AR/ VR, and autonomous driving. The automotive market, which traditionally used low density (low-MB) memory, will see the adoption of DRAM memory led by the emerging trend of autonomous driving and in-vehicle infotainment. The NOR flash memory market also saw a resurgence and is expected to grow at an impressive 16% CAGR to reach ~US$4.4 billion by 2022, due to its application in new areas such as AMOLED displays, touch display driver ICs and industrial IoTs.

On the supply side, the consolidation of players, the difficulty in migrating to advanced nodes due to technical challenges, and the need for higher investment to migrate from 2D to 3D NAND, has led to shortfall in both DRAM & NAND flash supply. DRAM players want to retain high ASPs (& high profitability) to justify the huge capex investment for advanced node migration and as such are not inclined to increase capacity. Entry of Chinese memory players will ease the supply side constraint, but it’ll not happen before 2020.

Memory device packaging

There are many variations of memory device packaging. This implies a wide range of packaging technology from the low pin count SOP package to the high pin-count TSV, all depending upon the specific product requirements such as density, performance, cost, etc. We have broadly identified five packaging platforms for memory devices: viz lead frame, wire-bond BGA, flip-chip BGA, WLCSP and TSV, even though in each platform there are many varia- tions and different nomenclature in industry.

The total memory package market is expected to grow at 4.6% CAGR2016-2022 to reach ~US$26 billion by 2022. [1] Wire-bond BGA accounted for more than 80% of the packaging market in dollar terms in 2016. Flip-chips, however, started making inroads in the DRAM memory packaging market and is expected to grow at ~20% CAGR in the next five years to account for more than 10% of the memorypackagingmarket.Currentlytheflip-chipmarket is only around 6% of the total memory packaging market. Flip-chip growth is led by its increased adoption in the DRAM PC/server segment fueled by a high bandwidth requirement.

Currently Samsung has already converted >90% of its DRAM packaging line. SK Hynix have started the conversion and other players will also adopt it in future. At Yole Développement (Yole), we believe that all DDR5 memory for PC/servers will move to flip-chip.

TSV is employed in high bandwidth memory devices requiring high bandwidth with low latency memory chips for high performance computing in various applications. In 2016 the TSV market was <1% of the total memory market. However, it is expected to grow by >30% CAGR to reach ~8% of memory packaging in dollar terms. WLSCP packaging is used in NOR flash and niche memory devices (EEPROMs/EPROM/ROM). It is expected to grow at >10% CAGR, but in terms of value will remain <1% of the market by 2022.

In mobile applications, memory packaging will mainly remain on the wire-bond BGA platform but will start to move into the multi-chip package (ePoP) for high end smartphones.

The main requirement of NAND flash devices is high storage density at low cost. NANDs are stacked using wire bonding to provide high density in a single package. The NAND packaging market is expected to reach ~ US$ 10 billion by 2022. NAND flash packaging will remain on the wire bond BGA platform and will not migrate to flip-chip. Toshiba, however, will start using TSV packaging in NAND devices to increase the data transfer rate for high end applications. Following Toshiba, we believe Samsung and SKHynix will also bring TSV packaged NAND devices into the market.

OSATs account for <20% of the memory packaging business

The total memory packaging market is estimated to have been ~US$20 billion in 2016. There are many OSATs involved in the memory packaging business, and >80% of the packaging (by value) is still done internally by OSATs. The majority of these are small OSATs and have only low-end packaging capability. Global memory IDMs have much experience in packaging, accumulated over years, and have their own internal large capacity. Therefore, there is limited opportunity for OSATs to make inroads into the packaging activity of IDMs. Many Chinese players, however, are entering the memory market with more than US$50 billion investment committed. [1] These new entrants do not have experience in memory assembly / packaging, unlike global IDMs, and they will outsource major packaging activities to OSATs. The flip-chip business for memory packaging will increase to 13% of the total market to reach US$3.5 billion in 2022. This is an opportunity for low-end memory OSATs to invest in flip-chip bumping and assembly capacity. Otherwise they will lose business to the big OSATs with advanced packaging capability.

Conclusion

The memory industry is going through a golden phase with strong demand coming from all sectors, particularly from the mobile and computing (mainly servers) markets.

Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV. Wire-bond BGA still accounts for the bulk of the memory packaging market. However, flip-chip technology will start making inroads in DRAM memory packaging and will grow at 20% CAGR (by revenue) over the next five years, accounting for ~13% of the total memory packaging market by 2022. The memory packaging market is mainly controlled by IDMs. OSATs have limited opportunity to impact IDM packaging activity. Many Chinese players, however, are entering the memory business and, unlike global IDMs, these new players lack experience in memory assembly/packaging and they outsource most of their packaging activity to OSATs.

SANTOSH KUMAR is a Senior Technology and Market Research Analyst at Yole Développement in France.

References

1. Memory Packaging Market and Technology Report 2017, Yole Développement

Technology trends in backplane technology are driving higher gas demand in display manufacturing. Specific gas requirements of process blocks are discussed, and various supply modes are reviewed.

BY EDDIE LEE, Linde Electronics, Hsinchu, Taiwan

Since its initial communalization in the 1990s, active matrix thin-film-transistor (TFT) displays have become an essential and indispensable part of modern living. They are much more than just televisions and smartphones; they are the primary communication and information portals for our day-to- day life: watches (wearables), appliances, advertising, signage, automobiles and more.

There are many similarities in the display TFT manufacturing and semiconductor device manufacturing such as the process steps (deposition, etch, cleaning, and doping), the type of gases used in these steps, and the fact that both display and semiconductor manufacturing both heavily use gases.

However, there are technology drivers and manufacturing challenges that differentiate the two. For semiconductor device manufacturing, there are technology limitations in making the device increasingly smaller. For display manufacturing, the challenge is primarily maintaining the uniformity of glass as consumers drive the demand for larger and thinner displays.

While semiconductor wafer size has maxed because of the challenges of making smaller features uniformly across the surface of the wafer, the size of the display mother glass has grown from 0.1m x 0.1m with 1.1mm thickness to 3m x 3m with 0.5mm thickness over the past 20 years due to consumer demands for larger, lighter, and more cost-effective devices.

As the display mother glass area gets bigger and bigger,so does the equipment used in the display manufacturing process and the volume of gases required. In addition, the consumer’s desire for a better viewing experience such as more vivid color, higher resolution, and lower power consumption has also driven display manufacturers to develop and commercialize active matrix organic light emitting displays (AMOLED).

Technology

Layers of display device

In general, there are two types of displays in the market today: active matrix liquid crystal display (AMLCD) and AMOLED. In its simplicity, the fundamental components required to make up the display are the same for AMLCD and AMOLED. There are four layers of a display device (FIGURE 1): a light source, switches that are the thin-film-transistor and where the gases are mainly used, a shutter to control the color selection, and the RGB (red, green, blue) color filter.

About backplane/TFT

The thin-film-transistors used for display are 2D transitional transistors, which are similar to bulk CMOS before FinFET. For the active matrix display, there is one transistor for each pixel to drive the individual RGB within the pixel. As the resolution of the display grows, the transistor size also reduces, but not to the sub-micron scale of semiconductor devices. For the 325 PPI density, the transistor size is approximately 0.0001 mm2 and for the 4K TV with 80 PPI density, the transistor size is approximately 0.001 mm2.

Technology trends TFT-LCD (thin-film-transistor liquid-crystal display) is the baseline technology. MO / White OLED (organic light emitting diode) is used for larger screens. LTPS / AMOLED is used for small / medium screens. The challenges for OLED are the effect of < 1 micron particles on yield, much higher cost compared to a-Si due to increased mask steps, and moisture impact to yield for the OLED step.

Mobility limitation (FIGURE 2) is one of the key reasons for the shift to MO and LTPS to enable better viewing experience from higher resolution, etc.

The challenge to MO is the oxidation after IGZO metalization / moisture prevention after OLED step, which decreases yield. A large volume of N2O (nitrous oxide) is required for manufacturing, which means a shift in the traditional supply mode might need to be considered.

Although AMLCD displays are still dominant in the market today, AMOLED displays are growing quickly. Currently about 25% of smartphones are made with AMOLED displays and this is expected to grow to ~40% by 2021. OLED televisions are also growing rapidly, enjoying double digit growth rate year over year. Based on IHS data, the revenue for display panels with AMOLED technol- ogies is expected to have a CAGR of 18.9% in the next five years while the AMLCD display revenue will have a -2.8% CAGR for the same period with the total display panel revenue CAGR of 2.5%. With the rapid growth of AMOLED display panels, the panel makers have accel- erated their investment in the equipment to produce AMOLED panels.

Types of backplanes

There are three types of thin-film-transistor devices for display: amorphous silicon (a-Si), low temperature polysilicon (LTPS), and metal oxide (MO), also known as transparent amorphous oxide semiconductor (TAOS). AMLCD panels typically use a-Si for lower-resolution displays and TVs while high-resolution displays use LTPS transistors, but this use is mainly limited to small and medium displays due to its higher costs and scalability limitations. AMOLED panels use LTPS and MO transistors where MO devices are typically used for TV and large displays (FIGURE 3).

How gases are used

This shift in technology also requires a change in the gases used in production of AMOLED panels as compared with the AMLCD panels. As shown in FIGURE 4, display manufacturing today uses a wide variety of gases.

These gases can be categorized into two types: Electronic Specialty gases (ESGs) and Electronic Bulk gases (EBGs) (FIGURE 5). Electronic Specialty gases such as silane, nitrogen trifluoride, fluorine (on-site generation), sulfur hexafluoride, ammonia, and phosphine mixtures make up 52% of the gases used in the manufacture of the displays while the Electronic Bulk gases–nitrogen, hydrogen, helium, oxygen, carbon dioxide, and argon – make up the remaining 48% of the gases used in the display manufacturing.

Key usage drivers

The key ga susage driver in the manufacturing of displays is PECVD (plasma-enhanced chemical vapor deposition), which accounts for 75% of the ESG spending, while dry etch is driving helium usage. LTPS and MO transistor production is driving nitrous oxide usage. The ESG usage for MO transistor production differs from what is shown in FIGURE 4: nitrous oxide makes up 63% of gas spend, nitrogen trifluoride 26%, silane 7%, and sulfur hexafluoride and ammonia together around 4%. Laser gases are used not only for lithography, but also for excimer laser annealing application in LTPS.

Silane: SiH4 is one of the most critical molecules in display manufacturing. It is used in conjunction with ammonia (NH3) to create the silicon nitride layer for a-Si transistor, with nitrogen (N2) to form the pre excimer laser anneal a-Si for the LTPS transistor, or with nitrous oxide (N2O) to form the silicon oxide layer of MO transistor.

Nitrogen trifluoride: NF3 is the single largest electronic material from spend and volume standpoint for a-Si and LTPS display production while being surpassed by N2O for MO production. NF3 is used for cleaning the PECVD chambers. This gas requires scalability to get the cost advantage necessary for the highly competitive market.

Nitrous oxide: Used in both LTPS and MO display production, N2O has surpassed NF3 to become the largest electronic material from spend and volume standpoint for MO production. N2O is a regional and localized product due to its low cost, making long supply chains with high logistic costs unfeasible. Averaging approximately 2 kg per 5.5 m2 of mother glass area, it requires around 240 tons per month for a typical 120K per month capacity generation 8.5 MO display production. The largest N2O compressed gas trailer can only deliver six tons of N2O each time and thus it becomes both costly and risky
for MO production.

Nitrogen: For a typical large display fab, N2 demand can be as high as 50,000 Nm3/hour, so an on-site generator, such as the Linde SPECTRA-N® 50,000, is a cost-effective solution that has the added benefit of an 8% reduction in CO2 (carbon dioxide) footprint over conventional nitrogen plants.

Helium: H2 is used for cooling the glass during and after processing. Manufacturers are looking at ways to decrease the usage of helium because of cost and availability issues due it being a non-renewable gas.

Gas distribution at the fab

N2 On-site generators: Nitrogen is the largest consumed gas at the fab, and is required to be available before the first tools are brought to the fab. Like major semiconductor fabs, large display fabs require very large amounts of nitrogen, which can only be economically supplied by on-site plants.

Cryogenic liquid truck trailers: Oxygen, argon, and carbon dioxide are produced at off-site plants and trucked short distances as cryogenic liquids in specialty vacuum-insulated tankers.
Compressed gas truck trailers: Other large volume gases like hydrogen and helium are supplied over longer distances in truck or ISO-sized tanks as compressed gases.

Individual packages: Specialty gases are supplied in individual packages. For higher volume materials like silane and nitrogen trifluoride, these can be supplied in large ISO packages holding up to 10 tons. Materials with smaller requirements are packaged in standard gas cylinders.

Blended gases: Laser gases and dopants are supplied as blends of several different gases. Both the accuracy and precision of the blended products are important to maintain the display device fabrication operating within acceptable parameters.

In-fab distribution: Gas supply does not end with the delivery or production of the material of the fab. Rather, the materials are further regulated with additional filtration, purification, and on-line analysis before delivery to individual production tools.

Conclusion

The consumer demand for displays that offer increas- ingly vivid color, higher resolution, and lower power consumption will challenge display makers to step up the technologies they employ and to develop newer displays such as flexible and transparent displays. The transistors to support these new displays will either be LTPS and / or MO, which means the gases currently being used in these processes will continue to grow. Considering the current a-Si display production, the gas consumption per area of the glass will increase by 25% for LTPS and ~ 50% for MO productions.

To facilitate these increasing demands, display manufacturers must partner with gas suppliers to identify which can meet their technology needs, globally source electronic materials to provide customers with stable and cost- effective gas solutions, develop local sources of electronic materials, improve productivity, reduce carbon footprint, and increase energy efficiency through on-site gas plants. This is particularly true for the burgeoning China display manufacturing market, which will benefit from investing in on-site bulk gas plants and collaboration with global materials suppliers with local production facilities for high-purity gas and chemical manufacturing.

Nanostructures are the holy grail of new materials.

The wonder material graphene, for example, is a single layer of carbon atoms arranged in a hexagonal pattern that, because of its conductivity, flexibility, transparency and strength, has the potential to create more efficient solar cells, smaller and faster electric circuits and microchips, transparent displays, and high density capacitors and batteries.

According to Xiaoji Xu (https://chemistry.cas2.lehigh.edu/faculty/xiaoji-xu-0), assistant professor in the Department of Chemistry at Lehigh University, another quality that makes nanomaterials like graphene so special is their ability to generate a physics phenomenon called a polariton.

Polaritons are quasiparticles resulting from a strong coupling of electromagnetic waves with an electric or magnetic dipole-carrying excitation–referred to by some as a light-matter coupling. Polaritons make it possible for nanostructures to confine–and compress–light around the material.

The ability to compress light is key to scaling down devices for future optical communications and computing. It could also lead to sensing at a scale below one nanometer, important for achieving biomedical advances in disease detection, prevention and treatment.

The challenge for people studying these materials, says Xu, is how to reveal–and characterize–the polaritons at the nanoscale because no conventional microscope can do that.

Now Xu and his team (https://xu-lab.com/) have found a way to reveal the 3-D shape of the polariton interaction around a nanostructure. Their technique improves upon the common spectroscopic imaging technique known as scattering-type scanning near-field optical microscopy (s-SNOM). The team’s method, called peak force scattering-type scanning near-field optical microscopy (PF-SNOM), works through a combination of peak force tapping mode and time-gated light detection. The researchers have detailed their work in an article called: “Tomographic and multimodal scattering-type scanning near-field optical microscopy with peak force tapping mode” (DOI: 10.1038/s41467-018-04403-5) published online on May 21st 2018 in Nature Communications. In addition to Xu, the paper’s co-authors include Haomin Wang, Le Wang and Devon S. Jakob, PhD students in Xu’s lab.

In the paper, the authors state: “PF-SNOM enables direct sectioning of vertical near-field signals from a sample surface for both three-dimensional near-field imaging and spectroscopic analysis. Tip-induced relaxation of surface phonon polaritons are revealed and modeled by considering tip damping.”

According to the researchers, PF-SNOM also offers an improved spatial resolution of five nanometers, rather than the typical ten nanometers offered by the traditional s-SNOM.

“Our technique could be beneficial to scientists studying nanostructures enabling them to better understand how the electrical field is distributed around a given nanostructure,” says Xu.

Their PF-SNOM characterization method is not only more direct than existing techniques, it can also simultaneously obtain the polaritonic, mechanical and electrical information.

With one measurement, explains Xu, multiple modes of information can be obtained–a unique advantage.

The development of PF-SNOM grew out of the team’s study of gap mode, when two plasmonic structures approach within a few nanometers there is a huge enhancement of the plasmon intensity in the gap between the two structures as energy is transferred from one structure to the other. With their ability to narrow this gap mode response in simulations, the researchers decided to try to extend it to non-gap mode – when increasing the distance between the atomic force microscopy (AFM) probe tip and the sample.

“Using an AFM tip, we measured the scattered light as a function of tip-sample distance,” explains Wang, a PhD student in Xu’s lab and a co-author on the paper. “We then gathered information at different tip-sample distances and combined all this layered information together to obtain the tomographic image and reveal the 3-D polariton structure.”

Interestingly, when the team began their experiments they expected a different outcome. However, during the simulations, they observed a special shape of light scattering and saw there was an obvious gap mode enhancement.

“It turned out that we could section the light in different tip-samples distances and use those signals to view the near-field response at different layers and in vertical directions,” says Wang.

He adds: “Though this work was done with infrared, in principle it could also be extended to other frequencies, such as visible and terahertz.”

Inorganic semiconductors such as silicon are indispensable in modern electronics because they possess tunable electrical conductivity between that of a metal and that of an insulator. The electrical conductivity of a semiconductor is controlled by its band gap, which is the energy difference between its valence and conduction bands; a narrow band gap results in increased conductivity because it is easier for an electron to move from the valence to the conduction band. However, inorganic semiconductors are brittle, which can lead to device failure and limits their application range, particularly in flexible electronics.

Inorganic semiconducting crystals generally tend to fail in a brittle manner. This is true for zinc sulfide (ZnS); ZnS crystals (A) show catastrophic fracture after mechanical tests under ordinary light-exposure environments (B). However, we found out that ZnS crystals can be plastically deformed up to a deformation strain of εt = 45 % when deformed along the [001] direction in complete darkness even at room temperature (C). Moreover, the optical band gap of the deformed ZnS crystals decreased by 0.6 eV after deformation. Credit: Atsutomo Nakamura

Inorganic semiconducting crystals generally tend to fail in a brittle manner. This is true for zinc sulfide (ZnS); ZnS crystals (A) show catastrophic fracture after mechanical tests under ordinary light-exposure environments (B). However, we found out that ZnS crystals can be plastically deformed up to a deformation strain of εt = 45 % when deformed along the [001] direction in complete darkness even at room temperature (C). Moreover, the optical band gap of the deformed ZnS crystals decreased by 0.6 eV after deformation. Credit: Atsutomo Nakamura

A group at Nagoya University recently discovered that an inorganic semiconductor behaved differently in the dark compared with in the light. They found that crystals of zinc sulfide (ZnS), a representative inorganic semiconductor, were brittle when exposed to light but flexible when kept in the dark at room temperature. The findings were published in Science.

“The influence of complete darkness on the mechanical properties of inorganic semiconductors had not previously been investigated,” study coauthor Atsutomo Nakamura says. “We found that ZnS crystals in complete darkness displayed much higher plasticity than those under light exposure.”

The ZnS crystals in the dark deformed plastically without fracture until a large strain of 45%. The team attributed the increased plasticity of the ZnS crystals in the dark to the high mobility of dislocations in complete darkness. Dislocations are a type of defect found in crystals and are known to influence crystal properties. Under light exposure, the ZnS crystals were brittle because their deformation mechanism was different from that in the dark.

The high plasticity of the ZnS crystals in the dark was accompanied by a considerable decrease in the band gap of the deformed crystals. Thus, the band gap of ZnS crystals and in turn their electrical conductivity may be controlled by mechanical deformation in the dark. The team proposed that the decreased band gap of the deformed crystals was caused by deformation introducing dislocations into the crystals, which changed their band structure.

“This study reveals the sensitivity of the mechanical properties of inorganic semiconductors to light,” coauthor Katsuyuki Matsunaga says. “Our findings may allow development of technology to engineer crystals through controlled light exposure.”

The researchers’ results suggest that the strength, brittleness, and conductivity of inorganic semiconductors may be regulated by light exposure, opening an interesting avenue to optimize the performance of inorganic semiconductors in electronics.

Pure quartz glass is highly transparent and resistant to thermal, physical, and chemical impacts. These are optimum prerequisites for use in optics, data technology or medical engineering. For efficient, high-quality machining, however, adequate processes are lacking. Scientists of Karlsruhe Institute of Technology (KIT) have developed a forming technology to structure quartz glass like a polymer. This innovation is reported in the journal Advanced Materials.

“It has always been a big challenge to combine highly pure quartz glass and its excellent properties with a simple structuring technology,” says Dr. Bastian E. Rapp, Head of the NeptunLab interdisciplinary research group of KIT’s Institute of Microstructure Technology (IMT). Rapp and his team develop new processes for industrial glass processing. “Instead of heating glass up to 800 °C for forming or structuring parts of glass blocks by laser processing or etching, we start with the smallest glass particles,” says the mechanical engineer. The scientists mix glass particles of 40 nanometers in size with a liquid polymer, form the mix like a sponge cake, and harden it to a solid by heating or light exposure. The resulting solid consists of glass particles in a matrix at a ratio of 60 to 40 vol%. The polymers act like a bonding agent that retains the glass particles at the right locations and, hence, maintains the shape.

This “Glassomer” can be milled, turned, laser-machined or processed in CNC machines just like a conventional polymer. “The entire range of polymer forming technologies is now opened for glass,” Rapp emphasizes. For fabricating high-performance lenses that are used in smartphones among others, the scientists produce a Glassomer rod, from which the lenses are cut. For highly pure quartz glass, the polymers in the composite have to be removed. For doing so, the lenses are heated in a furnace at 500 to 600 °C and the polymer is burned fully to CO2. To close the resulting gaps in the material, the lenses are sintered at 1300 °C. During this process, the remaining glass particles are densified to pore-free glass.

This forming technology enables production of highly pure glass materials for any applications, for which only polymers have been suited so far. This opens up new opportunities for the glass processing industry as well as for the optical industry, microelectronics, biotechnology, and medical engineering. “Our process is suited for mass production. Production and use of quartz glass are much cheaper, more sustainable, and more energy-efficient than those of a special polymer,” Rapp explains.

This is the third innovation for the processing of quartz glass that has been developed by NeptunLab on the basis of a liquid glass-polymer mixture. In 2016, the scientists already succeeded in using this mixture for molding. In 2017, they applied the mixture for 3D printing and demonstrate its suitability for additive manufacture. Within the framework of the “NanomatFutur” competition for early-stage researchers, the team was funded with EUR 2.8 million by the Federal Ministry of Education and Research from 2014 to 2018. A spinoff now plans to commercialize Glassomer.

Among the chief complaints for smartphone, laptop and other battery-operated electronics users is that the battery life is too short and–in some cases–that the devices generate heat. Now, a group of physicists led by Deepak K. Singh, associate professor of physics and astronomy at the University of Missouri, has developed a device material that can address both issues. The team has applied for a patent for a magnetic material that employs a unique structure–a “honeycomb” lattice that exhibits distinctive electronic properties.

The left shows the atomic force micrograph, exhibiting honeycomb structure pattern behind a magnetic device. Inset shows the schematic of current flow direction. On the right: electrical data reveals diode-type behavior of current flowing in one direction. Inset shows that the dissipative power is of the order of nano-watt in the current flowing direction, which is at least three orders of magnitude smaller than the semiconductor diode. Credit: Deepak Singh

The left shows the atomic force micrograph, exhibiting honeycomb structure pattern behind a magnetic device. Inset shows the schematic of current flow direction. On the right: electrical data reveals diode-type behavior of current flowing in one direction. Inset shows that the dissipative power is of the order of nano-watt in the current flowing direction, which is at least three orders of magnitude smaller than the semiconductor diode. Credit: Deepak Singh

“Semiconductor diodes and amplifiers, which often are made of silicon or germanium, are key elements in modern electronic devices,” said Singh, who also serves as the principal investigator of the Magnetism and Superconductivity Research Laboratory at MU. “A diode normally conducts current and voltage through the device along only one biasing direction, but when the voltage is reversed, the current stops. This switching process costs significant energy due to dissipation, or the depletion of the power source, thus affecting battery life. By substituting the semiconductor with a magnetic system, we believed we could create an energetically effective device that consumes much less power with enhanced functionalities.”

Singh’s team developed a two-dimensional, nanostructured material created by depositing a magnetic alloy, or permalloy, on the honeycomb structured template of a silicon surface. The new material conducts unidirectional current, or currents that only flow one way. The material also has significantly less dissipative power compared to a semiconducting diode, which is normally included in electronic devices.

The magnetic diode paves the way for new magnetic transistors and amplifiers that dissipate very little power, thus increasing the efficiency of the power source. This could mean that designers could increase the life of batteries by more than a hundred-fold. Less dissipative power in computer processors could also reduce the heat generated in laptop or desktop CPUs.

“Although more works need to be done to develop the end product, the device could mean that a normal 5-hour charge could increase to more than a 500-hour charge,” Singh said. “The device could also act as an ‘on/off switch’ for other periphery components such as closed-circuit cameras or radio frequency attenuators, which reduces power flowing through a device. We have applied for a U.S. patent and have begun the process of incorporating a spin-off company to help us take the device to market.”

The proposed startup company associated with this research, highlights the university’s impact on the state’s economic development efforts, including commercialization of research conducted at Mizzou, workforce development and job growth, quality of life improvements for residents, and attracting corporations and businesses to the state. Companies commercializing MU technologies have secured hundreds of millions of dollars in investments and grants to advance their commercialization efforts. In 2017, the Office of Technology Management and Industry Relations reported that 31 U.S. patents were issued to members of the MU community.

A Columbia University-led international team of researchers has developed a technique to manipulate the electrical conductivity of graphene with compression, bringing the material one step closer to being a viable semiconductor for use in today’s electronic devices.

By compressing layers of boron nitride and graphene, researchers were able to enhance the material's band gap, bringing it one step closer to being a viable semiconductor for use in today's electronic devices. Credit: Philip Krantz

By compressing layers of boron nitride and graphene, researchers were able to enhance the material’s band gap, bringing it one step closer to being a viable semiconductor for use in today’s electronic devices. Credit: Philip Krantz

“Graphene is the best electrical conductor that we know of on Earth,” said Matthew Yankowitz, a postdoctoral research scientist in Columbia’s physics department and first author on the study. “The problem is that it’s too good at conducting electricity, and we don’t know how to stop it effectively. Our work establishes for the first time a route to realizing a technologically relevant band gap in graphene without compromising its quality. Additionally, if applied to other interesting combinations of 2D materials, the technique we used may lead to new emergent phenomena, such as magnetism, superconductivity, and more.”

The study, funded by the National Science Foundation and the David and Lucille Packard Foundation, appears in the May 17 issue of Nature.

The unusual electronic properties of graphene, a two-dimensional (2D) material comprised of hexagonally-bonded carbon atoms, have excited the physics community since its discovery more than a decade ago. Graphene is the strongest, thinnest material known to exist. It also happens to be a superior conductor of electricity – the unique atomic arrangement of the carbon atoms in graphene allows its electrons to easily travel at extremely high velocity without the significant chance of scattering, saving precious energy typically lost in other conductors.

But turning off the transmission of electrons through the material without altering or sacrificing the favorable qualities of graphene has proven unsuccessful to-date.

“One of the grand goals in graphene research is to figure out a way to keep all the good things about graphene but also create a band gap – an electrical on-off switch,” said Cory Dean, assistant professor of physics at Columbia University and the study’s principal investigator. He explained that past efforts to modify graphene to create such a band gap have degraded the intrinsically good properties of graphene, rendering it much less useful. One superstructure does show promise, however. When graphene is sandwiched between layers of boron nitride (BN), an atomically-thin electrical insulator, and the two materials are rotationally aligned, the BN has been shown to modify the electronic structure of the graphene, creating a band gap that allows the material to behave as a semiconductor – that is, both as an electrical conductor and an insulator. The band gap created by this layering alone, however, is not large enough to be useful in the operation of electrical transistor devices at room temperature.

In an effort to enhance this band gap, Yankowitz, Dean, and their colleagues at the National High Magnetic Field Laboratory, the University of Seoul in Korea, and the National University of Singapore, compressed the layers of the BN-graphene structure and found that applying pressure substantially increased the size of the band gap, more effectively blocking the flow of electricity through the graphene.

“As we squeeze and apply pressure, the band gap grows,” Yankowitz said. “It’s still not a big enough gap – a strong enough switch – to be used in transistor devices at room temperature, but we have gained a fundamentally better understanding of why this band gap exists in the first place, how it can be tuned, and how we may target it in the future. Transistors are ubiquitous in our modern electronic devices, so if we can find a way to use graphene as a transistor it would have widespread applications.”

Yankowitz added that scientists have been conducting experiments at high pressures in conventional three-dimensional materials for years, but no one had yet figured out a way to do them with 2D materials. Now, researchers will be able to test how applying various degrees of pressure changes the properties of a vast range of combinations of stacked 2D materials.

“Any emergent property that results from the combination of 2D materials should grow stronger as the materials are compressed,” Yankowitz said. “We can take any of these arbitrary structures now and squeeze them and the strength of the resulting effect is tunable. We’ve added a new experimental tool to the toolbox we use to manipulate 2D materials and that tool opens boundless possibilities for creating devices with designer properties.”

Synopsys, Inc. (Nasdaq: SNPS) today announced that GLOBALFOUNDRIES (GF) has certified the Synopsys IC Validator tool for physical signoff on the GF 14LPP process technology. With this signoff certification, designers can take advantage of IC Validator’s speed and scalability, while ensuring a high level of manufacturability compliance and maximum yield. The certified runsets, including DRC, LVS, and metal fill technology files, are available today from GF.

“Signoff certification of IC Validator is an essential step in supporting our mutual customers for physical signoff,” said Jai Durgam, vice president, Customer Design Enablement at GLOBALFOUNDRIES. “Synopsys worked closely with us on an extensive tool certification and runset qualification for IC Validator on our 14LPP process technology. Our foundry customers can now use IC Validator’s fast analysis to maximize the high-performance and power efficiency benefits of our 14LPP process technology. In addition, we are actively working to expand IC Validator signoff verification for all of our advanced processes.”

IC Validator, a key component of the Synopsys Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, programmable electrical rule checks (PERC), dummy metal fill, and DFM enhancement capabilities. IC Validator is architected for high performance and scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. It uses both multi-threading and distributed processing over multiple machines to provide scalability benefits that extend to more than a thousand CPUs.

“Manufacturing complexity at advanced nodes challenges designers to deliver within schedule,” said Christen Decoin, senior director of business development, Design Group at Synopsys. “Our close collaboration with GLOBALFOUNDRIES ensures designers have timely access to performance-optimized runsets. The runsets, in concert with IC Validator’s massively parallel architecture’s scalability, provide designers a fast and accurate path to physical signoff closure.”