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NUST MISIS scientists have finally found out why a material that could potentially become the basis for ultra-fast memory in new computers is formed. Professor Petr Karpov and Serguei Brazovskii, both researchers at NUST MISIS, have managed to develop a theory which explains the mechanism of the latent state formation in layered tantalum disulfide, one of the most promising materials for modern microelectronics. The latent state of matter (which will be discussed further) was discovered by Serguei Brazovskii with a group of experimenters from Slovenia in 2014. The experiment that led to the beginning of the “boom” for the studies of layered materials lied in the fact that the tantalum disulfide sample, which was less than 100 nanometers big, was affected by an ultrashort laser (an electric pulse). The state of the material changed because of pulses in the irradiated area, and the sample became either a conductor of dielectrics or vice versa, depending on the experimenters’ wish. The switching even occurred in just one picosecond –a far quicker rate than in the “fastest” materials used as storage mediums in modern computers. That condition didn’t fade after exposure, but instead persisted. Accordingly, the material has become a potential candidate for the basis of the next generation of information data mediums.

Serguei Brazovskii is currently serving as the leading scientist of the “Theory of locally adjustable electronic states in layered materials” project at NUST MISIS, as well as working as a leading scientist at the University of Paris-Sud (Orsay, France) Laboratory of Theoretical Physics and Statistical Models.

Professor Petr Karpov, engineer at the NUST MISIS Department for Theoretical Physics and Quantum Technologies, explained the root of the matter, “The ‘boom’ in the study of layered tantalum disulfide happened, as well as a number of articles on this topic in different journals being published, after our colleagues from Slovenia discovered the latent state of the matter, unattainable in conventional (thermodynamic) phase transitions. However, most of these works were experimental, and the theory lagged behind. That is, the state could have been received but why did it turn out [that way]? What were the mechanisms of its formation? What its nature is in general, remained unclear. Why doesn’t the system return to its original state, continuing to remain in modified form indefinitely? In this article we tried to find the theoretical justification of the occurring processes”.

Tantalum disulfide belongs to a special group of conductor materials in which so-called charge-density waves are formed. This means that in addition to the natural peaks of electron density caused by the presence of an atom, there is also another periodicity that is several times greater than the distance between the adjacent atoms of the crystal lattice. In this case, the degree of that periodicity is the “root of thirteen”, so there is quite a large difference.

Picture A shows a layer of tantalum atoms. The period between the “superpeaks” is marked with a red arrow. The state of the different sites in the tantalum disulfide layer differ from each other in the fact that the maximum electron density is centered on tantalum atoms. The red ones show one state, while the “blue” and “white” ones show other states.

The work of NUST MISIS scientists consisted of constructing and studying a universal theoretical model that could describe the most important and intriguing property of the newly discovered state: the formation and transformation of nano-structural mosaics (pic. b). Some of the metal atoms fly out of the lattice after the processing of electrical impulses in the sample of layered tantalum disulfide, and that causes defects — charged vacancies in the electronic crystal.

However, instead of keeping a maximum distance from each other, the charges are “smeared” along the linear chains of tantalum atoms, forming boundaries of zones with different states of tantalum atoms. These “domains” then essentially chain up, connected to a global network. Manipulating these nanosets is the reason for the switching and memory effects observed in the material.

“We tried to find out why similar charges in such a structure do not repel, but, in fact, are attracted to each other. It turned out that this process is energetically more profitable than the maximum removal of positive charges from each other because the formation of fractional charged domain walls minimizes the charge of the constituent wall of atoms, which is why the domain system becomes more stable. This is completely confirmed by the experiment, and the whole crystal can be taken to such a state with a domain mosaic and globules dividing the walls”, — added Petr Karpov.

According to the scientists, thanks to the development of this theory, it is possible to confirm that the domain state of tantalum disulfide can be used for long-term storage and super-fast operation of information.

Graphene, a two-dimensional lattice of carbon atoms, has attracted enormous interest from a broad base of the research community for more than one decade. Graphene nanoribbons (GNRs), narrow strips of graphene, being quasi one-dimensional, possess complementary features relative to their two-dimensional counterpart of graphene sheets. Based on theoretical calculations, GNRs’ electrical properties can be controlled by the width and edge configuration and they can vary from being metallic to semiconducting. The physical properties of the GNRs depend significantly on the size and number of layers, which in turn depend on their synthesis method. There are three major approaches for synthesis of GNRs: cutting graphene by different lithographic techniques; bottom-up synthesis from polycyclic molecules; and unzipping of carbon nanotubes (CNTs). While the bottom-up method provides a route to precise edge control, and the lithographic method can afford GNRs with precise placement, the unzipping method has the advantage of mass-production on a large scale.

MWCNT unzipping methods can be classified into four major types: the reductive-intercalation-assisted approach, the oxidative unzipping, the electrochemical unzipping, and the group of methods that can be denoted as miscellaneous. The first approach is based on the well-known ability of alkali metals to intercalate graphite with expansion in the Z-axis direction. Being applied toward MWCNTs, such lattice expansion induces extreme stress within the concentric walls, resulted in the bursting, or longitudinal opening, of the tubes. The resulted GNRs are highly conductive, but they remain multi-layered and foliated. Due to the attraction between the surfaces, they do not exfoliate to single-layer ribbons.

The oxidative approach involves treatment of MWCNTs in acidic oxidative media with the formulation almost identical to that used in production of graphene oxide (GO) from graphite by the Hummers method. The resulting product is graphene oxide nanoribbons (GONRs). Unlike GNRs obtained by the reductive-intercalation method, GONRs easily exfoliate in aqueous solution, and they can be obtained as single-layered structures. A reaction mechanism for oxidative unzipping was proposed by Kosynkin et al.1 Invoking the classical oxidation of the alkenes by permanganate in acids, the first step is the formation of manganate ester on a C-C bond, and the second step is the rupture of the C-C bond with formation of ketones at the newly formed edges. This mechanism was further developed in the theoretical work by Rangel et al.2 The original synthesis spawned numerous studies on oxidative unzipping of MWCNTs. In many reports, the unzipping process was denoted as “chemical” as opposed to the “intercalation-exfoliation”, indicating that the permanganate-induced oxidative mechanism has been commonly accepted, and was even suggested toward unzipping SWCNTs.

The newly proposed mechanism was based on the Lab’s competences on the studies of the mechanism of GO formation of graphite that involves three consecutive steps: (a) intercalation of graphite by sulfuric acid with formation of a stage-1 H2SO4-graphite intercalation compound (GIC); (b) conversion of stage-1 H2SO4-GIC into pristine GO, and (c) exfoliation of GO to single-layer sheets upon exposure to water. Thus, under given conditions, formation of stage-1 H2SO4-GIC is unavoidable for any graphitic material. Subsequently, the mechanism of the oxidative unzipping of MWCNTs might be also intercalation-driven. If this is correct, one should be able to stop the reaction after the first intercalation-unzipping step before the second oxidation step proceeds. If attained, this will afford unzipped but not oxidized or minimally oxidized products possessing properties similar to reductively unzipped GNRs obtained by potassium or sodium-potassium metal intercalation. In this work, the Lab investigated the impact of the two key parameters, the KMnO4/MWCNT ratio, and the time of reaction on the structure and composition of as-obtained GNR products, and derived a revised and more complete understanding of the unzipping process.

The researchers demonstrated that the mechanism of the oxidative unzipping of MWCNTs is indeed intercalation-driven. The overall unzipping process involves the same three steps as in the course of GO production from graphite by the Hummers and modified Hummers methods: intercalation, oxidation, and exfoliation. With MWCNTs, the intercalation is associated with simultaneous unzipping. At low KMnO4/MWCNT ratios, one can obtain GNRs with characteristics similar to those produced by reductive unzipping. 0.12 wt equiv KMnO4 is the threshold ratio sufficient for almost complete unzipping, with only small amounts of covalent oxidation. Controlling the KMnO4/MWCNT ratio and time of reaction allows one to produce GNRs with the properties varying in a broad continuous range from multi-layered graphenic GNRs through single-layered GONRs. Thus, the team answered several questions that remained open in the field of unzipping MWCNTs, such as the reason why the inner-most walls of the nanotubes remain zipped. The intercalation-driven reaction mechanism provides a rationale for the impossibility of unzipping single-wall and few-wall CNTs, and aids in a reevaluation of the data from the oxidative unzipping process.

Toshiba Electronic Devices & Storage Corporation (“Toshiba”) has released two new MOSFETs “TPHR7904PB” and “TPH1R104PB” housed in the small low-resistance SOP Advance (WF) package, as new additions to the automotive 40V N-channel power MOSFET series. Mass production starts today.

Fabricated using the latest ninth generation trench U-MOS IX-H process and housed in a small low-resistance package, the new MOSFETs provide low on-resistance and thus help reduce conduction loss. The U-MOS IX-H design also lowers switching noise compared with Toshiba’s previous design (U-MOS IV), helping to reduce EMI (Electromagnetic Interference).

The SOP Advance (WF) package adopts a wettable flank terminal structure, which enables AOI (Automated Optical Inspection) after soldering.

Applications

  • Electric power steering (EPS)
  • Load switches
  • Electric pumps

Features

  • Provides a maximum on-resistance, RDS(ON)max, of 0.79 mΩ from the use of the U-MOS IX-H process and the SOP Advance(WF) package.
  • Low-noise characteristics reduce electromagnetic interference (EMI).
  • Available in a small low-resistance package with a wettable flank terminal structure.

Main Specifications

(Unless otherwise specified, @Ta=25°C)

Part Number

Drain-Source
voltage
VDSS
(V)

Drain
current
(DC)
ID
(A)

Drain-Source
on-resistance

RDS(ON) max.(mΩ)

Built-in
Zener Diode
between
Gate-Source

 Series

@VGS=6V

@VGS=10V
TPH1R104PB 40 120 1.96 1.14 No U-MOS IX
TPHR7904PB 150 1.3 0.79 No U-MOS IX

What makes the Vivo X20 Plus UD smartphone so important is that it is the first smartphone to use Synaptics’ under-display fingerprint sensor, and it has the potential to bite into Apple’s face recognition technology, announced the Teardowns service of ABI Research, a market-foresight advisory firm providing strategic guidance on the most compelling transformative technologies.

(PRNewsfoto/ABI Research)

(PRNewsfoto/ABI Research)

Traditional fingerprint sensors are either embedded under the home key on the front of the mobile phone or on the back of the phone. Placing the fingerprint sensor under the display on the front of the mobile phone should allow for a borderless display on three sides of the display. The top still requires room for the front camera, proximity sensor, and receiver, etc. However, Vivo did not take full advantage of the new fingerprint technology from Synaptics. Vivo retained a significant border below the display along the bottom of the phone.

“Vivo may have been cautious to fully commit to the new technology and left room to fall back to a traditional sensor below the display,” said Jim Mielke, ABI Research’s vice president of the Teardowns service. “The performance of this first implementation does warrant some caution as the sensor seemed less responsive and required increased pressure to unlock the phone.”

Smartphone manufacturers are continually trying to achieve the truly borderless phone, and currently there are only three ways to achieve and still maintain biometric security: fingerprint sensor on the back of the phone, fingerprint sensor under the display, and facial/retina-based recognition. Despite the non-optimal capabilities, the Vivo X20 Plus UD is well ahead of Apple’s face recognition technology.

“Face recognition on smartphones is five times easier to spoof than fingerprint recognition,” stated ABI Research Industry Analyst Dimitrios Pavlakis (“Executive Foresights: Did Apple Miss the Bus – The Display – Integrated Fingerprint Sensor Gives the Industry a Much-Needed Push“). “Despite the decision to forgo its trademark sapphire sensor in the iPhone X in favor of face recognition (FaceID,) Apple may be now forced to return to fingerprints in the next iPhone,” added Pavlakis.

Fingerprint sensors are increasingly becoming more relevant with a host of new banking, financial institution and payment service providers getting behind the technology.

Vivo, a 9-year-old company based in China, was smart to partner with California-based Synaptics, which has 30-plus years of experience in the “human interface revolution” by offering touch, display and biometrics products.

ABI Research’s Teardowns reports feature ultra-high-resolution imaging, pinpoint power measurements, detailed parts list with fully costed BOMs (bill of materials), block diagrams and x-rays. ABI Research performs the highest resolution imagery in the teardown industry, providing unprecedented competitive analysis on components, cost, and chip system functionality.

ON Semiconductor (Nasdaq: ON) has introduced the industry’s first 1/1.7-inch 2.1 megapixel CMOS image sensor featuring ON Semiconductor’s newly developed 4.2μm Back Side Illuminated (BSI) pixels – the AR0221 delivers class-leading low light sensitivity for industrial applications.

The AR0221 offers exceptional 3-exposure line-interleaved High Dynamic Range (HDR) with a sensor resolution of 1936H x 1096V, supporting frame rates of 1080p at 30 fps and an outstanding Signal-Noise Ratio (SNR) across visible and near-infrared wavelengths. Its 16:9 ratio with vivid colors and high contrast make it ideal for demanding industrial applications.

Gianluca Colli, Vice President and General Manager, Consumer Solution Division of Image Sensor Group at ON Semiconductor, said: “The AR0221 represents the industry’s best CMOS image sensor in this class, thanks to its outstanding low light sensitivity and SNR performance. By including features like windowing, auto black level correction and an onboard temperature sensor, ON Semiconductor has produced an image sensor that will enable a new generation of security and surveillance cameras.”

The sensor offers dual data interfaces in the form of 4-lane MIPI CSI-2 and HiSPi SLVS. Designed to meet industrial-grade specifications, the AR0221 can operate in harsh outdoor environments where operating temperatures can range between -30°C and +85°C. Packaged in a durable, reliable and robust iBGA package with anti-reflection coating on its cover glass, the AR0221 is programmable through a simple two-wire serial interface.

When power generators like windmills and solar panels transfer electricity to homes, businesses and the power grid, they lose almost 10 percent of the generated power. To address this problem, scientists are researching new diamond semiconductor circuits to make power conversion systems more efficient.

The view of the H-diamond MOSFET NOR logic circuit from above (left), and the operation of the NOR logic circuits, showing that the circuit only produces voltage when both inputs are at zero. Credit: Liu et al.

The view of the H-diamond MOSFET NOR logic circuit from above (left), and the operation of the NOR logic circuits, showing that the circuit only produces voltage when both inputs are at zero. Credit: Liu et al.

A team of researchers from Japan successfully fabricated a key circuit in power conversion systems using hydrogenated diamond (H-diamond.) Furthermore, they demonstrated that it functions at temperatures as high as 300 degrees Celsius. These circuits can be used in diamond-based electronic devices that are smaller, lighter and more efficient than silicon-based devices. The researchers report their findings this week in Applied Physics Letters, from AIP Publishing.

Silicon’s material properties make it a poor choice for circuits in high-power, high-temperature and high-frequency electronic devices. “For the high-power generators, diamond is more suitable for fabricating power conversion systems with a small size and low power loss,” said Jiangwei Liu, a researcher at Japan’s National Institute for Materials Science and a co-author on the paper.

In the current study, researchers tested an H-diamond NOR logic circuit’s stability at high temperatures. This type of circuit, used in computers, gives an output only when both inputs are zero. The circuit consisted of two metal-oxide-semiconductor field-effect transistors (MOSFETs), which are used in many electronic devices, and in digital integrated circuits, like microprocessors. In 2013, Liu and his colleagues were the first to report fabricating an E-mode H-diamond MOSFET.

When the researchers heated the circuit to 300 degrees Celsius, it functioned correctly, but failed at 400 degrees. They suspect that the higher temperature caused the MOSFETs to breakdown. Higher temperatures may be achievable however, as another group reported successful operation of a similar H-diamond MOSFET at 400 degrees Celsius. For comparison, the maximum operation temperature for silicon-based electronic devices is about 150 degrees.

In the future, the researchers plan to improve the circuit’s stability at high temperatures by altering the oxide insulators and modifying the fabrication process. They hope to construct H-diamond MOSFET logic circuits that can operate above 500 degrees Celsius and at 2.0 kilovolts.

“Diamond is one of the candidate semiconductor materials for next-generation electronics, specifically for improving energy savings,” said Yasuo Koide, a director at the National Institute for Materials Science and co-author on the paper. “Of course, in order to achieve industrialization, it is essential to develop inch-sized single-crystal diamond wafers and other diamond-based integrated circuits.”

The 2018 Symposia on VLSI Technology & Circuits will deliver a unique perspective into the technological ecosystem of converging industry trends – machine learning, IoT, artificial intelligence, wearable/implantable biomedical applications, big data, and cloud computing – the emerging technologies needed for ‘smart living.’ In a weeklong conference packed with technical presentations, a demonstration session, panel discussions, focus sessions, short courses, and a new “Friday Forum” on machine learning, the microelectronics industry’s premiere international conference covers technology, circuits, and systems with a range and scope unlike any other conference.

Built around the theme of “Technology, Circuits & Systems for Smart Living,” the Symposia programintegrates advanced technology developments, innovative circuit design, and the applications that they enable as part of our global society’s adoption of smart, connected devices and systems that change the way humans interact with each other.

Plenary Sessions (June 19):
The Symposia will open with two technology plenary sessions, including “Memory Technology: The Core to Enable Future Computing Systems” by Scott DeBoer, executive VP for technology development, Micron; and “Revolutionizing Cancer Genomic Medicine by Artificial Intelligence & Supercomputing with Big Data” by Satoru Miyano, director of the Human Genome Center, Institute of Medical Science at University of Tokyo.

The following Circuits plenary sessions include “Hardware-Enabled Artificial Intelligence” by Dr. Bill Dally, chief scientist & senior VP, Nvidia; and “Semiconductor Technologies Accelerate Our Future Vision: ‘ANSHIN Platform'” by Tsuneo Komatsuzaki, advisor, SECOM.

Focus Sessions (June 19, 20 & 21):
As part of the Symposia’s ongoing program integration, a series of joint focus sessions will be held to present contributed papers from the Technology and Circuits Symposia on June 20 and 21. Topics will include: “Heterogeneous System Integration,” “Power Devices & Circuits,” “New Devices & Systems for AI,” and “Design & Technology Co-Optimization (DTCO) in Advanced CMOS Technology.”

On June 19, the Technology focus sessions will include: “Back-End Compatible Devices & Advanced Thermal Management“ and “Sensors and Devices for IoT, Medicine, & Smart Living.” The Circuits focus sessions, held on June 21, include “Machine Learning Circuits & SoCs,” and “Advanced Wireline Techniques.”

Evening Panel Sessions (June 18 & 19):
A joint panel discussion, bringing together leading experts from Technology & Circuits programs will be held June 18 to answer the question, “Is the CPU Dying or Dead? Are Accelerators the Future of Computation?”

As Moore’s Law slows down and processor architecture innovations move away from single thread performance, the future of computing seems to be moving away from the general purpose CPU. Is the era of the CPU over? Will future CPUs simply coordinate activity among accelerators and other specialized processing units? The panel will examine future computing workloads as well as the innovative technology and circuit solutions that enable them, from moving computation closer to memory, and developing bio-inspired systems.

The Technology evening panel session panel discussion, held on June 19 will examine “Storage Class Memories: Who Cares? DRAM is Scaling Fine, NAND Stacking is Great.” Memory – DRAM and NAND scaling – though difficult, has persisted due to rapid innovations and continued engineering. Although there are new economic and fundamental challenges posed to continued memory scaling, a new class of memories – Storage Class memories, appears to bridge the latency gap that exists in the memory hierarchy and promises to improve system performance. Now the real question becomes – who really cares now? System architects, DRAM/NAND manufacturers? End users? The panel will discuss the challenges and opportunities of storage class memories in the environment where DRAM and NAND scaling continue.

The question to be addressed by the Circuits evening panel session, also held on June 19, is “What’s The Next Big Thing After Smartphones?” Although smartphones have driven the industry for more than a decade, the pace of innovation is slowing, and market saturation is occurring. What will be the next big thing? The Internet of Things? Automotive electronics? Virtual reality? Something else? A set of panelists with diverse expertise will discuss the possibilities.

Thursday Luncheon (June 21):
Continuing the Symposia’s tradition of thought-provoking presentations centered around the conference theme is the Thursday luncheon talk, entitled “The Hardware of The Mind, from Turing to Today,” by Grady Booch, chief scientist for software engineering at IBM Research. As scientists continue to the computing power of the human mind, they strive to bridge the gap between the physicality of silicon and the exquisite wonder of the brain. This presentation examines the journey of the hardware of the mind – from the Iliad, to da Vinci, to Edison, to Turing, to today – including an examination of how the growing understanding of the brain transforms the engineering of silicon, and how the laws of physics as well as the laws of humanity constrain that journey.

Full Day Short Courses (June 18):
The Technology Short Course – “Device & Integration Technologies for Sub-5nm CMOS & the Next Wave of Computing” will cover a range of topics, including CMOS technology beyond the 5nm node, MOL/BEOL interconnects, atomic-level analysis for FinFET & Nanowire design, 3D integration for image sensors, neuromorphic AI hardware, memory technologies for AI/machine learning, and sensors & analog devices for next generation computing.

The first Circuits Short Course – “Designing for the Next Wave of Cloud Computing” will address advanced computer architectures, GPU applications and FPGA acceleration, the evolution of memory and in-memory computation, and advanced packaging, power delivery and cooling for cloud computing, as well as the impact of quantum computing.

The second Circuits Short Course – “Bio-Sensors, Circuits & Systems for Wearable & Implantable Medical Devices” will cover circuits and systems for mobile healthcare, analog front-ends for bio-sensors, digital phenotyping using wearable sensors, bi-directional neural interfacing, body-area networking and body-coupled communications, ultrasound-on-a-chip, as well as a CMOS-based implantable retinal prosthesis.

Demonstration Session (June 18):
Following a successful launch last year in Kyoto, the popular demonstration session will again be part of the Symposia program, providing participants an opportunity for in-depth interaction with authors of selected papers from both Technology and Circuits sessions. These demonstrations will illustrate technological concepts and analyses through table-top presentations that show device characterization, chip operational results, and potential applications for circuit-level innovations.

Friday Forum (June 22):
New to the Symposia program this year will be the Friday Forum – a full-day series of presentations focusing on how technology and circuit designers engage in and drive the future of AI/machine learning systems, a subject area that continues to evolve as an impactful driver of the integrated systems that are part of the Symposia’s “Smart Living” theme. “Machine Learning Today & Tomorrow: A Technology, Circuits & Systems View” will provide the foundations and performance metrics for machine learning systems, an examination of advanced and emerging circuit architectures for next-generation systems, as well as highlighting tools and datasets for benchmarking and evaluating service-oriented architecture (SoA) machine learning systems.

The annual Symposium on VLSI Technology & Circuits will be held at the Hilton Hawaiian Village in Honolulu, Hawaii from June 18-22, 2018, with Short Courses held on June 18 and a special Friday Forum dedicated to machine learning/AI topics on June 22. The two conferences have been held together since 1987, providing an opportunity for the world’s top device technologists, circuit and system designers to exchange leading edge research on microelectronics technology, with alternating venues between Hawaii and Japan. A single registration enables participants to attend both Symposia.

Today, research and innovation hub in nanoelectronics and digital technologies imec, and fabless technology innovator Qromis, have announced the development of high performance enhancement mode p-GaN power devices on 200mm engineered Coefficient of Thermal Expansion (CTE)-matched substrates, processed in imec’s silicon pilot line. The substrates are offered by Qromis as commercial 200mm QST® substrates as part of their patented product portfolio. The results will be presented at next week’s CS international Conference (April 10-11, Brussels, Belgium).

Today, GaN-on-Si technology is the industry standard platform for commercial GaN power switching devices for wafer diameters up to 150mm/6 inch.  Imec has pioneered the development of GaN-on-Si power technology for 200mm/8 inch wafers and qualified enhancement mode HEMT and Schottky diode power devices for 100V, 200V and 650V operating voltage ranges, paving the way to high volume manufacturing applications. However, for applications beyond 650V such as electric cars and renewable energy, it has become difficult to further increase the buffer thickness on 200mm wafers to the levels required for higher breakdown and low leakage levels, because of the mismatch in coefficient of thermal expansion (CTE) between the GaN/AlGaN epitaxial layers and the silicon substrate.  One can envisage to use thicker Si substrates to keep wafer warp and bow under control for 900V and 1200V applications, but practice has learned that for these higher voltage ranges, the mechanical strength is a concern in high volume manufacturing, and the ever thicker wafers can cause compatibility issues in wafer handling in some processing tools.

Carefully engineered and CMOS fab-friendly QST® substrates with a CTE-matched core having a thermal expansion that very closely matches the thermal expansion of the GaN/AlGaN epitaxial layers, are paving the way to 900V-1200V buffers and beyond, on a standard semi-spec thickness 200mm substrate. Moreover, QST® substrates open perspectives for very thick GaN buffers, including realization of free-standing and very low dislocation density GaN substrates by >100 micron thick fast-growth epitaxial layers. These unique features will enable long awaited commercial vertical GaN power switches and rectifiers suitable for high voltage and high current applications presently dominated by Si IGBTs and SiC power FETs and diodes.

“QST® is revolutionizing GaN technologies and businesses for 200mm and 300mm platforms”, stated Cem Basceri, President and CEO of Qromis.  “I am very pleased to see the successful demonstration of high performance GaN power devices by stacking leading edge technologies from Qromis, imec and AIXTRON,” Basceri said.

In this specific collaboration, imec and Qromis developed enhancement mode p-GaN power device specific GaN epitaxial layers on 200mm QST®substrates, with buffers grown in AIXTRON’s G5+ C 200mm high volume manufacturing MOCVD system.

Imec then ported its p-GaN enhancement mode power device technology to the 200mm GaN-on- QST® substrates in their silicon pilotline and demonstrated high performance power devices with threshold voltage of 2.8 Volt.  “The engineered QST® substrates from Qromis facilitated a seamless porting of our process of reference from thick GaN-on-Si substrates to standard thickness GaN-on- QST® substrates using the AIX G5+ C system, in a joint effort of imec, Qromis and AIXTRON,” stated Stefaan Decoutere, program director for GaN power technology at imec. The careful selection of the material for the core of the substrates, and the development of the light-blocking wrapping layers resulted in fab-compatible standard thickness substrates and first-time-right processing of the power devices.

quormis

A further step has been taken along the road to manufacturing solar cells from lead-free perovskites. High quality films based on double perovskites, which show promising photovoltaic properties, have been developed in collaboration between Linköping University, Sweden, and Nanyang Technological University in Singapore.

The lead-free double perovskite solar cells (yellow, in the front) compared with the lead-based device (dark, in the background). The next step is tune the color of the double perovskites into dark, so that they can absorb more light for efficient solar cells. Credit: Thor Balkhed

The lead-free double perovskite solar cells (yellow, in the front) compared with the lead-based device (dark, in the background). The next step is tune the color of the double perovskites into dark, so that they can absorb more light for efficient solar cells. Credit: Thor Balkhed

Research groups around the world have recognised the potential of perovskites as one of the most promising materials for the development of cheap, environmentally friendly and efficient solar cells. In just a few years, the power conversion efficiency has increased from a few percent to over 22%. The perovskites currently available for use in solar cells, however, contain lead, and Feng Gao, senior lecturer at LiU, was appointed in the autumn of 2017 as Wallenberg Academy Fellow to develop lead-free double perovskites, in which a monovalent metal and a trivalent metal replace the divalent lead.

In the laboratory at the Division of Biomolecular and Organic Electronics, LiU, postdoc researchers Weihua Ning and Feng Wang have successfully manufactured single-layer thin films of densely packed crystals of double perovskites. The films are of extremely high quality and can be used as the active layer in solar cells, in which sunlight is absorbed and charge carriers created.

“Our colleagues at Nanyang Technological University in Singapore have shown that the charge carriers demonstrate long diffusion lengths in the material, which is necessary if the material is to be appropriate for application in solar cells,” says Feng Gao.

The power conversion efficiency of the solar cells is still low – only around 1% of the energy in sunlight is converted to electricity – but neither Feng Gao or Weihua Ning are worried.

“No, we have taken the first major step and developed a method to manufacture the active layer. We have several good ideas of how to proceed to increase the efficiency in the near future,” says Feng Gao.

Weihua Ning nods in agreement.

Researchers have calculated that over 4,000 different combinations of materials can form double perovskites. They will also use theoretical calculations to identify the combinations that are most suitable for use in solar cells.

This breakthrough for research in double perovskites is also a result of the joint PhD programme in Materials- and nanoscience/technology at Linköping University and Nanyang Technological University.

“This publication is a spin-off of the discussions in relation to the joint PhD programme between NTU-LiU. Two PhD students, one on each side, have been recruited to work on this project. This is an excellent start for the program.” says Professor Tze Chien Sum from NTU.

“We complement each other very well, the group led by Professor Sum in NTU are experts in photophysics and we are experts in materials science and device physics,” says Feng Gao.

Tre results is published in the prestigious scientific journal Advanced Materials.

Leti, a research institute of CEA Tech, today announced Leti’s silicon photonics process design kit (PDK) for photonic circuits is available in the Synopsys PhoeniX OptoDesigner suite.

Leti’s integrated silicon photonics platform has been developed for high-speed optical transceivers and highly-integrated optical interposer applications. The process design kit contains the design rules and building blocks for multi-project wafer and custom runs on Leti’s Si310 platform. It also includes a catalogue of components available at Leti, allowing Synopsys PhoeniX OptoDesigner customers to select the ones they need to build their circuits. Once the customers have a completed circuit design, Leti produces a proof of concept on a multi-project wafer run.

Used by more than 300 designers worldwide, OptoDesigner gives access to a complete set of passive components, such as grating couplers, silicon waveguides and transitions; and active components, such as high-speed Mach Zehnder modulators and high-speed germanium photodiodes based on Leti’s fab. It also includes physical verification tools checking whether the contributions meet the design rules defined by the fabrication constraints in Leti’s clean room.

“On the same mask, with this design kit, we are able to have photonic circuits performing various functions, according to the area of expertise of the different contributors,” said Andre Myko, responsible of MPW runs at Leti. “Fabless companies and academics therefore can realize substantial cost savings by ‘sharing’ production costs on multi-project wafer runs.”

Leti is a world leader in silicon photonics technology. Its photonic platform is France’s largest R&D center for the development, characterization and simulation of optoelectronic systems and components. Its activities range from component design through component fabrication, integration into systems and packaging.

“Leti’s process design kit available for Synopsys’ PhoeniX OptoDesigner is a licensed plug-in library of solutions that support multi-project wafers and custom runs provided by Leti,” said Niek Nijenhuis, global business development manager of Synopsys’ PhoeniX OptoDesigner products. “In addition to the photonic elements from the standard OptoDesigner library, Leti’s PDK contains technology-specific information like mask layer names, design rules, validated building blocks, die sizes and GDS file settings.”

Leti’s silicon photonics platform is also fully compatible with STMicroelectronics’ platform in Crolles, which enables fabless customers to take their new circuits to high-volume production.