Tag Archives: letter-pulse-tech

Organic semiconductors enable the fabrication of large-scale printed and mechanically flexible electronic applications, and have already successfully established themselves on the market for displays in the form of organic light-emitting diodes (OLEDs). In order to break into further market segments, however, improvements in performance are still needed. Doping is the answer. In semiconductor technology, doping refers to the targeted introduction of impurities (also called dopants) into the semiconductor material of an integrated circuit. These dopants function as intentional “disturbances” in the semiconductor that can be used to specifically control the behaviour of the charge carriers and thus the electrical conductivity of the original material. Even the smallest amounts of these can have a very strong influence on electrical conductivity. Molecular doping is an integral part of the majority of commercial organic electronics applications. Until now, however, an insufficient fundamental physical understanding of the transport mechanisms of charges in doped organic semiconductors has prevented a further increase in conductivity to match the best inorganic semiconductors such as silicon.

Researchers from the Dresden Integrated Center for Applied Physics and Photonic Materials (IAPP) and the Center for Advancing Electronics Dresden (cfaed) at TU Dresden, in cooperation with Stanford University and the Institute for Molecular Science in Okazaki, have now identified key parameters that influence electrical conductivity in doped organic conductors. The combination of experimental investigations and simulations has revealed that introducing dopant molecules into organic semiconductors creates complexes of two oppositely charged molecules. The properties of these complexes like the Coulomb attraction and the density of the complexes significantly determine the energy barriers for the transport of charge carriers and thus the level of electrical conductivity. The identification of important molecular parameters constitutes an important foundation for the development of new materials with even higher conductivity.

The results of this study have just been published in the renowned journal Nature Materials. While the experimental work and a part of the simulations were conducted at the IAPP, the Computational Nanoelectronics Group at the cfaed under the leadership of Dr. Frank Ortmann verified the theoretical explanations for the observations by means of simulations at the molecular level. In doing so, a comprehensive foundation for new applications for organic semiconductor technology has been created.

The inaugural SEMI 3D & Systems Summit opens today as the industry gathers for the latest insights and trends in 3D integration and systems for semiconductor manufacturing and applications. The 28-30 January summit in Dresden, Germany, highlights the future of intelligent systems powered by artificial intelligence (AI). To register, click here.

SEMI 3D & Systems Summit features a broad scope of topics aimed at driving business opportunities and innovation in areas including:

  • 3DIC Through-Silicon-Via (TSV) technology
  • 2.5D, 3D FO-WLP/e-WLB
  • Active and passive interposers
  • Stacked dies or stacked wafers
  • 3D alternative technologies
  • 5G Integration

Keynotes

Professor Hubert Lakner, director, Fraunhofer-Institute for Photonic Microsystems IPMS, will kick off the summit with his keynote Heterointegration – The Path to Future Complex Intelligent Systems. Lakner will explore connected intelligence opportunities arising from the transition to autonomous driving, the digitalization and electrification of cars, and the digitalization of industry and electrical power grids. These capabilities will be enabled by AI, improved cybersecurity, reinforced connectivity through 5G, edge computing, low-power components, sensors and power management.

Steffen Kroehnert, senior director, Technology Development, Amkor Technology Inc. will discuss advances in heterogeneous integration. The current wave of technology innovation in the semiconductor industry is largely driven by AI, deep learning, cloud computing and Internet of Things (IoT), with each of these leading-edge technologies sharing a common need: high-speed signaling with ultra-low latency/power and real time computational formulations. These capabilities require fully integrated functionality at the source, better known as the edge.

3D & System Summit Speakers

3D & Systems Summit speakers include experts from industry leaders such as Orbotech, GLOBALFOUNDRIES, Fraunhofer-Institute for Photonic Microsystems IPMS, EPIC – European Photonics Industry Consortium, McKinsey, System Plus Consulting, ASE Group, imec, DISCO HI-TEC EUROPE, STMicroelectronics, G-ray, Amkor, TU Dresden, Huawei, Fraunhofer IZM, AT&S AG, Deca Technologies and Miland.

Exhibitors Include Leaders in 3D Integration Microelectronics

The exhibition will showcase the most prominent names in 3D integration microelectronics manufacturing including ASE Group, Amkor Technology, Canon, Confovis, DISCO, FineTech, Fraunhofer IZM, FRT Metrology, Imec, LPKF, Optim Wafer Services, SPTS andXPERI. See the floorplan here.

3D & Systems Summit attendees are also invited to join the Symposium Panel Level Packaging 2019, organized by Fraunhofer IZM, 30 January, 14:00-18:00. Registration for the event is open. More details on the symposium are available here.

By Serena Brischetto

SEMI met with Martin Schrems, director of Strategy and Business Development at AT&S AG, to discuss Fan-Out technology trends ahead of SEMI 3D & Systems Summitin Dresden, Germany.

SEMI: What are the AT&S AG mission and vision and your role within the company?

Schrems: AT&S AG is evolving from a pure PCB manufacturer towards an interconnect solution provider. We can clearly see a continued trend towards miniaturization and modularization by (3D) integration of components such as integrated circuits and passives. Module sizes tend to increase by integrating more functions and system-level requirements. As a PCB maker, we have served such system-level requirements for a long time. Further integration offers opportunities to embed components in PCBs or substrates, offer layout and simulation services, as well as provide assembly and test services depending on specific customer requirements. As director of Strategy and Business Development, I work with my colleagues in AT&S, customers, and partners across the industry towards understanding and leveraging this major transformation in the electronics industry.

SEMI: What project are you currently working on that you think will make a difference in 2019?

Schrems: There are number of very exciting projects, many of them already involving AT&S contributions to module integration. Some of these projects involve key customers directly. We see exciting opportunities for integration of larger multi-function modules by combining PCB, substrate, and embedding core competences.

SEMI: The focus of your presentation at the 3D & Systems Summit will be on “Fan-Out System-in-Board technology enabling module and system-level integration.” What do you see as the key trend in this area?

Schrems: Fan-Out technologies are used to distribute I/O pad connections of nanoCMOS ICs over a larger area. This relaxes bump pitch and feature size requirements for subsequent system-level PCB interconnects. In some cases, Fan-Out layers already provide a substitute to currently used Flip-Chip substrates. Well-known examples are Fan-Out packages for application processors for smartphones. There is definitely a trend in the market towards Fan-Out for high-end processor applications. Advantages of such Fan-Out packages are shorter electrical connections and a reduced thickness.

However, one weakness of current Fan-Out packages is that only a limited number of components can be integrated due to mechanical stability challenges – a barrier to further component integration in larger modules. Currently, the only way to integrate more components is to use laminate-based PCBs and substrates with conventional Surface Mount Technology. Recent proposals like our “Fan-Out System-in-Board” (FO-SiBTM) technology are expected to provide an alternative Fan-Out packaging option at the board-level in the future.

SEMI: Please elaborate.

Schrems: Fan-Out capability and integration of more components – typically up to the 100 and more needed for electronics integration at system level – can be achieved simultaneously by combining technologies from the PCB and the packaging world. PCB laminates such as glass particles and organic materials provide mechanical stability for large boards. The recent introduction of substrate-like PCBs (mSAP) has already paved the way to cover applications that were reserved for substrates and classical packaging in the past.

With FO-SiBTM technology, we have taken it a step further and offer the option to integrate SAP substrate layers onto the PCB with lines/spaces below 10µm. FO-SiBTM makes it possible to directly contact nanoCMOS chips on PCBs without any intermediate substrates. Further adding Cu pillar technology at panel level will enable Fan-Out structures even for surface-mounted components, making recent R&D on panel-level Cu pillar technology very important. Through joint R&D, we can drive progress in the industry to further enable cost-effective heterogeneous 3D integration.

SEMI: What are your expectations for the 3D & Systems Summit in Dresden, and why do you recommend your members and other industry leaders to attend?

Schrems: The 3D summit is the high-level conference where key electronics industry players discuss major heterogeneous integration trends. Therefore, we very much appreciate the opportunities to exchange ideas across the supply chain including users, developers of integrated electronics hardware and tool manufacturers.

Serena Brischetto is a marketing and communications manager at SEMI Europe.

Laser systems specialist LPKF Laser & Electronics, based in Hannover, Germany has added a foundry service for thin glass substrates to its product portfolio. The company recently introduced the Laser-Induced Deep Etching technology, or LIDE for short, a process for the precise and highly efficient manufacturing of through-glass vias (TGV) and other deep micro features in thin glass substrates. The LIDE process is able to overcome past limitations in glass drilling and micro machining as it combines very high productivity and low manufacturing cost with the superior quality of a direct data process, forgoing masks or photo processing.

With the introduction of its new independent foundry service, LPKF is hoping to make the LIDE technology available on a much wider scale, covering both prototyping and experimental applications as well as scalable mass production capacity. The service is aimed at the manufacturing of glass substrates for advanced IC and MEMS packaging as well as micro-machining of spacer wafers,microfluidics and other specialty glass applications. LPKF’s new foundry service is located at its corporate headquarters and will operate under the company’s Vitrion brand name.

Established in 1976, LPKF Laser & Electronics manufactures laser systems used in circuit board prototyping, microelectronics fabrication, solar panel scribers, laser plastic welding systems and recently added a foundry service for thin glass substrates used in electronics packaging. LPKF’sworldwide headquarters is located in Hannover, Germany and its North American headquarters resides in Portland, OR.

ULVAC Technologies, Inc. (www.ulvac.com) has introduced the LS series of dry screw pumps as a high performance, more compact and lower cost replacement to multi-stage dry Roots pumps for a wide range of vacuum applications. With four pumping speeds from 120 to 1,000 m3/h, the LS series provides high pumping speed, compact size and low power consumption in a low cost package.

The ULVAC LS pump features a pair of conical shaped, variable pitch, deeply machined steel screws that allow the pump to be 1/3 shorter in length and 1/3 lighter in weight than other screw pumps in the same pumping speed class. This advanced screw design also increases the pumping speed near atmospheric pressure, allowing the LS pump to deliver a 20% faster pump down time while using less power. Power consumption is no more than 0.6 kW upon reaching ultimate pressure. A specialized built-in silencer reduces the noise level to not more than 61 dB(a). The lighter weight and smaller size of the LS series pumps compared to other dry pumps makes them excellent candidates for easy retrofits. When repairs are needed, cost and time is half that of a typical multi-stage Roots dry pump.

Researchers at the University of Exeter have developed an innovative technique that could help create the next generation of everyday flexible electronics.

A team of engineering experts have pioneered a new way to ease production of van der Waals heterostructures with high-K dielectrics- assemblies of atomically thin two-dimensional (2-D) crystalline materials.

One such 2-D material is graphene, which comprises of a honeycomb-shaped structure of carbon atoms just one atom thick.

While the advantages of van der Waals heterostructures is well documented, their development has been restricted by the complicated production methods.

Now, the research team has developed a new technique that allows these structures to achieve suitable voltage scaling, improved performance and the potential for new, added functionalities by embedding a high-K oxide dielectric.

The research could pave the way for a new generation of flexible fundamental electronic components.

The research is published in the journal Science Advances.

Dr Freddie Withers, co-author of the paper and from the University of Exeter said: “Our method to embed a laser writable high-K dielectric into various van der Waals heterostructure devices without damaging the neighbouring 2D monolayer materials opens doors for future practical flexible van der Waals devices such as, field effect transistors, memories, photodetectors and LED’s which operate in the 1-2 Volt range”

The quest to develop microelectronic devices to increasingly smaller size underpins the progress of the global semiconductor industry – a collection of companies that includes the tech and communication giants Samsung and Toshiba – has been stymied by quantum mechanical effects.

This means that as the thickness of conventional insulators is reduced, the ease at which electrons can escape through the films.

In order to continue scaling devices ever smaller, researchers are looking at replacing conventional insulators with high-dielectric-constant (high-k) oxides. However, commonly used high-k oxide deposition methods are not directly compatible with 2D materials.

The latest research outlines a new method to embed a multi-functional, nanoscaled high-K oxide, only a within van der Waals devices without degrading the properties of the neighbouring 2D materials.

This new technique allows for the creation of a host of fundamental nano-electronic and opto-electronic devices including dual gated graphene transistors, and vertical light emitting and detecting tunnelling transistors.

Dr Withers added: “The fact we start with a layered 2D semiconductor and convert it chemically to its oxide using laser irradiation allows for high quality interfaces which improve device performance.

“What’s especially interesting for me is we found this oxidation process of the parent HfS2 to take place under laser irradiation even when its sandwiched between 2 neighbouring 2D materials. This indicates that water needs to travel between the interfaces for the reaction to occur.”

An international team of researchers has reported a breakthrough in fabricating atom-thin processors – a discovery that could have far-reaching impacts on nanoscale chip production and in labs across the globe where scientists are exploring 2D materials for ever-smaller and -faster semiconductors.

The team, headed by New York University Tandon School of Engineering Professor of Chemical and Biomolecular Engineering Elisa Riedo, outlined the research results in the latest issue of Nature Electronics.

They demonstrated that lithography using a probe heated above 100 degrees Celsius outperformed standard methods for fabricating metal electrodes on 2D semiconductors such as molybdenum disulfide (MoS2). Such transitional metals are among the materials that scientists believe may supplant silicon for atomically small chips. The team’s new fabrication method – called thermal scanning probe lithography (t-SPL) – offers a number of advantages over today’s electron beam lithography (EBL).

First, thermal lithography significantly improves the quality of the 2D transistors, offsetting the Schottky barrier, which hampers the flow of electrons at the intersection of metal and the 2D substrate. Also, unlike EBL, the thermal lithography allows chip designers to easily image the 2D semiconductor and then pattern the electrodes where desired. Also, t-SPL fabrication systems promise significant initial savings as well as operational costs: They dramatically reduce power consumption by operating in ambient conditions, eliminating the need to produce high-energy electrons and to generate an ultra-high vacuum. Finally, this thermal fabrication method can be easily scaled up for industrial production by using parallel thermal probes.

Riedo expressed hope that t-SPL will take most fabrication out of scarce clean rooms – where researchers must compete for time with the expensive equipment – and into individual laboratories, where they might rapidly advance materials science and chip design. The precedent of 3D printers is an apt analogy: Someday these t-SPL tools with sub-10 nanometer resolution, running on standard 120-volt power in ambient conditions, could become similarly ubiquitous in research labs like hers.

“Patterning Metal Contacts on Monolayer MoS2 with Vanishing Schottky Barriers Using Thermal Nanolithography” appears in the January 2019 edition of Nature Electronics and can be accessed at http://dx.doi.org/10.1038/s41928-018-0191-0 with a “News & Views” analysis at https://www.nature.com/articles/s41928-018-0197-7.

Riedo’s work on thermal probes dates back more than a decade, first with IBM Research – Zurich and subsequently SwissLitho, founded by former IBM researchers. A process based on a SwissLitho system was developed and used for the current research. She began exploring thermal lithography for metal nanomanufacturing at the City University of New York (CUNY) Graduate Center Advanced Science Research Center (ASRC), working alongside co-first-authors of the paper, Xiaorui Zheng and Annalisa Calò, who are now post-doctoral researchers at NYU Tandon; and Edoardo Albisetti, who worked on the Riedo team with a Marie Curie Fellowship.

ZEISS today unveiled a new suite of high-resolution 3D X-ray imaging solutions for failure analysis (FA) of advanced semiconductor packages, including 2.5/3D and fan-out wafer-level packages. The new ZEISS systems include the Xradia 600-series Versa and Xradia 800 Ultra X-ray microscopes (XRM) for submicron and nanoscale package FA, respectively, as well as the new Xradia Context microCT. With the addition of these new systems to its existing family of products, ZEISS now provides the broadest portfolio of 3D X-ray imaging technologies serving the semiconductor industry.

“Throughout its 170-year history, ZEISS has pushed the frontiers of scientific research and advanced the start-of-the-art in imaging technologies to enable new industrial applications and technological innovations,” stated Dr. Raj Jammy, president, ZEISS Process Control Solutions (PCS) and Carl Zeiss SMT, Inc. “Now more than ever in the semiconductor industry, where package as well as device features are shrinking in all three dimensions, new imaging solutions are needed to quickly isolate failures in order to enable higher package yields. We are extremely pleased to announce this trio of new 3D X-ray imaging solutions for advanced semiconductor packaging, which provides our customers with a powerful high-resolution toolset to improve their failure analysis success rates.”

Advanced Packaging Requires New Defect Detection and Failure Analysis Methods
As the semiconductor industry approaches the limits of CMOS scaling, semiconductor packaging needs to help bridge the performance gap. To continue producing ever-smaller and faster devices with lower power requirements, the semiconductor industry is turning to package innovation through 3D stacking of chips and other novel packaging formats. This drives increasingly complex package architectures and new manufacturing challenges, along with increased risk of package failures. Furthermore, since the physical location of failures is often buried within these complex 3D structures, conventional methods for visualizing failure locations are becoming less effective. New techniques are required to efficiently isolate and determine the root cause of failures in these advanced packages.

To address these needs, ZEISS has developed a new suite of 3D X-ray imaging solutions that provides submicron and nanoscale 3D images of features and defects buried within intact structures in advanced package 3D architectures. This is enabled by rotating a sample and capturing a series of 2D X-ray images from different perspectives, followed by reconstruction of 3D volumes using sophisticated mathematical models and algorithms. An unlimited number of virtual cross-sections of the 3D volume may be viewed from any angle – providing valuable insight of failure locations prior to physical failure analysis (PFA). The combination of submicron and nanoscale XRM solutions from ZEISS provides a unique FA workflow that can significantly enhance FA success rates. ZEISS’s new Xradia Context microCT offers high contrast and resolution in a large field of view, using projection-based geometric magnification, and is fully upgradable to Xradia Versa.

New Imaging Solutions in Detail
Xradia 600-series Versa is the next generation of 3D XRM for non-destructive imaging of localized defects within intact advanced semiconductor packages. It excels in structural and FA applications for process development, yield improvement and construction analysis. Based on the award-winning Versa platform with Resolution at a Distance (RaaD) capability, Xradia 600-series Versa offers unsurpassed performance for high-resolution imaging of larger samples at long working distances to determine root causes of defects and failures in packages, circuit boards and 300 mm wafers. It can easily visualize defects associated with package-level failures, such as cracks in bumps or microbumps, solder wetting problems or through silicon via (TSV) voids. The 3D visualization of defects prior to PFA reduces artifacts and guides cross-section orientations, leading to improved FA success rates. Features include:

  • 0.5 micron spatial resolution, 40 nm min voxel size
  • Up to 2x higher throughput than Xradia 500-series Versa, achieved while maintaining high resolution with excellent source spot-size stability and thermal management control across the full kV and power range
  • Improved ease of use, including fast-activation source control
  • Ability to observe submicron structural changes within a package successively imaged at multiple reliability test read points

Xradia 800 Ultra brings 3D XRM to the nanoscale realm, producing images of buried features with nanoscale spatial resolution while preserving the volume integrity of the region of interest. Applications include process analysis, construction analysis and defect analysis of ultra-fine-pitch flip chip and bump connections – enabling process improvement for ultra-fine-pitch package and back-end-of-line (BEOL) interconnects. Xradia 800 Ultra enables visualization of the texture and volume of solder consumed by intermetallic compounds in fine-pitch copper pillar microbumps. Defect sites are preserved during imaging, enabling targeted follow-up analysis by a variety of techniques. The construction quality of blind assemblies, such as wafer-to-wafer bonded interconnect and direct hybrid bonding, can be characterized in 3D. Features include:

  • 150 nm and 50 nm spatial resolution (sample preparation is required)
  • Optional pico-second laser sample prep tool, enabling extraction of an intact volume sample (typically 100 microns in diameter) in under one hour
  • Compatibility with a wide range of options for follow-on analysis, including transmission electronic microscopy (TEM), energy dispersive X-ray spectroscopy (EDS), atomic force microscopy (AFM), secondary ion mass spectroscopy (SIMS) and nanoprobing

The piezoelectric materials that inhabit everything from our cell phones to musical greeting cards may be getting an upgrade thanks to work discussed in the journal Nature Materials released online Jan 21.

Xiaoyu ‘Rayne’ Zheng, assistant professor of mechanical engineering in the College of Engineering, and a member of the Macromolecules Innovation Institute, and his team have developed methods to 3D print piezoelectric materials that can be custom-designed to convert movement, impact and stress from any directions to electrical energy.

“Piezoelectric materials convert strain and stress into electric charges,” Zheng explained.

A printed flexible sheet of piezoelectric smart material. Credit: Photo by H. Cui of the Zheng Lab

The piezoelectric materials come in only a few defined shapes and are made of brittle crystal and ceramic – the kind that require a clean room to manufacture. Zheng’s team has developed a technique to 3D print these materials so they are not restricted by shape or size. The material can also be activated – providing the next generation of intelligent infrastructures and smart materials for tactile sensing, impact and vibration monitoring, energy harvesting, and other applications.

Unleash the freedom to design piezoelectrics

Piezoelectric materials were originally discovered in the 19th century. Since then the advances in manufacturing technology has led to the requirement of clean-rooms and a complex procedure that produces films and blocks which are connected to electronics after machining. The expensive process and the inherent brittleness of the material, has limited the ability to maximize the material’s potential.

Zheng’s team developed a model that allows them to manipulate and design arbitrary piezoelectric constants, resulting in the material generating electric charge movement in response to incoming forces and vibrations from any direction, via a set of 3D printable topologies. Unlike conventional piezoelectrics where electric charge movements are prescribed by the intrinsic crystals, the new method allows users to prescribe and program voltage responses to be magnified, reversed or suppressed in any direction.

“We have developed a design method and printing platform to freely design the sensitivity and operational modes of piezoelectric materials,” Zheng said. “By programming the 3D active topology, you can achieve pretty much any combination of piezoelectric coefficients within a material, and use them as transducers and sensors that are not only flexible and strong, but also respond to pressure, vibrations and impacts via electric signals that tell the location, magnitude and direction of the impacts within any location of these materials.”

3D printing of piezoelectrics, sensors and transducers

A factor in current piezoelectric fabrication is the natural crystal used. At the atomic level, the orientation of atoms are fixed. Zheng’s team has produced a substitute that mimics the crystal but allows for the lattice orientation to be altered by design.

“We have synthesized a class of highly sensitive piezoelectric inks that can be sculpted into complex three-dimensional features with ultraviolet light. The inks contain highly concentrated piezoelectric nanocrystals bonded with UV-sensitive gels, which form a solution – a milky mixture like melted crystal – that we print with a high-resolution digital light 3D printer,” Zheng said.

The team demonstrated the 3D printed materials at a scale measuring fractions of the diameter of a human hair. “We can tailor the architecture to make them more flexible and use them, for instance, as energy harvesting devices, wrapping them around any arbitrary curvature,” Zheng said. “We can make them thick, and light, stiff or energy-absorbing.”

The material has sensitivities 5-fold higher than flexible piezoelectric polymers. The stiffness and shape of the material can be tuned and produced as a thin sheet resembling a strip of gauze, or as a stiff block. “We have a team making them into wearable devices, like rings, insoles, and fitting them into a boxing glove where we will be able to record impact forces and monitor the health of the user,” said Zheng.

“The ability to achieve the desired mechanical, electrical and thermal properties will significantly reduce the time and effort needed to develop practical materials,” said Shashank Priya, associate VP for research at Penn State and former professor of mechanical engineering at Virginia Tech.

New applications

The team has printed and demonstrated smart materials wrapped around curved surfaces, worn on hands and fingers to convert motion, and harvest the mechanical energy, but the applications go well beyond wearables and consumer electronics. Zheng sees the technology as a leap into robotics, energy harvesting, tactile sensing and intelligent infrastructure, where a structure is made entirely with piezoelectric material, sensing impacts, vibrations and motions, and allowing for those to be monitored and located. The team has printed a small smart bridge to demonstrate its applicability to sensing the locations of dropping impacts, as well as its magnitude, while robust enough to absorb the impact energy. The team also demonstrated their application of a smart transducer that converts underwater vibration signals to electric voltages.

“Traditionally, if you wanted to monitor the internal strength of a structure, you would need to have a lot of individual sensors placed all over the structure, each with a number of leads and connectors,” said Huachen Cui, a doctoral student with Zheng and first author of the Nature Materials paper. “Here, the structure itself is the sensor – it can monitor itself.”

By Serena Brischetto

SEMI met with Jay Zhang, business development director at Corning Incorporated, to discuss recent innovations at Corning that allow fine granularity CTE engineering as well as high Young’s modulus. We also talked about the impact of this work on in-process warp control, as well as the associated production methodology that provides rapid prototyping and high-volume manufacturing. We spoke ahead of his presentation at the 3D & Systems Summit, 28-30 January, 2019, in Dresden, Germany. To register for the event, please click here.

SEMI: What is Corning’s mission and vision and your role within the company?

Zhang: Corning is one of the world’s leading innovators in materials science with a track record of 165+ years of life-changing innovations. We excel in glass science, ceramics science, and optical physics and succeed through sustained investment in RD&E. Our products include Corning® Gorilla® glass, a durable material used on more than six billion mobile devices worldwide, and industry-leading LCD glass for display applications.

We have recently dedicated a unit of the company called Precision Glass Solutions to address the emerging need for glass in the semiconductor industry. Here we apply Corning’s long history of glass science expertise and deep customer relationships in consumer electronics to support cutting-edge applications like wafer-level optics for precise 3D sensing and carrier solutions for temporary bonding applications in semiconductor manufacturing. It’s our most recent work in the Carrier Solutions product line that I’m excited to present: a new carrier glass product optimized for fan-out, called Corning Advanced Packaging Carriers.

SEMI: What projects are you currently working on that you think will make a difference in 2019?

Zhang: My team is excited to introduce Corning Advanced Packaging Carriers this year. This is a new line of product within our portfolio of Carrier Solutions. These ultra-flat glass carriers are specially developed to reduce customers’ challenge of in-process warp by up to 40 percent, which in turn helps advanced packaging customers achieve better yield.

Corning Advanced Packaging Carriers feature high-stiffness properties and are available in a wide range of coefficients of thermal expansion (CTE) in fine granularity. These attributes help customers select an ideal glass carrier that will minimize in-process warp for their package. Furthermore, we make sample quantities of these carriers available in just four to six weeks to help maximize efficiency during customers’ R&D process.

My team is excited about the potential of this new product, but also encouraged by our results. We have already supplied this product and have heard from one of the largest semiconductor companies in Taiwan that it has reduced in-process warp by as much as 150μm.

SEMI: Your presentation at the 3D & Systems Summit will focus on Agile Manufacturing of Glass Carriers for Advanced Packaging. What exactly will you be sharing?

Zhang: There is a lot of interest right now in using glass as a carrier substrate in temporary bonding applications in advanced semiconductor packaging – especially in fan-out processes. We also know that in-process warp is a significant challenge to companies pursuing advanced packaging because different CTE materials are added during the process.

My team has done a lot of work to understand the impact that an ideal CTE glass carrier substrate can have on minimizing in-process warp. We have studied the available levers – both theoretical and in real-life fab environments – that can help address this challenge. I will present our findings on how it is possible to select a glass carrier with the ideal CTE and Young’s modulus to reduce in-process warp by up to 40 percent, and how Corning has developed an agile manufacturing platform to support customers with these ideal carriers from their R&D stage through mass production.

SEMI: What do you think will be a hot topic in the next few years?

Zhang: We expect high-end fanout technology to address more applications beyond just mobile APs. There is also an interesting dynamic playing out between wafer-level and panel-level fan-out technologies. Corning is active in both areas. In developing and offering high performance glass carriers, we hope to help enable our customers to expand the fan-out applications space.

SEMI: What are your expectations regarding the summit in Dresden, and why do you recommend your members and other industry leaders to attend the 2019 3D & Systems Summit?

Zhang: Europe is where some of the most advanced packaging technologies are born. Fan-out also saw early commercialization there. I hope to meet many scientists and technologists at 3D & Systems Summit and exchange technical and business ideas. We also hope to get early feedback from other attendees about the value of our new product offering.

Serena Brischetto is a marketing and communications manager at SEMI Europe.

This originally appeared on the SEMI blog.