Tag Archives: letter-pulse-tech

Leti, a research institute of CEA Tech, today announced it has created the world’s first microfluidic circuit for cooling a particle detector, perhaps paving the way to a revolutionary, new detector technique at the Large Hadron Collider. This world-first event has been developed for CERN, the European nuclear research organization.

This breakthrough cooling system is part of CERN’s NA62 Gigatracker (GTK), a silicon pixel detector used to measure the arrival time and the position of incoming beam particles in the world’s largest particle accelerator. The NA62 detector is designed to study the “very rare” decay of kaons, subatomic particles made of quarks. Understanding these decays will help physicists check some of the predictions that the Standard Model of particle physics makes about short-distance interactions. Specifically, NA62 will measure the rate at which the charged kaon decays into a charged pion and a neutrino-antineutrino pair.

The Standard Model of particle physics explains how the basic building blocks of matter interact, governed by four fundamental forces in nature: gravity, electromagnetism and the strong and weak nuclear forces.

“The very rare decay of Kaons is sensitive to contributions coming from new particles and therefore represents a powerful way of searching for new physics,” said Augusto Ceccucci, NA62 spokesperson. “This technique complements the direct approach of the LHC detectors, and is a key component in CERN’s programs to probe the ultimate constituents of matter and understand the laws of nature.”

The NA62 is comprised of a set of three innovative silicon pixel detectors, whose job is to measure the arrival time and the position of the incoming beam particles. Installed in the heart of the NA62 detector, the silicon sensors are cooled down to approximately minus-20 degrees Celsius by a microfluidic silicon device developed by Leti and CERN researchers. The cooling system is required to remove the heat produced by the readout chips the silicon sensor is bonded to. The NA62 Gigatracker has a cooling plate on top of which both the silicon sensor and the readout chip are bonded.

In 2012, after CERN chose Leti to supply the microfluidic devices, CERN provided an initial fabrication process-flow that Leti’s Silicon Specialty Solutions (Leti-3S) program implemented in its own flow with its expertise in silicon processing, strictly following CERN’s technical specifications.

Leti-3S scientists demonstrated for the first time in the field of high-energy physics (HEP) the possibility of using silicon microfluidic devices for thermal management of silicon pixel detectors and their read-out electronics in LHC experiments.

Leti’s work included using deep silicon plasma-etching processes for microchannel production, its expertise at bonding silicon wafers at microscopic levels, and further grinding and thinning. In addition, Leti built titanium-nickel-gold contacts to connect the coolers to the NA62 device.

“The challenge was above all that we had only two pieces per wafers because of their large dimensions, meaning that two defects could result in a zero-percent yield,” said Catherine Charrier, project leader at Leti. “Maintaining the quality of the coolers on the centimeter dimensions, while respecting micrometric specifications, was a real challenge that we were able to overcome.”

Since being selected by CERN to work on NA62, Leti has contributed to the development of several types of cooling devices.

“Producing these silicon coolers provides us the opportunity to contribute to the scientific communities that use large instruments, which will expand Leti’s scope of operation,” Charrier said.

Power electronics, which do things like modify voltages or convert between direct and alternating current, are everywhere. They’re in the power bricks we use to charge our portable devices; they’re in the battery packs of electric cars; and they’re in the power grid itself, where they mediate between high-voltage transmission lines and the lower voltages of household electrical sockets.

Power conversion is intrinsically inefficient: A power converter will never output quite as much power as it takes in. But recently, power converters made from gallium nitride have begun to reach the market, boasting higher efficiencies and smaller sizes than conventional, silicon-based power converters.

Commercial gallium nitride power devices can’t handle voltages above about 600 volts, however, which limits their use to household electronics.

At the Institute of Electrical and Electronics Engineers’ International Electron Devices Meeting this week, researchers from MIT, semiconductor company IQE, Columbia University, IBM, and the Singapore-MIT Alliance for Research and Technology, presented a new design that, in tests, enabled gallium nitride power devices to handle voltages of 1,200 volts.

That’s already enough capacity for use in electric vehicles, but the researchers emphasize that their device is a first prototype manufactured in an academic lab. They believe that further work can boost its capacity to the 3,300-to-5,000-volt range, to bring the efficiencies of gallium nitride to the power electronics in the electrical grid itself.

That’s because the new device uses a fundamentally different design from existing gallium nitride power electronics.

“All the devices that are commercially available are what are called lateral devices,” says Tomás Palacios, who is an MIT professor of electrical engineering and computer science, a member of the Microsystems Technology Laboratories, and senior author on the new paper. “So the entire device is fabricated on the top surface of the gallium nitride wafer, which is good for low-power applications like the laptop charger. But for medium- and high-power applications, vertical devices are much better. These are devices where the current, instead of flowing through the surface of the semiconductor, flows through the wafer, across the semiconductor. Vertical devices are much better in terms of how much voltage they can manage and how much current they control.”

For one thing, Palacios explains, current flows into one surface of a vertical device and out the other. That means that there’s simply more space in which to attach input and output wires, which enables higher current loads.

For another, Palacios says, “when you have lateral devices, all the current flows through a very narrow slab of material close to the surface. We are talking about a slab of material that could be just 50 nanometers in thickness. So all the current goes through there, and all the heat is being generated in that very narrow region, so it gets really, really, really hot. In a vertical device, the current flows through the entire wafer, so the heat dissipation is much more uniform.”

Narrowing the field

Although their advantages are well-known, vertical devices have been difficult to fabricate in gallium nitride. Power electronics depend on transistors, devices in which a charge applied to a “gate” switches a semiconductor material — such as silicon or gallium nitride — between a conductive and a nonconductive state.

For that switching to be efficient, the current flowing through the semiconductor needs to be confined to a relatively small area, where the gate’s electric field can exert an influence on it. In the past, researchers had attempted to build vertical transistors by embedding physical barriers in the gallium nitride to direct current into a channel beneath the gate.

But the barriers are built from a temperamental material that’s costly and difficult to produce, and integrating it with the surrounding gallium nitride in a way that doesn’t disrupt the transistor’s electronic properties has also proven challenging.

Palacios and his collaborators adopt a simple but effective alternative. The team includes first authors Yuhao Zhang, a postdoc in Palacios’s lab, and Min Sun, who received his MIT PhD in the Department of Electrical Engineering and Computer Science (EECS) last spring; Daniel Piedra and Yuxuan Lin, MIT graduate students in EECS; Jie Hu, a postdoc in Palacios’s group; Zhihong Liu of the Singapore-MIT Alliance for Research and Technology; Xiang Gao of IQE; and Columbia’s Ken Shepard.

Rather than using an internal barrier to route current into a narrow region of a larger device, they simply use a narrower device. Their vertical gallium nitride transistors have bladelike protrusions on top, known as “fins.” On both sides of each fin are electrical contacts that together act as a gate. Current enters the transistor through another contact, on top of the fin, and exits through the bottom of the device. The narrowness of the fin ensures that the gate electrode will be able to switch the transistor on and off.

“Yuhao and Min’s brilliant idea, I think, was to say, ‘Instead of confining the current by having multiple materials in the same wafer, let’s confine it geometrically by removing the material from those regions where we don’t want the current to flow,'” Palacios says. “Instead of doing the complicated zigzag path for the current in conventional vertical transistors, let’s change the geometry of the transistor completely.”

Leti, a research institute of CEA Tech, demonstrated significant improvements in the field of memory systems at IEDM 2017 this week.

These include reconfiguring Static Random-Access Memory (SRAM) into Content-Addressable Memory (CAM), improving non-volatile crossbar memories and using advanced Tunnel Field-Effect Transistors (TFET). Another breakthrough presents a high-density SRAM bitcell on Leti’s CoolCubeTM 3D platform, which reduces the area required for memory by 30 percent, while maintaining full device functionality. This breakthrough points the way to easing the major memory bottleneck in more complex systems on chip (SoC), where up to 90 percent of the SoC area might be taken by SRAM.

The breakthroughs were reported Dec. 5 at IEDM 2017 in a paper titled “Advanced Memory Solutions for Emerging Circuits and Systems.”

A key obstacle to shrinking SRAM on SoCs is bitcell-area limitations linked to required performance and yield, both of which become more challenging as technology scales. Lowering system power consumption is also limited by memory, as the SRAM performance and its stability scale less successfully than logic performance at lower voltages. Other memories like CAM might be affected even more by voltage scaling.

“All of these obstacles become particularly important for the Internet of Things, where ultralow-power consumption and the cost of individual nodes are crucial, and SRAM limitations have a big impact on both,” said Bastien Giraud, one of the paper authors.

Leti approached these challenges with a CoolCubeTM SRAM design focusing on the development of a compact and functional four-transistor bitcell, along with other innovations:

  • Reconfiguring memory between the CAM and SRAM, depending on the application
  • Optimizing memory using TFET, focusing on the exploitation of its negative differential-resistance effect to build ultralow-power SRAM, Flip Flops (FF) and refresh-free Dynamic Random Access Memory (DRAM)
  • A new compensation technique for crosspoint memory that reduces the voltage drop and leads to larger memory arrays.

Leti said its proposed CAM/SRAM outperforms memories, with operations at 1.56GHz and 0.13fJ/bit energy per search. In addition, the proposed TFET designs are competitive in terms of area, performance and static power consumption. Leti’s proposed compensation technique in crosspoint memory also enables the design of cost-efficient large memory arrays, while reducing the impact of temporal and spatial variations.

Short-term applications include crossbar circuits for storage-class memory and flexible SOCs with SRAM/CAM re-configurability.

“In the longer term, Leti’s CoolCubeTM technology will be able to deliver very high-density SRAM,” Giraud said. “Enabling TFET-based DRAM and integrating TFET standard cells into CMOS designs will allow circuit designers to take advantage of the best features of both technologies.”

Cree, Inc. (Nasdaq: CREE) announces the commercial availability of the XLamp®XD16 LED, the industry’s first Extreme Density LED, which delivers up to 5 ½ times higher lumen density than Cree’s previous generation of high power LEDs. Built on Cree’s groundbreaking NX Technology Platform, the XD16 LED combines breakthrough lumen density, low optical cross-talk, unsurpassed thermal contact and ease of system manufacturing to enable innovative new designs for a broad spectrum of lighting applications, such as color-tuning, street, portable and industrial.

“Cree’s new XD16 LED delivers an incredible amount of light output for such a tiny package,” said Joe Skrivan, senior technical director at Black Diamond Equipment. “The XD16 LED’s breakthrough lumen output and peak intensity is a game-changer for our climbing headlamp products because we can design better beam control and decrease the overall size and weight compared to existing designs.”

The XLamp XD16 LED delivers a lumen density of more than 284 lumens per square-millimeter, which is the highest level achieved by a commercially available lighting-class LED. The ceramic-based XD16 LED utilizes the proven XQ footprint and successfully addresses challenges with luminaire manufacturing, thermal design, optical design and reliability faced by competing LEDs. For example, the XD16 LED reduces system-level optical loss by up to three times versus competing technologies when LEDs are placed close together on a board. This improvement translates into fewer wasted lumens and higher efficacy for lighting products.

“Cree’s new Extreme Density LED demonstrates that true LED innovation improves our customers’ system performance without forcing compromise,” said Dave Emerson, Cree LEDs executive vice president and general manager. “The XD16 LED delivers unmatched lumen density without the design and manufacturing challenges associated with inferior LED technology approaches. Now, lighting manufacturers can easily achieve previously unattainable levels of light output and efficacy in their existing form factors.”

The new LEDs are characterized and binned at 85°C, available in ANSI White, EasyWhite® 3- and 5-step color temperatures (2700K – 6500K), and CRI options of 70, 80 and 90. Product samples are available now and production quantities are available with standard lead times.

3D acoustic imaging is useful for measuring the heights of bumps on BGAs, flip chips, and other devices. But it can also be used to image and quantify depth/height variation of features within a particular sample.

BY TOM ADAMS, Sonoscan, Inc., Elk Grove Village, IL

Three-dimensional acoustic images, like three-dimensional light images, differ from their two-dimensional counterparts by displaying the z dimension in addition to x and y dimensions. The first 3D acoustic images were made around by 20 years ago at Sonoscan, who invented the technique. The technology can display the surface topography of a sample, or its internal profile at a desired depth.

The C-SAM® acoustic micro imaging tools that make the 3D images have a transducer that pulses ultrasound at a given frequency at or into the sample thousands of times a second as the transducer scans back and forth above the surface of the sample. A pulse of ultrasound leaving the transducer travels first through a water couplant, supplied constantly by a water jet attached to the transducer. Every time ultrasound exits one material/fluid and enters another, some of the ultra- sound is reflected to the transducer; as a result, a portion of the pulse is reflected by the water-to-sample surface interface. The rest of the pulse crosses the surface interface and travels deeper into the sample.

In most acoustic imaging, the concern is with the amplitude of the returned echoes from the interior of the sample. A well bonded interface between silicon and epoxy will reflect a small amount of the pulse. The amount of ultrasound reflected causes a specific amplitude in the return echo. The echo amplitude is measured and then displayed in the acoustic image by an assigned color value for that amplitude. The highest amplitude echoes essentially indicate 100% reflection and are produced only by the interface between a solid and a gas. All gap-type defects meet this definition.

By measuring the amplitude of the reflected signal and identifying those having near-total reflection, an acoustic micro imaging (AMI) tool can detect voids, cracks, non-bonds and other gap-type anomalies that threaten the longevity of a part.

3D imaging, however, cares about the position in time of a reflection from a given plane such as the surface of the sample. By measuring the distance, in time, from the end of the transducer to the front surface, AMI can assign a color value to each location in time that the front surface occurs. In this way a color represen- tation of the topography is made. Plastic BGA packages, for example, are notorious for having internal defects that disturb the flatness of the package’s surface. By assigning a color to each height variation, the locations of surface disturbances are easily detected. The same method can be used to image unpopulated printed circuit boards to ensure that they are flat enough to avoid placing stress on connections. Samples imaged in 3D are viewed at an angle from the vertical perspective in order to make local height differences visible.

Recently the method has been used in a different role – measuring the height, before substrate attachment, of the solder bumps on BGAs. A precise vertical range is set – in acoustic terms, a gate. If the tops of all the solder bumps fall within the small vertical range defined by the gate, successful bonding of all bumps to the substrate is more likely.

The basics of imaging rounded bumps are essentially the same as for imaging flat surfaces. The sides of the bump may send back little or no signal, but in this investigation, they are not the area of interest. The color of the top of the bump is what matters, because it indicates whether the top lies within the narrow vertical range for successful bonding. Interpretation of the image is simplified by software that stretches the image of each solder bump vertically. If the solder bumps were imaged in their actual height, the gate in which the top should lie would be tiny and hard to see. Stretching each bump vertically does not change the measurement, it simply makes the results easier to interpret.

FIGURE 1 shows an acoustic side view image of a solder bump in its unstretched form, and the stretched form of its acoustic image. (Acoustic side views of internal features can be made by Sonoscan’s Q-BAMTM imaging mode, designed for non-destructive cross sectioning.) Even after the image is stretched, it may represent a vertical extent of only several microns. If bumps were imaged without vertical exaggeration, distinguishing accept from reject might be very difficult or even impossible. The amount of stretching needed for the bumps on a particular part type of BGAs, and the vertical extent of the gate that will yield the best results can typically be determined from previous experience with a BGA. Overall, what matters is not the precise configuration of the gate but ensuring that all bumps are very close to each other in height.

Screen Shot 2017-12-07 at 11.32.53 AM

FIGURE 2 is the stretched 3D image of the solder bumps on one BGA before placement onto a PCB. The desired condition is that the top surface of the bump lie within the thin horizontal slice colored green in the image. FIGURE 3 is a magnified view of a small section of Fig. 2.

Screen Shot 2017-12-07 at 11.33.02 AM Screen Shot 2017-12-07 at 11.33.08 AM

All the bumps in this BGA have tops that lie within the vertical “green” gate. There are no bumps toppled by other colors, a condition that would reveal that the bump might not bond to the substrate as well. The black areas in the figure are locations where no bump is present. BGAs like this are loaded into JEDEC-style trays and imaged in large quantities. Identification and removal of BGAs having one or more unsuitable bumps can be automated. The failure criteria are completely customizable depending on the level of tolerance a particular sample is held to.

FIGURE 4 is a small portion of the 3D image of a BGA where results were not quite so uniform. The desired color for the top of each bump here is red. As shown red is the top color on many of the bumps, especially in the left half of the image. But elsewhere there are bumps with pink, orange and other top colors. This is a BGA that may not make good contact with the PCB. Further down the assembly line this sample would likely experience immediate or early electrical failures due to attachment issues.

Screen Shot 2017-12-07 at 11.33.15 AM

Location information can become useful to large scale production companies that are trying to understand their process better. If there are trends that suggest a specific location on the BGA is having a bump height problem, then there maybe something related to the process, handling, or materials being used that could be causing the issue. The measurement can be taken simultaneously while scanning in standard reflection mode. There is no addition in scan time or reduction in UPH to make this measurement.

3D imaging can also be used to depict strictly internal features. The operator sets two vertical values – an internal gate – to define the top and bottom of the desired depth measurement. This mode is known as profile mode imaging. When imaging in profile mode, only the echoes that occur within the depth of the gate are used for imaging. Signals outside of the gate are ignored. Because this is 3D imaging inside the part, the variation is measured relative to the top surface of the part.

3D acoustic imaging is useful for measuring the heights of bumps on BGAs, flip chips, and other devices. But it can also be used to image and quantify depth/ height variation of features within a particular sample. Measuring the distance of each of the thousands of x-y locations across the entire top surface of a tilted die can reveal how much of a threat to longevity the tilt is. It may even be helpful to stretch the image vertically to make so that the tilt could be easily seen to the human eye. Depending on the gate and depth chosen for a given profile mode image, it is possible to discern defects that occur at different height locations. This can be useful by showing that two similar looking defects may not be occurring at the exact same depth within the part. For example, you may have a void within the molding compound just a few microns before the lead frame. In standard reflection mode imaging, it would be impossible to determine if the defect occurred just before the lead (inclusion within the mold compound) or if the defect was a result of poor bonding directly to the lead frame. The is because standard reflection mode imaging only measures the amplitude of a given echo and not its location in time. Using profile mode, the depth location information is displayed using a color bar to depict the height infor- mation. In this way, defects that occur at different heights will also be assigned a different color value. This is the value of 3D acoustic imaging: mapping Time-Distance relationships at the surface or inter- nally for a given sample in a manner that is useful and easy to interpret.

Leti, a research institute of CEA Tech, has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This breakthrough shows the way to transitioning away from 100mm wafers and a process based on bulk III-V technology that requires contacts with noble metals and lift-off based patterning.

The project, carried out in the framework of the IRT Nanoelec program, which is headed by Leti, demonstrated that the hybrid device’s performance is comparable to the reference device fabricated with the current process on 100mm wafers. The fabrication flow is fully planar and compatible with large-scale integration on silicon-photonic circuits.

The results were reported Dec. 5 at IEDM 2017 in a paper titled “Hybrid III-V/Si DFB Laser Integration on a 200mm Fully CMOS-compatible Silicon Photonics Platform”.

CMOS compatibility with silicon photonics lowers fabrication costs, and provides access to mature and large-scale facilities, which enables packaging compatibility with CMOS driving circuits.

“Silicon-photonic technologies are becoming more mature, but the main limitation of these platforms is the lack of an integrated light source,” said Bertrand Szelag, a co-author of the paper. “This project showed that a laser can be integrated on a mature silicon-photonic platform with a modular approach that does not compromise baseline process performances. We demonstrated that the entire process can be done in a standard CMOS fabrication line with conventional process and materials, and that it is possible to integrate all the photonic building blocks at large scale.”

The integration required managing a thick silicon film, typically 500nm thick, for the hybrid laser, and a thinner one, typically 300nm, for the baseline silicon-photonic platform. This required locally thickening the silicon by adding 200nm of amorphous silicon via a damascene process, which presents the advantage of leaving a flat surface favorable for bonding III-V silicon. The laser can be integrated on a mature silicon photonic platform with a modular approach that does not compromise the baseline process performance.

The novelty of the approach also included using innovative laser electrical contacts that do not contain any noble metals, such as gold. The contacts also prohibit integration lift-off-based processes. Nickel-based metallization was used with an integration technique similar to a CMOS transistor technique, in which tungsten plugs connect the device to the routing metal lines.

Next steps include integrating the laser with active silicon-photonic devices, e.g. a modulator and photodiode with several interconnect metal levels in a planarized backend. Finally, III-V die bonding will replace III-V wafer bonding in order to process lasers on the entire silicon wafer.

Tilted scanning electron microscopy view of the III-V/Si DFB laser after the IIIV patterning steps.

Tilted scanning electron microscopy view of the III-V/Si DFB laser after the IIIV patterning steps.

Laser spectrum at 160 mA injection currents

Laser spectrum at 160 mA injection currents

A group of spintronics researchers at EPFL is using new materials to reveal more of the many capabilities of electrons. The field of spintronics seeks to tap the quantum properties of “spin,” the term often used to describe one of the fundamental properties of elementary particles – in this case, electrons. This is among the most cutting-edge areas of research in electronics today.

Researchers working in the Laboratory of Nanoscale Electronics and Structures (LANES), which is run by Professor Andras Kis, were able to quantify these quantum properties for a category of two-dimensional semiconductors called transition metal dichalcogenides, or TMDCs. Their research projects, which were published recently in ACS Nano and today in Nature Communications, confirm that materials like graphene (C), molybdenite (MoS2) and tungsten diselenide (WSe2) offer, either alone or by combining some of their characteristics, new perspectives for the field of electronics – perspectives that could ultimately lead to smaller chips that generate less heat.

“With the methods we’ve recently developed, we’ve shown that it is possible to access the spin in these TMDC materials, quantify it and use it to introduce new functionalities,” says Kis.

This all takes place at an extremely small scale. In order to access these quantum properties, the researchers must work with high quality materials. “If we want to examine certain characteristics of electrons, including their energy, we need to be able to watch them move over relatively long distances without there being too much dispersion or disruption,” explains Kis.

In the form of waves

The researchers’ method allows them to obtain samples of sufficient quality both to observe how electrons move around in the form of waves and to quantify their energy.

But the LANES team was also able to access another quantum property. Spins of electrons and holes in this type of a 2D semiconductor can be in one of two states, which are conventionally described as being oriented upward – spin up – or downward – spin down. Their energy will be slightly different in each of these two states. That’s called spin splitting, and the EPFL researchers have measured it for the first time for electrons in TMDC materials. In the second publication, the researchers wrote about how they used the spin splitting in a TMDC in order to introduce polarized spin currents in graphene without using a magnetic field.

These discoveries are a step forward for the emerging field of spintronics and make it increasingly likely that a different property of charge carriers – i.e. spin, in addition to the electrical charge – will play a role in tomorrow’s electronic devices.

Quantenna Communications, Inc. (Nasdaq:QTNA), a developer of high performance Wi-Fi solutions, today announced that Dr. Nambi Seshadri, Quantenna’s chief technologist has been selected as the 2018 IEEE Alexander Graham Bell Medal recipient for exceptional contributions to wireless, networking and engineering. In addition to this highest honor, Seshadri’s prize consists of a gold medal, a bronze replica, a certificate, and an honorarium.

“The innovations by Nambi form the basis for some of today’s Wi-Fi and other wireless networking standards and systems, now in use by billions of Wi-Fi users,” said Dr. Sam Heidari, Chairman and Chief Executive Officer, Quantenna. “We are honored to have such a distinguished and accomplished chief technologist on our team. The process is extraordinarily competitive, this is a great lifetime accomplishment and one of the most prestigious honors that one may receive in our field.”

Every year, the IEEE board of directors selects a SINGLE individual to receive the IEEE Alexander Graham Bell Medal. The selection criteria used include weighing the value of the individual’s contribution to communication among people as well as to communication sciences and engineering, and an evaluation of the contributor, nominator and references. The timeliness of the recognition, and quality of the nomination also are considered.

The IEEE Alexander Graham Bell Medal was established in 1976 by the IEEE Board of Directors, in commemoration of the centennial of the telephone’s invention, to provide recognition for outstanding contributions to telecommunications. The invention of the telephone by Alexander Graham Bell in 1876 was a major event in electrotechnology. It was instrumental in stimulating the broad telecommunications industry that has dramatically improved life throughout the world. As an individual, Bell himself exemplified the contributions that scientists and engineers have made to the betterment of mankind.

In addition to serving as chief technologist to Quantenna, Seshadri is a Professor of Electrical and Computer Engineering (ECE) for the University of California, San Diego. Prior to Quantenna, Seshadri held multiple senior positions at Broadcom Corporation where he helped Broadcom’s wireless initiatives, including it’s foray into cellular, mobile multimedia, low power wireless connectivity, GPS and others. During 2011-2014, he also served as the General Manager of the Mobile Platforms Business Unit. Prior to joining Broadcom Corporation, he was a Member of Technical Staff at with AT&T Bell Lab Laboratories and Head of Communications Research at AT&T Shannon Labs where he contributed to fundamental advances in wireless communication theory and practice.

Seshadri was elected Fellow of the Institute of Electrical and Electronic Engineers (IEEE) in 2000 and was elected to the National Academy of Engineering (USA) in 2012 and as a Foreign Member of the Indian National Academy of Engineering in the year 2013. He holds approximately 200 patents. He was a co-recipient of the IEEE Information Theory Paper Award in 1999 for his paper with Tarokh and Calderbank on space-time codes, and his IEEE Journal on Selected Areas In Communications (JSAC) paper on space-time coding modems with Naguib, Tarokh, and Calderbank was selected by IEEE Communication Society for publication in, “The Best of the Best: Fifty Years of Communications and Networking Research,” for 2003.

A research group in Japan announced that it has quantified for the first time the impacts of three electron-scattering mechanisms for determining the resistance of silicon carbide (SiC) power semiconductor devices in power semiconductor modules. The university-industry team consisting of researchers from the University of Tokyo and Mitsubishi Electric Corporation has found that resistance under the SiC interface can be reduced by two-thirds by suppressing electron scattering by the charges, a discovery that is expected to help reduce energy consumption in electric power equipment by lowering the resistance of SiC power semiconductors.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electron scattering under the silicon carbide (SiC) interface is limited by three factors: roughness of the SiC interface, charges under the SiC interface and atomic vibration. Credit: 2017 Mitsubishi Electric Corporation.

Electric power equipment used in home electronics, industrial machinery, trains and other apparatuses requires a combination of maximized efficiency and minimized size. Mitsubishi Electric, a leading Japanese electronics and electrical equipment manufacturer, is accelerating use of SiC devices for power semiconductor modules, which are key components in electric power equipment. SiC power devices offer lower resistance than conventional silicon power devices, so to further lower their resistance it is important to understand correctly the characteristics of the resistance under the SiC interface.

“Until now, however, it had been difficult to measure separately resistance-limiting factors that determine electron scattering,” says Satoshi Yamakawa, senior manager of the SiC Device Development Center at Mitsubishi Electric’s Advanced Technology R&D Center.

Electron scattering focusing on atomic vibration was measured using technology from the University of Tokyo. The impact that charges and atomic vibration have on electron scattering under the SiC interface was revealed to be dominant in Mitsubishi Electric’s analyses of fabricated devices. Although it has been recognized that electron scattering under the SiC interface is limited by three factors, namely, the roughness of the SiC interface, the charges under the SiC interface and the atomic vibration, the contribution of each factor had been unclear. A planar-type SiC metal-oxide-semiconductor field-effect transistor (SiC-MOSFET), in which electrons conduct away from the SiC interface to around several nanometers, was fabricated to confirm the impact of the charges.

“We were able to confirm at an unprecedented level that the roughness of the SiC interface has little effect while charges under the SiC interface and atomic vibration are dominant factors,” says Koji Kita, an associate professor at the University of Tokyo’s Graduate School of Engineering and one of scientists leading the research.

Using an earlier planar-type SiC-MOSFET device for comparison, resistance was reduced by two-thirds owing to suppression of electron scattering, which was achieved by making the electrons conduct away from the charges under the SiC interface. The previous planar-type device has the same interface structure as that of the SiC-MOSFET fabricated by the electronics maker.

For the test, Mitsubishi Electric handled the design, fabrication and analysis of the resistance-limiting factors and the University of Tokyo handled the measurement of electron-scattering factors.

“Going forward, we will continue refining the design and specifications of our SiC MOSFET to further lower the resistance of SiC power devices,” says Mitsubishi Electric’s Yamakawa.

This research achievement was announced at the 63rd International Electron Devices Meeting (IEDM) in San Francisco, California, on December 4, 2017.

See-through electronic devices, such as transparent displays, smart windows and concealed circuits require completely translucent components if users are to digitally interact with their perceived surroundings and manipulate this information in real time. Now, KAUST researchers have devised a strategy that helps to integrate transparent conducting metal-oxide contacts with two-dimensional (2D) semiconductors into these devices.

Ultrathin semiconductor sheets that are composed of transition metals associated with chalcogen atoms, such as sulfur, selenium and tellurium, present exceptional electronic properties and optical transparency. However, to date, incorporating molybdenum sulphide (MoS2) monolayers into circuits has relied on silicon substrates and metal electrodes, such as gold and aluminum. The opacity of these materials has stalled attempts to develop fully transparent 2D electronic devices.

The KAUST team led by material scientists Xi-Xiang Zhang and Husam Alshareef has combined MoS2 monolayers with transparent contacts to generate a series of devices and circuits, such as transistors, inverters, rectifiers and sensors. The contacts consisted of aluminum-doped zinc oxide (AZO), a low-cost transparent and electrically conductive material that may soon replace the widely used indium-tin oxide. “We wanted to capitalize on the excellent electronic properties of 2D materials, while retaining full transparency in the circuits,” explains Alshareef.

According to Alshareef, the researchers grew the contacts over a large area by atomic-layer deposition, during which individual atom layers precisely accumulate on a substrate. Their main difficulty was to also form high-quality MoS2 monolayers on silicon-based substrates over a large area. “We overcame this by using an interfacial layer that promotes MoS2 growth,” says Alshareef.

The team also developed a water-based transfer process that moves the as-deposited large-area monolayers onto a different substrate, such as glass or plastic. The researchers then deposited the AZO contacts on the transferred 2D sheets before manufacturing the devices and circuits.

The resulting devices outperformed their equivalents equipped with opaque metal contacts, such as gate, source and drain electrodes, which demonstrates the high compatibility between transparent conducting metal-oxide contacts and MoS2 monolayers. “The transistors fabricated by the large-area process showed the lowest turn-on voltage of any reported MoS2 monolayer-based thin-film transistor grown by chemical vapor deposition,” says PhD student Zhenwei Wang, first author of the study.

“Additional circuits are planned that will help demonstrate that our approach is robust and scalable” says Alshareef.