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Alpha and Omega Semiconductor Limited (AOS) (Nasdaq:AOSL) a designer, developer and global supplier of a broad range of power semiconductors and power ICs, today announced the release of AONS66916 production utilizing the latest Alpha Shield Gate Technology Generation 2 (AlphaSGT2). The AONS66916 has RDS(ON) * Qg  (FOM) and more robust capability for a greater safety margin. In synchronous rectification, it is essential to optimize the reverse recovery charge and reduce the voltage overshoot. These attributes enable higher efficiency and robustness to critical high density telecom and server applications.

The AlphaSGT2 provides ~30% lower RDS(ON) compared to AlphaSGT1 and is designed to be more robust with significant avalanche energy improvement. AlphaSGT2 technology reduces both conduction and switching losses. Thus, with AlphaSGT2 technology, circuit designers can prevent paralleling devices for lower turn-on resistance, enabling higher power density in power supply applications.

“The new AlphaSGT2 100V technology is designed for critical applications such as Telecom and Datacom power supplies where power density, high efficiency, and robustness is essential,” said Peter H. Wilson, Director of Product Marketing at AOS.

Technical Highlights

Part Number VDS (V) VGS (V) RDS(ON)MAX (mOhms) Qg (typ) (nC) ID @ TA = 25°C (A)
@ 10V
AONS66916 100 ±20 3.6 67 100

The AONS66916 is immediately available in production quantities with a lead-time of 15 weeks. The unit price of 1,000 pieces is $ 1.2.

Alpha and Omega Semiconductor Limited, or AOS, is a designer, developer and global supplier of a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM and Power IC products.

STMicroelectronics (NYSE: STM) is powering up wireless charging for mobile devices by introducing one of the world’s first chips to support the latest industry standard for faster charging.

Nowadays, people are using their smartphones and tablets so intensively that many need to top up battery power several times a day. With wireless charging, users don’t need to carry the charger or a bulky power bank, and can charge their electronic devices as fast as with a cable. Major mobile manufacturers are committing to wireless charging by joining the industry alliances and launching compatible products.

Users on the move, who put their mobiles down to charge for a few minutes – say, during a break or in a meeting — need the device to be ready to go again when they are. To enable this, the Wireless Power Consortium (WPC) that manages the Qi specification — a widely adopted industry standard — has introduced the Extended Power profile for faster charging. By raising the maximum charging power from 5W to 15W, this new profile enables devices to be charged up to three times more quickly.

One of the market’s first wireless-charging controllers to support Qi Extended Power, ST’s STWBC-EP combines best-in-class energy efficiency, consuming just 16mW in standby and able to wirelessly transfer more than 80% of the total input power, with unique features created by ST to enhance the user experience. These include a patented solution enhancing active presence detection to wake the system quickly when a compatible object is presented for charging. The patented technology also enhances the performance of Foreign Object Detection (FOD), to cut power and prevent overheating if objects containing metals are brought too close to the charger. Other unique innovations enhance power control and energy transfer to maximize efficiency and ease of use.

“ST’s Advanced Wireless-Charging chip enables manufacturers to create new, high-power products that offer superior features and efficiency,” said Domenico Arrigo, General Manager, Industrial and Power Conversion Division, STMicroelectronics. “The Qi Extended Power support dramatically shortens charging time and our patented detection and safety innovations greatly improve safety and ease of use.”

The STWBC-EP provides the level of integration allowing to simplify charger design while providing the flexibility to work with supply voltages ranging from 5V USB power up to 12V.

To help accelerate time to market for product developers, ST has created an associated reference design with a Qi 15W ready-built transmitter board and documentation to get started. ST also has a 15W receiver chip (STWLC33) for use in high-speed chargeable devices, which developers can use to complete their applications.

ST’s new wireless-charging chip will be showcased at the Qi Wireless Power Developers Conference and Tradeshow held in San Francisco on November 16-17.

The STWBC-EP is available now, as a 32-lead QFN (5mm x 5mm) device, priced from $3.175 for 1000 pieces.

 

A*STAR’s Institute of Microelectronics (IME) has established a development line to accelerate the development of fan-out wafer level packaging (FOWLP) capabilities for next-generation Internet of Things (IoT) technologies. The FOWLP development line, which is built upon existing infrastructure at IME’s facilities at Singapore Science Park II, and its new facilities at Fusionopolis Two, will allow IME and its partners (see Annex A for list of partners) to develop technologies that serve a wide range of markets such as that of consumer electronics, healthcare and automotive.

The IoT is set to become the next growth driver for the semiconductor industry, as demand for internet-connected devices continues to soar. FOWLP is an emerging breakthrough chip packaging technology platform aimed at meeting the technology requirements of next-generation electronic devices that require ultra- low power consumption rates, smaller package profiles, higher performance; and all made at a lower cost.

IME’s FOWLP development line is equipped with fully automated tools that can perform the “mold-first” and “Re-Distribution Layer (RDL)-first” method in multi- chip fabrication. The “RDL-first” method is expected to achieve a higher reliability rate compared to the conventional “mold-first” method traditionally used by the semiconductor industry. IME and its partners will jointly develop tools and processes for next-generation FOWLP technologies such as high speed Copper (Cu) pillar plating, Physical Vapor Deposition (PVD) process to control the wafer warpage, moldable underfilling for Chip-to-Wafer, as well as over molding on wafer with vertical Cu pillar/Cu wire interconnections using wafer level compression molding, plasma descum of small vias and warpage adjustment, etc.

To unlock the potential of FOWLP and accelerate the development and adoption of these innovative process technologies by the industry, IME has also formed a consortium comprising leading OSATs, Materials, Equipment, EDA, Fabless partners (see Annex A for list of consortium members).

The FOWLP development line consortium will allow members across the value chain to co-share resources on an open innovation platform, and draw upon IME’s rich portfolio of advanced packaging capabilities to address the complexities in system scaling and heterogeneous system integration. The FOWLP development line will be a test-bedding platform through which consortium members could gain new insights on requirements of FOWLP by testing and developing new processes, paving the way for high-volume manufacturing.

The FOWLP development line utilises tools already in use in major OSATs, and will allow processes, materials and integration flows developed at IME to be smoothly transferred. Through this development line, fabless companies could also make quicker decisions on package structure, integration flows, processes, materials and equipment for their new products; so materials and equipment suppliers could expedite the development of their products and increase their adoption.

“The launch of IME’s FOWLP development line and consortium will enable us to advance pre-competitive R&D that positions the semiconductor industry for growth opportunities in the thriving IoT market. Through an open and collaborative approach, the consortium will drive the development and the transfer of innovative technologies from pilot-scale to commercial production more easily and quickly,” said Dr. Tan Yong Tsong, Executive Director, IME.

“We are extremely proud to be a part of IME’s FOWLP consortium and play an active role in this great initiative. This broad industry cooperation will help solve one of the largest challenges faced by the semiconductor industry in the area of achieving higher density in advanced packaging. ERS is committed to developing new thermo-management solutions to enable next generation of FOWLP technologies,” said Mr. Klemens Reitinger, Chief Executive Officer, ERS Electronic GmbH.

“We are pleased to be collaborating with IME in this FOWLP development line consortium (DLC). We have benefitted from the experience in the previous consortium on High Density FOWLP, and are confident that with our combined experience and knowledge, the consortium will accelerate the development of FOWLP and establish an innovative cost-effective manufacturing process to further the mass adoption of FOWLP,” said Mr. Tong Liang Cheam, Vice President of Corporate Strategy, Kulicke & Soffa.

“It’s exciting to participate in this new FOWLP development line at IME to advance chip packaging. Nordson has a successful history of working on innovations in the semiconductor packaging industry, and this consortium is positioned well to produce excellent solutions,” said Mr. Joseph Stockunas, Vice President, Advanced Technology – Electronics Systems, Nordson Corporation.

“It is through collaborative efforts, such as that of the FOWLP development line and consortium that the semiconductor ecosystem can advance. Our engagement with the consortium will not only benefit our customers, but the industry as a whole in driving the adoption of this technology for emerging High Bandwidth Memory (HBM) and diverse IoT applications,” said Mr. Asim Salim, Vice President of Manufacturing Operations, Open-Silicon. “Through Open- Silicon’s extensive experience in 2.5D ASIC design, and the expertise of the consortium, issues like cost will be mitigated, thus enabling OEMs of all sizes to adopt FOWLP technology.”

“We are delighted to be a part of IME’s FOWLP development line consortium and continue to play an active role in this open innovation initiative. Industry-wide cooperation is key in overcoming the many challenges faced today by the electronics packaging industry. Orbotech is committed to developing new cost- efficient solutions to enable the next generation of advanced packaging technologies, which in turn will impact the industry’s next inflection point,” said Dr. Abraham Gross, Chief Technology Officer and Head of Innovation, Orbotech.

“As demand for high speed, high bandwidth data connectivity in consumer electronics continues to grow, the performance and cost challenges limiting the implementation of high frequency millimeter wave applications have the potential to be addressed with FOWLP solutions. We look forward to working with the FOWLP development line consortium to realise the benefits of FOWLP technology for mmWave antennae devices in emerging markets such as automotive and the Internet of Things (IoT),” said Mr. Shim Il Kwon, Chief Technology Officer, STATS ChipPAC.

The Institute of Microelectronics (IME) is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR).

Enabling the A.I. era


November 8, 2017

BY PETE SINGER, Editor-in-Chief

There’s a strongly held belief now that the way in which semiconductors will be designed and manufactured in the future will be largely determined by a variety of rapidly growing applications, including artificial intelligence/deep learning, virtual and augmented reality, 5G, automotive, the IoT and many other uses, such as bioelectronics and drones.

The key question for most semiconductor manufacturers is how can they benefit from these trends? One of the goals of a recent panel assembled by Applied Materials for an investor day in New York was to answer that question.

The panel, focused on “enabling the A.I. era,” was moderated by Sundeep Bajikar (former Sellside Analyst, ASIC Design Engineer). The panelists were: Christos Georgiopoulos (former Intel VP, professor), Matt Johnson (SVP in Automotive at NXP), Jay Kerley (CIO of Applied Materials), Mukesh Khare (VP of IBM Research) and Praful Krishna (CEO of Coseer). The panel discussion included three debates: the first one was “Data: Use or Discard”; the second was “Cloud versus Edge”; and the third was “Logic versus Memory.”

“There’s a consensus view that there will be an explosion of data generation across multiple new categories of devices,” said Bajikar, noting that the most important one is the self-driving car. NXP’s Johnson responded that “when it comes to data generation, automotive is seeing amazing growth.” He noted the megatrends in this space: the autonomy, connectivity, the driver experience, and electrification of the vehicle. “These are changing automotive in huge ways. But if you look underneath that, AI is tied to all of these,” he said.

He said that estimates of data generation by the hour are somewhere from 25 gigabytes per hour on the low end, up to 250 gigabytes or more per hour on the high end. or even more in some estimates.

“It’s going to be, by the second, the largest data generator that we’ve seen ever, and it’s really going to have a huge impact on all of us.”

Intel’s Georgiopoulos agrees that there’s an enormous amount of infrastructure that’s getting built right now. “That infrastructure is consisting of both the ability to generate the data, but also the ability to process the data both on the edge as well as on the cloud,” he said. The good news is that sorting that data may be getting a little easier. “One of the more important things over the last four or five years has been the quality of the data that’s getting generated, which diminishes the need for extreme algorithmic development,” he said. “The better data we get, the more reasonable the AI neural networks can be and the simpler the AI networks can be for us to extract information that we need and turn the data information into dollars.” Check out our website at www.solid-state.com for a full report on the panel.

Kyma Technologies, Inc., a developer of advanced wide bandgap semiconductor materials technologies, announced it has used its new K200 hydride vapor phase epitaxy (HVPE) growth tool to produce high quality 200mm diameter HVPE GaN on QST (QROMIS Substrate Technology) templates.

Today’s announcement of Kyma’s development of 200mm diameter GaN on QST templates follows its announcement in 2016 of its demonstration of 150mm diameter GaN on QST templates in partnership with QROMIS, Inc. (formerly Quora Technology, Inc.) and its recent announcement of the commissioning of Kyma’s K200 HVPE growth tool.

200-mm GaN on QST® Template

Pictured is one of the demonstrated 200mm diameter HVPE GaN on QST templates which consists of 10 microns of HVPE GaN grown on a 5 micron MOCVD GaN on QST wafer provided by QROMIS, Inc. X-ray diffraction rocking curve linewidths for the templates fall in the range of 250 and 330 arc-sec for the symmetric {002) and asymmetric {102} XRD peaks, respectively, which is consistent with high structural quality. Low wafer bow (~50 microns) and smooth surface morphology suggest these materials should support high performance device manufacturing.

Kyma’s newly constructed K200 HVPE tool represents a first for the industry and was designed by Kyma engineers to enable uniform and rapid growth of high quality GaN on a number of different substrates.

Keith Evans, President & CEO, commented, “We have successfully transferred the process for making high quality GaN to our K200 HVPE tool. The structural quality of the GaN produced on QROMIS’ QST substrate is excellent. We are currently engaging with customers interested in large diameter GaN on QST templates.”

Kyma and Qromis are partnered for this work under a Kyma-led US DOE Phase IIB SBIR with award number DE-SC0009653.

QROMIS recently began manufacturing 200-mm QST substrates and GaN-on-QST wafers using its foundry partner Vanguard International Semiconductor (VIS). VIS is planning to offer GaN power device manufacturing services on 8-inch diameter QST platform in 2018.

QROMIS co-founder & CEO Cem Basceri added, “QROMIS’ CMOS fab-friendly 200-mm diameter QST substrates and GaN-on-QST wafers represent a disruptive technology, enabling GaN epitaxy from a few microns to hundreds of microns for GaN power applications ranging from 100V to 1,500V or beyond in lateral, quasi vertical or vertical device forms, and device manufacturing on the same 8-inch or 12-inch diameter platform at Si power device cost. Kyma’s K200 HVPE technology represent an important value-add to QST-based GaN power device manufacturing by enabling the low cost deposition of a thicker and lower defect density GaN surface than is practically achievable using MOCVD growth alone.”

Kyma is also teamed with a semiconductor equipment OEM to manufacture K200 HVPE tools for customers who prefer to bring Kyma’s HVPE GaN growth process in-house.

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing.

BY STACY WEGNER, Ottawa, Canada, and JEONGDONG CHOE, Ottawa, Canada

TechInsights analysts have been keeping an intent watch on where technology has progressed, how it’s changing, and what new developments are emerging. At the end of the first quarter, our analysts shared their insights and thoughts about what to keep an eye on as the year unfolds. In this article, they provide an update on what 2017 has delivered so far.

Intelligent, connected devices

As we wrote earlier this year, in 2016, wearables were extremely interesting mainly because there was so much uncertainty around whether or not the market would be viable. Some, no, many, say the wearables market will cool off and possibly just expire. At TechInsights, we do will not speculate about whether this market is going to survive. We will report what we find and analyze what is currently being sold. Apple, Samsung, and Huawei have all released smartwatches for what would parallel a “flagship” in the mobile market (FIGURE 1). Fitness bands are becoming even ”smarter” and combining sensors where possible. Perhaps one of the most notable developments is Nokia’s acquisition and complete integration of Withings into its existing brands.

Screen Shot 2017-11-07 at 12.24.01 PM

We are witnessing the “rise of the machines,” in products from scales and hair brushes to rice cookers. Primarily these devices offer consumers convenience. For example, with a connected scale, instead of recording your weight manually, the smart scales do the job for you, syncing with various health apps so you can track your weight over time. The connected hair brush provides insights into your hair’s manageability, frizziness, dryness, split ends and breakage to provide a hair quality score. Brushing patterns, pressure applied and brush stroke counts are analyzed to measure effectiveness of brushing habits and a personal diagnosis is provided with tips and real-time product recommendations. The most common connected devices include refrigerators, lights, washing machines, thermostats, and televisions.

One dominant example is the ever-popular Amazon Echo, which has taken on a life of its own and is generating spin-off markets and competition. In July, it was reported that Amazon’s Alexa voice platform passed 15,000 skills — the voice-powered apps that run on devices like the Echo speaker, Echo Dot, newer Echo Show and others. The figure is up from the 10,000 skills Amazon officially announced in February. Amazon’s Alexa is building out an entire voice app ecosystem putting it much further ahead than its nearest competitor. The success seen with Echo has motivated other companies like Google, Lenovo, LG, Samsung and Apple to release compet- itive speakers, however it is estimated that Amazon is expected to control 70 percent of the market this year. In addition, Amazon and Microsoft recently announced a partnership to better integrate their digital assistants. This cross-platform integration provides users with access to Cortana features that Alexa is missing, and vice versa. Finally, the high- performance far-field microphones found in Amazon Echo products may soon find their way to other hardware companies as Amazon announced that the technology is available to those who want to integrate into the Alexa Experience. With its new reference solution, it’s never been easier for device makers to integrate Alexa and offer their customers the same voice experiences.

In the mobile market overall, we are seeing a strong emergence of devices targeted for the very hot market of India. The mobile devices for this market range from supporting 15 or more cellular bands to as few as five cellular bands, and that is for smart- phones. At TechInsights, we will be analyzing OEMs in India like Micromax, Intex, and Lava to see how they approach dealing with strong competitors like Samsung and Xiaomi.

Memory devices

In early 2017, 32L and 48L 3D NAND products were common and all the NAND players were eager to develop next generation 3D NAND products such as 64L and 128L. 3D NAND has been jumping into 64L (FIGURE 2). Samsung, Western Digital, Toshiba, Intel, and Micron already revealed CS or mass-products on the market. SK Hynix also showed their 72L NAND die as a CS product. In the second half of this year, we will see 64L and 72L NAND products on the commercial market. For n+1 generation with 96L or 128L, we expect that two-stacked cell array architecture for 3D NAND would be adopted in 2018. Micron/Intel will keep their own FG based 3D NAND cell structure for the next generation.

Screen Shot 2017-11-07 at 12.24.10 PM

Referring to DRAM, all the major players already used their advanced process technology for cell array integration such as an advanced ALD for high-k dielectrics, low damage plasma etching and honeycomb capacitor structure. Buried WL, landing pad and plug for a capacitor node, and MESH structure are still main stream. Samsung 18nm DRAM products for DDR4 and LPDDR4X are on the market. SK Hynix and Micron will reveal the same tech node DRAM products in this year. n+1 gener- ation with 15nm or 16nm node will be next in 2018. Once 6F2 15nm DRAM cell technology is successful, 4F2 DRAM products such as a capacitorless DRAM might be delayed. In 2018, 18nm and 15nm DRAM technology will be used for GDDR6 and LPDDR5.

When it comes to emerging memory, 3D XPoint memory technology is a hot potato (FIGURE 3). The XPoint products from Intel are on the market as an Optane SSD with 16GB and 32GB. Performance including retention, reliability and speed are not matched as expected, but they used a double stacked memory cell between M4 and M5 on the memory array. It’s a PCM with GST based material. An OTS with Se-As-Ge-Si is added between the PCM and the electrode (WL or BL). We expect to see multiple (triple or quadruple) stacked XPoint memory architecture within a couple years. For other emerging memory such as STT-MRAM, PCRAM and ReRAM, we’re waiting on some commercial products from Adesto (CBRAM 45nm, RM33 series) and Everspin (STT-MRAM pMTJ 256Mb, AUP-AXL-M128).

Screen Shot 2017-11-07 at 12.24.21 PM

Conclusion

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing. As our analysts continue to examine and reveal the innovations others can’t inside advanced technology, we will continue to share our findings on these and new technologies as they emerge, including how they are used, how they impact the market, and how they will be changed by the next discovery or invention.

Radiant Vision Systems, a provider of high-resolution imaging solutions for automated visual analysis of devices and surfaces, announces the release of the INSPECT.assembly system, a new turnkey automated visual inspection station for in-line assembly verification. The INSPECT.assembly is fully-integrated with Radiant technology and configured to precise tolerances to meet production-level inspection needs of complex electronic assemblies. The INSPECT.assembly system detects the presence, position, and integrity of components including screws, cables, connectors, and other critical features before final device enclosure to automate assembly inspection.

radiant visions

“Electronics manufacturing processes today are largely automated. However, final inspection for board-based connected assemblies has lacked an effective automated solution that ensures both consistency and accuracy,” says Davis Bowling, Radiant’s Regional Account Manager for assembly verification applications. “At the final stages of production where internal components are verified – before electronics are enclosed before or after functional testing – human inspectors remain the primary inspection method. This is due to the human’s superior visual acuity and judgment over typical machine vision systems for complex visual analysis. Humans can quickly detect very subtle defects in a variety of assembly contexts, even as parts change. However, human inspection lacks an automated system’s repeatability. To apply an automated solution in these contexts, the technology must offer the same level of visual acuity and judgment to ensure failures do not escape or result after goods are shipped.”

Radiant’s new INSPECT.assembly system is a turnkey inspection station that employs ProMetric® Y imaging systems with camera resolution (up to 29 megapixels) and dynamic range (above 70 dB) far exceeding the specifications of typical machine vision systems. Applied in photometric measurement of light and color in displays and backlit components, ProMetric cameras capture fine-detail images with a level of precision that rivals human visual acuity. Because INSPECT.assembly is fully-integrated with Radiant camera, lighting, fixturing, and software, Radiant engineers are able to design each INSPECT.assembly to match the specifications of each customer application. This advanced vision technology solves critical inspection challenges through a combination of the image registration & analysis functions of the camera with proprietary machine vision “super tools” in INSPECT Software, which blend multiple machine vision software algorithms in a single tool to enable comprehensive analysis of specific features. For instance, a tool can be engineered with the unique algorithms required to locate the routing path of a cable to ensure that it is properly seated around guides on a board-based assembly.

“Capturing precise feature flaws during final inspections is critical not only for preventing functional failures in the manufacturing process, but also latent failures that may occur after shipment,” states Bowling. “A cable that is routed away from its guide may be pinched or damaged with repeated device use. A loose connector may detach with vibration. These issues may cause a device to fail after it has left the manufacturing facility, resulting in a return or potentially a broader product recall. The INSPECT.assembly’s imaging capability combined with custom-configured software allow manufacturers to catch subtle errors like these that human inspectors, standard machine vision systems, and functional testing may miss.”

Radiant’s new INSPECT.assembly system rivals human visual acuity and judgment for detecting defects while quantifying visual data for automated operations, bridging the gap between human and machine vision inspection for the most challenging assemblies. Occupying the same physical footprint as a human operator on the line, the INSPECT.assembly system easily rolls onto moving conveyers, adjusting to heights from 525-950 mm. The system features a touch screen for results monitoring, adjustment of inspection tolerances, and part changes. The system’s INSPECT Software is pre-configured with multiple inspection tool recipes specific to each part, enabling adaptability to line changeover. The system also offers reporting functionality, barcode reading, and data output for traceability of inspection results and process control to improve operations for reducing product returns and recalls.

MagnaChip Semiconductor Corporation(NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor products, announced today it now offers a 0.35 micron 700V Ultra-High Voltage process technology (UHV) that reduces mask counts, manufacturing time and cost for power-related AC-DC products. This UHV process technology offers 700V nLDMOS, 700V JFET, and 5.5V CMOS devices that are suitable for manufacturing AC-DC converter ICs and LED driver ICs.

The demand for AC-powered products in home appliances continues to increase, creating the need for highly efficient and cost-competitive AC-DC converter ICs, AC-DC chargers and LED driver ICs.  MagnaChip’s 0.35 micron 700V UHV process technology is a suitable match to manufacture these types of power-related products.

MagnaChip provides various types of UHV technology to meet the diverse demands of the customers. HP35ULB700, the newly developed UHV process, eliminates five photolithography steps through process simplification compared with MagnaChip’s previous generation of UHV technology, making it possible to reduce manufacturing cost and to accelerate the time to market. Among the devices offered in HP35ULB700 are 700V low Ron nLDMOS, 500V nLDMOS, 700V JFET, 5.5V CMOS, BJT, 700V resistor, BP cap, and MIM and fuse. All these devices enable the integrated solution of AC-DC converter ICs and LED driver ICs. The 700V low Ron nLDMOS devices offer improved specific-on-resistance of 150 mohm·cm2. In addition, the devices enable various design schemes, including the possibility to separate or connect the source and the bulk in nLDMOS.

YJ Kim, MagnaChip’s Chief Executive Officer, commented, “Our  0.35 micron 700V UHV technology  provides our foundry customers with a high-performance, highly efficient manufacturing process for AC-DC converter ICs and LED driver ICs for various LED lighting applications.” Mr. Kim added, “To meet the diverse customer requirements, MagnaChip will continue to develop new UHV technologies such as customer-specific UHV processes with additional option devices.”

A mineral discovered in Russia in the 1830s known as a perovskite holds a key to the next step in ultra-high-speed communications and computing.

Researchers from the University of Utah’s departments of electrical and computer engineering and physics and astronomy have discovered that a special kind of perovskite, a combination of an organic and inorganic compound that has the same structure as the original mineral, can be layered on a silicon wafer to create a vital component for the communications system of the future. That system would use the terahertz spectrum, the next generation of communications bandwidth that uses light instead of electricity to shuttle data, allowing cellphone and internet users to transfer information a thousand times faster than today.

The new research, led by University of Utah electrical and computer engineering professor Ajay Nahata and physics and astronomy Distinguished Professor Valy Vardeny, was published Monday, Nov. 6 in the latest edition of Nature Communications.

The terahertz range is a band between infrared light and radio waves and utilizes frequencies that cover the range from 100 gigahertz to 10,000 gigahertz (a typical cellphone operates at just 2.4 gigahertz). Scientists are studying how to use these light frequencies to transmit data because of its tremendous potential for boosting the speeds of devices such as internet modems or cell phones.

Nahata and Vardeny uncovered an important piece of that puzzle: By depositing a special form of multilayer perovskite onto a silicon wafer, they can modulate terahertz waves passing through it using a simple halogen lamp. Modulating the amplitude of terahertz radiation is important because it is how data in such a communications system would be transmitted.

Previous attempts to do this have usually required the use of an expensive, high-power laser. What makes this demonstration different is that it is not only the lamp power that allows for this modulation but also the specific color of the light. Consequently, they can put different perovskites on the same silicon substrate, where each region could be controlled by different colors from the lamp. This is not easily possible when using conventional semiconductors like silicon.

“Think of it as the difference between something that is binary versus something that has 10 steps,” Nahata explains about what this new structure can do. “Silicon responds only to the power in the optical beam but not to the color. It gives you more capabilities to actually do something, say for information processing or whatever the case may be.”

Not only does this open the door to turning terahertz technologies into a reality — resulting in next-generation communications systems and computing that is a thousand times faster — but the process of layering perovskites on silicon is simple and inexpensive by using a method called “spin casting,” in which the material is deposited on the silicon wafer by spinning the wafer and allowing centrifugal force to spread the perovskite evenly.

Vardeny says what’s unique about the type of perovskite they are using is that it is both an inorganic material like rock but also organic like a plastic, making it easy to deposit on silicon while also having the optical properties necessary to make this process possible.

“It’s a mismatch,” he said. “What we call a ‘hybrid.'”

Nahata says it’s probably at least another 10 years before terahertz technology for communications and computing is used in commercial products, but this new research is a significant milestone to getting there.

“This basic capability is an important step towards getting a full-fledged communications system,” Nahata says. “If you want to go from what you’re doing today using a modem and standard wireless communications, and then go to a thousand times faster, you’re going to have to change the technology dramatically.”

Researchers at UC Berkeley and UC Riverside have developed a new, ultrafast method for electrically controlling magnetism in certain metals, a breakthrough that could lead to greatly increased performance and more energy-efficient computer memory and processing technologies.

In this schematic of a magnetic memory array, an ultrafast electrical pulse switches a magnetic memory bit.

In this schematic of a magnetic memory array, an ultrafast electrical pulse switches a magnetic memory bit.

The findings of the group, led by Berkeley electrical engineering and computer sciences (EECS) professor Jeffrey Bokor, are published in a pair of articles in the journals Science Advances (Vol. 3, No. 49, Nov. 3, 2017) and Applied Physics Letters (Vol. III, No. 4, July 24, 2017).

Computers use different kinds of memory technologies to store data. Long-term memory, typically a hard disk or flash drive, needs to be dense in order to store as much data as possible. But the central processing unit (CPU) — the hardware that enables computers to compute — requires its own memory for short-term storage of information while operations are executed. Random Access Memory (RAM) is one example of such short-term memory.

Reading and writing data to RAM needs to be extremely fast in order to keep up with the CPU’s calculations. Most current RAM technologies are based on charge (electron) retention, and can be written at rates of billions of bits per second (or bits/nanosecond). The downside of these charge-based technologies is that they are volatile, requiring constant power or else they will lose the data.

In recent years, magnetic alternatives to RAM, known as Magnetic Random Access Memory (MRAM), have reached the market. The advantage of magnets is that they retain information even when memory and CPU are powered off, allowing for energy savings. But that efficiency comes at the expense of speed. A major challenge for MRAM has been to speed up the writing of a single bit of information to less than 10 nanoseconds.

“The development of a non-volatile memory that is as fast as charge-based random-access memories could dramatically improve performance and energy efficiency of computing devices,” says Bokor. “That motivated us to look for new ways to control magnetism in materials at much higher speeds than in today’s MRAM.”

“Inspired by recent experiments in the Netherlands on ultrafast magnetic switching using sub-picosecond duration laser pulses, we built special circuits to study how magnetic metals respond to electrical pulses as short as a few trillionths of a second,” or picoseconds, says coauthor Yang Yang (M.S.’13 Ph.D.’17 MSE). “We found that in a magnetic alloy made up of gadolinium and iron, these fast electrical pulses can switch the direction of the magnetism in less than 10 picoseconds. That is orders of magnitude faster than any other MRAM technology.”

“The electrical pulse temporarily increases the energy of the iron atom’s electrons,” says Richard Wilson, currently an assistant professor of mechanical engineering at UC Riverside who began his work on this project as a postdoctoral researcher in EECS at Berkeley.  “This increase in energy causes the magnetism in the each of the iron and gadolinium atoms to exert torque on one another, and eventually leads to a reorientation of the metal’s magnetic poles. It’s a completely new way of using electrical currents to control magnets.”

After their initial demonstration of electrical writing in the special gadolinium-iron alloy, the research team sought ways to expand their method to a broader class of magnetic materials.  “The special magnetic properties of the gadolinium-iron alloy are what makes this work,” says Charles-Henri Lambert, a Berkeley EECS postdoc. “Therefore, finding a way to expand our approach for fast electrical writing to a broader class of magnetic materials was an exciting challenge.”

Addressing that latter challenge was the subject of a second study, published in Applied Physics Letters in July.  “We found that when we stack a single-element magnetic metal such as cobalt on top of the gadolinium-iron alloy, the interaction between the two layers allows us to then manipulate the magnetism of the cobalt on unprecedented time-scales as well,” says Jon Gorchon, a postdoctoral research in the Materials Sciences Division at Lawrence Berkeley Lab and in EECS at UC Berkeley.

“Together, these two discoveries provide a route toward ultrafast magnetic memories that enable  a new generation of high-performance, low power computing processors with high-speed, non-volatile memories right on chip, ” Bokor says.

Additional team members include Akshay Pattabi, a Berkeley EECS Ph.D. candidate, and Berkeley EECS professor Sayeef Salahuddin. The research was supported by grants from the National Science Foundation and the U.S. Department of Energy.