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Microsemi Corporation (Nasdaq: MSCC), a provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the company’s new Mi-V™ ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family. The announcement comes as the company also introduces Mi-V RV32IMA and additional field programmable gate array (FPGA)-based soft CPU solutions ideally suited for designs utilizing RISC-V open instruction set architectures (ISAs).

“As a leader in RISC-V, we are pleased Microsemi is the first tier one vendor to build out a complete open RISC-V ecosystem, which not only supports our needs, but contributes to the entire development community,” said Jim Aralis, chief technology officer and vice president of advanced development at Microsemi. “Customers can now select RISC-V for their new designs knowing a tier one vendor committed to the success of this technology is providing all the necessary tools to confidently use RISC-V soft CPUs in their products.”

RISC-V, an ISA which is a standard open architecture under the governance of the RISC-V Foundation, offers numerous benefits, including portability as well as enabling the open source community to test and improve cores at a faster pace than closed ISAs. As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures. Microsemi’s new Mi-V ecosystem brings together a number of industry leaders involved in the development of RISC-V to leverage their capabilities and streamline RISC-V designs for customers.

“Micrium is pleased to join Microsemi’s Mi-V ecosystem with our highly dependable µC/OS-II real-time kernel, a full-featured embedded operating system,” said Jean Labrosse, co-founder and chief architect at Micrium. “As RISC-V continues to grow in popularity, we look forward to working closely with Microsemi to support accelerated adoption of its RISC-V soft CPU product offerings as well as the entire ecosystem’s RISC-V advancements.”

Microsemi’s Mi-V ecosystem, part of Microsemi’s Accelerate Ecosystem, contains a number of components. Design tools include Microsemi’s SoftConsole Eclipse-based integrated development environment (IDE), the firmware catalog and Libero PolarFire system-on-chip (SoC). Operating systems include Express Logic’s ThreadX, Huawei LiteOS and Micrium µC/OS-II. Boards include the RTG4™ development kit, IGLOO™2 RISC-V board from Future Electronics, PolarFire Evaluation Kit and more. Debug dongles from Microsemi and Olimex, first-stage bootloaders and numerous soft peripherals are also included. Example projects, drivers and firmware are all available on GitHub, the world’s largest repository of open source software.

Deployment of soft CPUs implemented with the R11C-V ISA is automatic and delivered to the user’s desktop via Microsemi’s IP Catalog. No end user license agreements are needed to gain access to the soft CPUs. Using RISC-V soft CPUs within the Mi-V ecosystem is simple, easy and free.

“Express Logic is pleased to be a foundational part of Microsemi’s Mi-V RISC-V ecosystem,” said William E. Lamie, President, Express Logic. “Our X-Ware Internet-of-Things (IoT) platform, including the industry-leading ThreadX RTOS with over 6.2 billion deployments, is the preferred embedded software platform for all designs requiring industrial-grade run-time solutions—making us an ideal fit for this new consortium.”

Offering low power and an open architecture, Microsemi’s PolarFire™, RTG4™, SmartFusion™2 and IGLOO™2 field programmable gate array (FPGA)-based RISC-V soft CPU cores are ideal for developing a wide variety of applications within the aerospace and defense, industrial and security markets. The Mi-V soft CPU cores make them particularly suitable for applications including guided munitions, IoT, secure communications and wireline bridging.

“The open source, royalty-free RISC-V instruction set creates a new business model for CPU designers that is garnering increasing interest and support,” said Linley Gwennap, principal analyst with The Linley Group, which named the RISC-V ISA “Best Technology of 2016” at its annual Analysts’ Choice Awards in January 2017. “By introducing the RV32IM CPU core with support from the Mi-V ecosystem, Microsemi will play an important role in boosting the adoption of RISC-V.”

Through Microsemi’s early involvement in the creation of the RISC-V Foundation, the company has an established leadership role in the emerging standard and ecosystem and is working closely with the nonprofit to ensure the ISA becomes an industry standard for a wide variety of computing devices. Ted Speers, head of product architecture and planning for Microsemi’s Programmable business unit, was appointed to the inaugural board of directors of the RISC-V Foundation in July 2016, and Ted Marena, director of SoC FPGA marketing, was recently sworn in as chair of the RISC-V Marketing Committee after serving as vice-chair since August 2016. Marena will also be the featured speaker at EE World Online’s upcoming webinar titled, “The RISC-V ecosystem is ready for prime time. Get started here!” on Oct. 25, 2017. Attendees can register online to join this event.

The Mi-V Ecosystem began as part of the Microsemi Accelerate Ecosystem, a program designed to reduce time to market for end customers and time to revenue for ecosystem participants. Microsemi’s Accelerate Ecosystem brings together leading silicon, intellectual property (IP), systems, software and design experts to deliver solutions for end customers.

Professor Martijn Kemerink of Linköping University has worked with colleagues in Spain and the Netherlands to develop the first material with conductivity properties that can be switched on and off using ferroelectric polarisation.

The phenomenon can be used for small and flexible digital memories of the future, and for completely new types of solar cells.

In an article published in the prestigious scientific journal Science Advances, the research group shows the phenomenon in action in three specially built molecules, and proposes a model for how it works.

This is the first material with conductivity properties that can be switched on and off using ferroelectric polarization. Credit: Thor Balkhed

This is the first material with conductivity properties that can be switched on and off using ferroelectric polarization. Credit: Thor Balkhed

“I originally had the idea many years ago, and then I just happened to meet Professor David González-Rodríguez, from the Universidad Autónoma de Madrid, who had constructed a molecule of exactly the type we were looking for,” says Martijn Kemerink.

The organic molecules that the researchers have built conduct electricity and contain dipoles. A dipole has one end with a positive charge and one with a negative charge, and changes its orientation (switches) depending on the voltage applied to it. In a thin film of the newly developed molecules, all the dipoles can be caused to switch at exactly the same time, which means that the film changes its polarisation. The property is known as ferroelectricity. In this case, it also leads to a change in the conductivity, from low to high or vice versa. When an electrical field with the opposite polarity is applied, the dipoles again switch direction. The polarisation changes, as does the ability to conduct current.

The molecules designed according to the model developed by the LiU researchers tend to spontaneously place themselves on top of each other to form a stack or a supramolecular wire, with a diameter of just a few nanometres. These wires can subsequently be placed into a matrix in which each junction constitutes one bit of information. This will make it possible in the future to construct extremely small digital memories with very high information density. The synthesis of the new molecules is, however, still too complicated for practical use.

“We have developed a model for how the phenomenon arises in principle, and we have shown experimentally that it works for three different molecules. We now need to continue work to build molecules that can be used in practical applications,” says Professor Martijn Kemerink, from Complex Materials and Devices at Linköping University, and principal author of the article.

Samsung Electronics Co., Ltd. announced today that 8-nanometer (nm) FinFET process technology, 8LPP (Low Power Plus), has been qualified and is ready for production.

The newest process node, 8LPP provides up to 10-percent lower power consumption with up to 10-percent area reduction from 10LPP through narrower metal pitch. 8LPP will provide differentiated benefits for applications including mobile, cryptocurrency and network/server, and is expected to be the most attractive process node for many other high performance applications.

As the most advanced and competitive process node before EUV is employed at 7nm, 8LPP is expected to rapidly ramp-up to the level of stable yield by adopting the already proven 10nm process technology.

“With the qualification completed three months ahead of schedule, we have commenced 8LPP production,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “Samsung Foundry continues to expand its process portfolio in order to provide distinct competitive advantages and excellent manufacturability based on what our customers and the market require.”

“8LPP will have a fast ramp since it uses proven 10nm process technology while providing better performance and scalability than current 10nm-based products,” said RK Chunduru, Senior Vice President of Qualcomm.

Details of the recent update to Samsung’s foundry roadmap, including 8LPP availability and 7nm EUV development, will be presented at the Samsung Foundry Forum Europe on October 18, 2017, in Munich, Germany. The Samsung Foundry Forum was held in the United States, South Korea and Japan earlier this year, sharing Samsung’s cutting-edge process technologies with global customers and partners.

 

To make continuous, strong and conductive carbon nanotube fibers, it’s best to start with long nanotubes, according to scientists at Rice University.

The Rice lab of chemist and chemical engineer Matteo Pasquali, which demonstrated its pioneering method to spin carbon nanotube into fibers in 2013, has advanced the art of making nanotube-based materials with two new papers in the American Chemical Society’s ACS Applied Materials and Interfaces.

The first paper characterized 19 batches of nanotubes produced by as many manufacturers to determine which nanotube characteristics yield the most conductive and strongest fibers for use in large-scale aerospace, consumer electronics and textile applications.

The researchers determined the nanotubes’ aspect ratio — length versus width — is a critical factor, as is the overall purity of the batch. They found the tubes’ diameters, number of walls and crystalline quality are not as important to the product properties.

Pasquali said that while the aspect ratio of nanotubes was known to have an influence on fiber properties, this is the first systematic work to establish the relationship across a broad range of nanotube samples. Researchers found that longer nanotubes could be processed as well as shorter ones, and that mechanical strength and electrical conductivity increased in lockstep.

The best fibers had an average tensile strength of 2.4 gigapascals (GPa) and electrical conductivity of 8.5 megasiemens per meter, about 15 percent of the conductivity of copper. Increasing nanotube length during synthesis will provide a path toward further property improvements, Pasquali said.

The second paper focused on purifying fibers produced by the floating catalyst method for use in films and aerogels. This process is fast, efficient and cost-effective on a medium scale and can yield the direct spinning of high-quality nanotube fibers; however, it leaves behind impurities, including metallic catalyst particles and bits of leftover carbon, allows less control of fiber structure and limits opportunities to scale up, Pasquali said.

“That’s where these two papers converge,” he said. “There are basically two ways to make nanotube fibers. In one, you make the nanotubes and then you spin them into fibers, which is what we’ve developed at Rice. In the other, developed at the University of Cambridge, you make nanotubes in a reactor and tune the reactor such that, at the end, you can pull the nanotubes out directly as fibers.

“It’s clear those direct-spun fibers include longer nanotubes, so there’s an interest in getting the tubes included in those fibers as a source of material for our spinning method,” Pasquali said. “This work is a first step toward that goal.”

The reactor process developed a decade ago by materials scientist Alan Windle at the University of Cambridge produces the requisite long nanotubes and fibers in one step, but the fibers must be purified, Pasquali said. Researchers at Rice and the National University of Singapore (NUS) have developed a simple oxidative method to clean the fibers and make them usable for a broader range of applications.

The labs purified fiber samples in an oven, first burning out carbon impurities in air at 500 degrees Celsius (932 degrees Fahrenheit) and then immersing them in hydrochloric acid to dissolve iron catalyst impurities.

Impurities in the resulting fibers were reduced to 5 percent of the material, which made them soluble in acids. The researchers then used the nanotube solution to make conductive, transparent thin films.

“There is great potential for these disparate techniques to be combined to produce superior fibers and the technology scaled up for industrial use,” said co-author Hai Minh Duong, an NUS assistant professor of mechanical engineering. “The floating catalyst method can produce various types of nanotubes with good morphology control fairly quickly. The nanotube filaments can be collected directly from their aerogel formed in the reactor. These nanotube filaments can then be purified and twisted into fibers using the wetting technique developed by the Pasquali group.”

Pasquali noted the collaboration between Rice and Singapore represents convergence of another kind. “This may well be the first time someone from the Cambridge fiber spinning line (Duong was a postdoctoral researcher in Windle’s lab) and the Rice fiber spinning line have converged,” he said. “We’re working together to try out materials made in the Cambridge process and adapting them to the Rice process.”

The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel, may go down as one of the most memorable editions for the sheer variety and depth of its talks, sessions, courses and events.

Among the most-anticipated talks are presentations by Intel and Globalfoundries, which will each detail their forthcoming competing FinFET transistor technology platforms in a session on Wednesday morning. FinFET transistors are a major driver of the continuing progress of the electronics industry, and these platforms are as important for their commercial potential as they are for their technical innovations.*

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations, along with other events.

“Those who attend IEDM 2017 will find much that is familiar, beginning with a technical program describing breakthroughs in areas ranging from mainstream CMOS technology to innovative nanoelectronics to medical devices. The Sunday Short Courses are also a perennial favorite because they are not only comprehensive but are also taught by accomplished world experts,” said Dr. Barbara De Salvo, Scientific Director at Leti. “But we have added some new features this year. One is a fourth Plenary session, on Wednesday morning, featuring Nobel winner Hiroshi Amano. Another is a revamped Tuesday evening panel. Not only will it focus on a topic of great interest to many people, it is designed to be more open and less formal.”

Other features of the IEDM 2017 include:

  • Focus Sessions on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current Status and Perspectives.
  • A vendor exhibition will be held, based on the success of last year’s event at the IEDM.
  • The IEEE Magnetics Society will again host a joint poster session on MRAM (magnetic RAM) in the exhibit area. New for this year, though, is that the Society will also hold its annual MRAM Global Innovation Forum on Thursday, Dec. 7 at the same hotel, enabling IEDM attendees to participate. (Refer to the IEEE Magnetics Society website.) The forum consists of invited talks by leading experts and a panel discussion.

Here are details of some of the events that will take place at this year’s IEDM:

90-Minute Tutorials – Saturday, Dec. 2
These tutorials on emerging technologies will be presented by leading technical experts in each area, with the goal of bridging the gap between textbook-level knowledge and cutting-edge current research.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec

Short Courses – Sunday, Dec. 3
The day-long Short Courses provide the opportunity to learn about important developments in key areas, and they enable attendees to network with the industry’s leading technologists.

Boosting Performance, Ensuring Reliability, Managing Variability in Sub-5nm CMOS, organized by Sandy Liao of Intel, will feature the following sections:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS,Cathyrn Christiansen, Globalfoundries
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights

Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang of TSMC, will feature the following sections:

  • Embedded Non Volatile Memory for Automotive Applications, Alfonso Maurelli, STMicroelectronics
  • 3D ReRAM: Crosspoint Memory Technologies, Nirmal Ramaswamy, Micron
  • Ferroelectric Memory in CMOS Processes, Thomas Mikolajick, Namlab
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive, Danny P. Shum, Globalfoundries
  • Embedded Memories for Energy-Efficient Computing, Jonathan Chang, TSMC
  • Abundant-Data Computing: The N3XT 1,000X, Subhasish Mitra, Stanford University

Plenary Presentations – Monday, Dec. 4

  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL
  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University. Dr. Amano received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting. His talk will be preceded by the Focus Session on silicon photonics.

Evening Panel Session – Tuesday evening, Dec. 5

  • Where will the Next Intel be Headquartered?  Moderator: Prof. Philip Wong, Stanford

Entrepreneurs Lunch
Jointly sponsored by IEDM and IEEE EDS Women in Engineering, this year’s Entrepreneurs Lunch will feature Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in Ohio. The moderator will be Prof. Leda Lunardi from North Carolina State University. Gras is an engineer by training and an entrepreneur by nature. After leaving her job as a NASA power systems engineer to work for on own startup company, she discovered a passion for building startup communities and helping technology-focused companies meet their goals. Named to the Forbes ’30 Under 30′ list in 2016, among many other recognitions and awards, Gras enjoys sharing her stories of founding a cleantech company with young entrepreneurs. She speaks on entrepreneurship, women in technology and clean energy at venues such as TEDx Budapest, the Pioneers Festival, and the IEEE WIE International Women’s Leadership Conference.

 

On 14-17 November in Munich, SEMICON Europa will co-locate with productronica for the first time, for a focus on innovation and the future of the electronics manufacturing supply chain. Gathering key stakeholders from across the electronics manufacturing supply chain, the extensive range and depth, programs and networking events make the platform a necessity for players across the European electronics industry. SEMICON Europa will take place at Messe München Hall B1.

An Opening Ceremony will include a welcome speech by Ajit Manocha, president and CEO of SEMI, followed by Laith Altimime, president, SEMI Europe, plus four keynotes:

  • Bosch Sensortec: Stefan Finkbeiner, CEO, on how environmental sensing can contribute to a better quality of life in the context of the IoT
  • Rinspeed Inc.: Frank M. Rinderknecht, founder and CEO, on how to create innovative technologies, materials and mobility means of tomorrow
  • SOITEC: Carlos Mazure, CTO, executive VP, on contributions and benefits of engineered substrates solutions and thin-layer transfer technologies, focusing on applications in the smart space
  • TSMC Europe: Maria Marced, president, on opportunities for new business models to apply in the Smart City

“We are at the brink of a new wave of innovation ─ called the “Fourth Industrial Revolution” or “Smart Manufacturing.” It’s driven by connected devices and smart applications known as the IoT. This presents many opportunities for closer collaborations at global level, connecting key players, key ecosystems and building on the strengths of players in the value chain,” said Laith Altimime, president of SEMI Europe.

New programs on Flexible Electronics, Materials, and Automotive expand SEMICON Europa’s impact:

Returning programs include:

Register for programs before 12 November for a discount: http://www.semiconeuropa.org/register

SEMICON Europa offers free programs available on the exhibition show floor, including the TechARENA sessions ─ from MedTech to Lithography, Smart Manufacturing and Photonics, and many other topics.

For the fourth time at SEMICON Europa, INNOVATION VILLAGE will bring early-stage technology companies, the semiconductor industry’s top strategic investors, and leading technology partners together. This year sponsors include the City of Dresden and Volkswagen.

More than ever, there are unique opportunities to network with peers and connect with a large number of stakeholders at SEMICON Europa as attendees gather at the SEMICON CXO Luncheon, SEMI Member Breakfast, and SEMI Networking Night.

Connect! Register here and stay in touch via Twitter at http://www.twitter.com (use #SEMICONEuropa)

A new method that precisely measures the mysterious behavior and magnetic properties of electrons flowing across the surface of quantum materials could open a path to next-generation electronics.

Found at the heart of electronic devices, silicon-based semiconductors rely on the controlled electrical current responsible for powering electronics. These semiconductors can only access the electrons’ charge for energy, but electrons do more than carry a charge. They also have intrinsic angular momentum known as spin, which is a feature of quantum materials that, while elusive, can be manipulated to enhance electronic devices.

A team of scientists, led by An-Ping Li at the Department of Energy’s Oak Ridge National Laboratory, has developed an innovative microscopy technique to detect the spin of electrons in topological insulators, a new kind of quantum material that could be used in applications such as spintronics and quantum computing.

A new microscopy method developed by an ORNL-led team has four movable probing tips, is sensitive to the spin of moving electrons and produces high-resolution results. Using this approach, they observed the spin behavior of electrons on the surface of a quantum material. Credit: Saban Hus and An-Ping Li/Oak Ridge National Laboratory, U.S. Dept. of Energy

A new microscopy method developed by an ORNL-led team has four movable probing tips, is sensitive to the spin of moving electrons and produces high-resolution results. Using this approach, they observed the spin behavior of electrons on the surface of a quantum material. Credit: Saban Hus and An-Ping Li/Oak Ridge National Laboratory, U.S. Dept. of Energy

“The spin current, namely the total angular momentum of moving electrons, is a behavior in topological insulators that could not be accounted for until a spin-sensitive method was developed,” Li said.

Electronic devices continue to evolve rapidly and require more power packed into smaller components. This prompts the need for less costly, energy-efficient alternatives to charge-based electronics. A topological insulator carries electrical current along its surface, while deeper within the bulk material, it acts as an insulator. Electrons flowing across the material’s surface exhibit uniform spin directions, unlike in a semiconductor where electrons spin in varying directions.

“Charge-based devices are less energy efficient than spin-based ones,” said Li. “For spins to be useful, we need to control both their flow and orientation.”

To detect and better understand this quirky particle behavior, the team needed a method sensitive to the spin of moving electrons. Their new microscopy approach was tested on a single crystal of Bi2Te2Se, a material containing bismuth, tellurium and selenium. It measured how much voltage was produced along the material’s surface as the flow of electrons moved between specific points while sensing the voltage for each electron’s spin.

The new method builds on a four-probe scanning tunneling microscope–an instrument that can pinpoint a material’s atomic activity with four movable probing tips–by adding a component to observe the spin behavior of electrons on the material’s surface. This approach not only includes spin sensitivity measurements. It also confines the current to a small area on the surface, which helps to keep electrons from escaping beneath the surface, providing high-resolution results.

“We successfully detected a voltage generated by the electron’s spin current,” said Li, who coauthored a paper published by Physical Review Letters that explains the method. “This work provides clear evidence of the spin current in topological insulators and opens a new avenue to study other quantum materials that could ultimately be applied in next-generation electronic devices.”

Leti, a research institute of CEA Tech, will hold a workshop on Oct. 17 to present updates on their progress developing CoolCube high-density 3D sequential, monolithic-integration technology, and their supporting design-and-manufacturing ecosystems.

The workshop at the Hyatt Regency San Francisco Airport, Burlingame, Calif., is an official satellite event of the 2017 IEEE S3S conference. It will feature presentations from Leti and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, as well as partner firms, such as Applied Materials, SCREEN Semiconductor and HP Enterprise. Workshop attendees will include representatives of a growing ecosystem of design, manufacturing, and related companies.

As an extension of High Density 3D Cu-Cu/Hybrid Bonding Chip-to-Wafer/Wafer-to-Wafer Technologies, the CoolCube  concept enables stacking active layers of transistors in the third dimension, while coping with thermal budgets that do not degrade the performance of transistors or metal interconnects. Leti and Qualcomm have been collaborating for four years on various 3DVLSI advanced concepts, which have broad applications in low-power mobile devices and other IC platforms.

Workshop topics will include:

  • a review of 3DVLSI research at Qualcomm Technologies
  • an update on Leti’s technology and design
  • a complete Leti 3D-technologies landscape presentation, and
  • exploration of expectations and challenges around 3DVLSI technology.

The workshop is designed to encourage an active exchange of ideas among attendees on applications, markets, integration and other related areas.

Leti will highlight technological solutions available now for top-tier CMOS integration using CoolCube:

  • high-quality mono-crystalline channel
  • high-performance source/drain contacts
  • high-reliability gate stack and
  • low-parasitic stable intermediate back-end-of-line on 300mm wafers.

Leti this year taped out a test vehicle based on its internal technology and CoolCube circuit and will publish final results of the test in 2018. In this CMOS integration, the technology starts from 28nm foundry wafers and extends to current Leti top-tier processes. During the Oct. 17 workshop, Leti will present the next step: a newCoolCube tape-out, scheduled for mid-2018 and open to partners and collaborators. It is targeted to demonstrate by hardware promising applications enabled by CoolCube/3DVLSI.  Design contributions are already planned or expected in the following fields: neuromorphic, near-memory processing, high-performance FPGA and energy-efficient computing.

“As CoolCube has evolved, its development team has received a growing number of inquiries from companies and organizations all along the semiconductor value chain, including materials and equipment suppliers, electronic design automation (EDA) companies, fabless chipmakers and foundries, and assembly and test houses,” said Jean-Eric Michallet, Leti Head of Microelectronics Components Department. “Mutual cooperation will be an essential element of successful integration into high-volume production, and representatives of companies in these sectors are encouraged to attend the workshop.”

 

Scientists have long searched for the next generation of materials that can catalyze a revolution in renewable energy harvesting and storage.

One candidate appears to be metal-organic frameworks. Scientists have used these very small, flexible, ultra-thin, super-porous crystalline structures to do everything from capturing and converting carbon into fuels to storing hydrogen and other gases. Their biggest drawback has been their lack of conductivity.

Now, according to USC scientists, it turns out that metal-organic frameworks can conduct electricity in the same way metals do.

This opens the door for metal organic-frameworks to one day efficiently store renewable energy at a very large, almost unthinkable scale.

The cobalt-based metal-organic framework used by the USC scientists, with purple representing cobalt, yellow representing sulfur and gray representing carbon. Credit: Smaranda Marinescu

The cobalt-based metal-organic framework used by the USC scientists, with purple representing cobalt, yellow representing sulfur and gray representing carbon. Credit: Smaranda Marinescu

“For the first time ever, we have demonstrated a metal-organic framework that exhibits conductivity like that of a metal. The natural porosity of the metal-organic framework makes it ideal for reducing the mass of material, allowing for lighter, more compact devices” said Brent Melot, assistant professor of chemistry at the USC Dornsife College of Letters, Arts & Sciences.

“Metallic conductivity in tandem with other catalytic properties would add to its potential for renewable energy production and storage” said Smaranda Marinescu, assistant professor of chemistry at the USC Dornsife College.

Their findings were published July 13 in the Journal of the American Chemical Society.

An emerging catalyst for long-term renewable energy storage

Metal-organic frameworks are so porous that they are well-suited for absorbing and storing gases like hydrogen and carbon dioxide. Their storage is highly concentrated: 1 gram of surface area provides the equivalent of thousands of square feet in storage.

Solar has not yet been maximized as an energy source. The earth receives more energy from one hour of sunlight than is consumed in one year by the entire planet, but there is currently no way to use this energy because there is no way to conserve all of it. This intermittency is intrinsic to nearly all renewable power sources, making it impossible to harvest and store energy unless, say, the sun is shining or the wind is blowing.

If scientists and industries could one day regularly reproduce the capability demonstrated by Marinescu, it would go a long way to reducing intermittency, allowing us to finally make solar energy an enduring and more permanent resource.

Metal or semiconductor: why not both?

Metal-organic frameworks are two-dimensional structures that contain cobalt, sulfur, and carbon atoms. In many ways, they very broadly resemble something like graphene, which is also a very thin layer of two-dimensional, transparent material.

As temperature goes down, metals become more conductive. Conversely, as the temperature goes up, it is semiconductors that become more conductive.

In the experiments run by Marinescu’s group, they used a cobalt-based metal-organic framework that mimicked the conductivity of both a metal and semiconductor at different temperatures. The metal-organic framework designed by the scientists demonstrated its greatest conductivity at both very low and very high temperatures.

GLOBALFOUNDRIES today unveiled AutoPro, a new platform designed to provide automotive customers a broad set of technology solutions and manufacturing services that minimize certification efforts and speed time-to-market. The company offers the industry’s broadest set of solutions for a full range of driving system applications, from informational Advanced Driver Assistance Systems (ADAS) to high-performance real-time processors for autonomous cars.

Today, the automobile semiconductor market is approximately $35 billion, and is expected to grow to an estimated $54 billion by 2023. This is driven by a need for new technologies that promise to enhance the driving experience such as navigation, remote roadside assistance and advanced systems that combine data from multiple sensors with high-performance processors that make control decisions.

“As vehicles move rapidly toward greater autonomy, auto manufacturers and parts suppliers are designing new ICs,” said Gregg Bartlett, senior vice president of the CMOS Business Unit at GF. “GF’s diverse automotive platform combines a range of technologies and services that meet the complexity and requirements for applications that enable connected intelligence for the automotive industry.”

Building on 10 years of automotive experience, the company’s AutoPro technology platform includes offerings in silicon germanium (SiGe), FD-SOI (FDX), CMOS and advanced FinFET nodes, combined with a broad range of ASIC design services, packaging and IP.

GF’s CMOS and RF solutions deliver an optimal combination of performance, integration and power efficiency for advanced sensors (radar, lidar, cameras), ADAS and autonomous processing (sensor fusion and AI compute) and body and powertrain control, with embedded eNVM technology for in-vehicle MCUs, as well as connectivity and infotainment systems. The company’s BCD and BCDLite® technologies provide high-voltage capabilities, with a path to supporting 48 volts that enable automotive power solutions for electric powertrain, Hybrid-electric (HEVs) and Internal Combustion Engine (ICE) vehicles.

These automotive solutions are available now, with additional access to quality and service across GF’s manufacturing fabs in the U.S., Europe, and Asia. GF AutoPro solutions support the full range of AEC-Q100 quality grades from Grade 2 to Grade 0.

AutoPro Service Package

In addition to GF’s technology platform, the company has initiated its AutoPro Service Package designed to ensure technology readiness, operational excellence and a robust automotive-ready quality system to continually improve quality and reliability throughout the product life-cycle.

GF’s Service Package builds on the company’s proven automotive quality and operational controls, providing customers access to the latest technologies which are designed to meet strict automotive quality requirements defined in the ISO, International Automotive Task Force (IATF), Automotive Electronics Council (AEC), and VDA (German) standards.

GF is currently working with major OEM customers and suppliers to develop and produce chips of the optimum quality and reliability as required by the various automotive applications.