Tag Archives: letter-pulse-tech

Chipmakers want every part of the wafer to produce, or yield, good die. Advances in process technologies over the years have just about made this a reality, even as feature dimensions continue to shrink and devices grow ever more complex. Now, the last frontier is improving yields at the edge of the wafer – the outer 10 mm or so – where chemical, physical, and even thermal discontinuities are simply much harder to control. Complicating matters, current strategies used to manage these edge issues involve tradeoffs between yield and manufacturing costs that result in less than ideal fab economics. At Lam, our technologists have been working on solutions to this challenge, and today, we released the new Corvus™ edge control technology for our Kiyo® conductor etch products to address these very issues and enhance edge yield.

Edge Challenges

Taking a closer look at the wafer’s edge, where up to ~10% of the die may be located, there are several issues at play that can impact yield. In all plasma etch reactors, the abrupt end of the wafer surface creates inherent electrical discontinuities at the edge region, forming voltage gradients that bend the plasma sheath. This, in turn, changes the direction of the plasma’s components (ions and neutrals), which impacts etch results and causes unwanted variability. In the case of 3D NAND devices, for example, this change in the plasma conditions at the wafer’s edge can cause tilted etch profiles or prevent features from being completely etched. In addition to affecting tilt angle, these edge effects can result in non-uniform critical dimensions (CDs) or changes in local overlay metrics.

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Another challenge is that process drift creates CD uniformity and selectivity problems over time. As a way to manage this, chipmakers often add more chamber wet cleans to restore the equipment to a standard condition. However, this approach significantly reduces productivity because the chamber is not available for processing wafers during this maintenance. In addition, as process margins get tighter, more frequent wet cleans are required, which increases operational costs.

Corvus Solution

Lam’s new Corvus technology provides a novel capability to smooth out extreme edge discontinuities and enhance edge performance. It offers the ability to tune the plasma sheath at the edge to produce a constant, user-defined etch rate and ion angle. For example, etch rate can be tuned to be faster or slower at the edge relative to the rate over the rest of the wafer. With 3D NAND applications, Corvus technology has demonstrated the ability to minimize plasma sheath drift, preventing detrimental feature tilting at the wafer’s edge. Tuning to within 1.5 mm of the edge, the new technology can correct for inherent process variation in the edge region as well as for incoming film variations to optimize die yield. Furthermore, with Corvus, every wafer sees the same edge conditions for optimal yield, eliminating previously seen systematic wafer-to-wafer yield variability.

Corvus technology not only improves across-wafer uniformity, it also greatly reduces wafer-to-wafer and chamber-to-chamber variability and eliminates the historical tradeoffs among yield, operational flexibility, and cost. Customers have reported die yield improvements of 0.5-2% per wafer, which can be a significant advantage – especially when you consider how many thousands of wafers chipmakers process every day. Additionally, Corvus has demonstrated the ability to provide higher and more consistent yield over a longer period. It also greatly enhances productivity and lowers overall fab operating costs for high-volume manufacturing by requiring fewer chamber wet cleans. The new technology is being used for advanced patterning, mask open, and other challenging conductor etch applications where reducing variation in CD, profile, or selectivity and improving productivity helps enable continued scaling.

The new capability provided by Corvus complements Lam’s Hydra® technology, which enables fine tuning of within-wafer uniformity and actively compensates for incoming variation. Together, these advanced process control technologies are reducing variability across the entire wafer surface, improving yield, and enabling the production of next-generation logic and memory devices.

Welch Foundation, the Army Research Office and the National Science Foundation supported the research.

The Rice laboratory of materials scientist Jun Lou has made a semiconducting transition-metal dichalcogenide (TMD) that starts as a monolayer of molybdenum diselenide. They then strip the top layer of the lattice and replace precisely half the selenium atoms with sulfur.

The new material they call Janus sulfur molybdenum selenium (SMoSe) has a crystalline construction the researchers said can host an intrinsic electric field and that also shows promise for catalytic production of hydrogen.

The work is detailed this month in the American Chemical Society journal ACS Nano.

The two-faced material is technically two-dimensional, but like molybdenum diselenide it consists of three stacked layers of atoms arranged in a grid. From the top, they look like hexagonal rings a la graphene, but from any other angle, the grid is more like a nanoscale jungle gym.

Tight control of the conditions in a typical chemical vapor deposition furnace — 800 degrees Celsius (1,872 degrees Fahrenheit) at atmospheric pressure — allowed the sulfur to interact with only the top layer of selenium atoms and leave the bottom untouched, the researchers said. If the temperature drifts above 850, all the selenium is replaced.

“Like the intercalation of many other molecules demonstrated to have the ability to diffuse into the layered materials, diffusion of gaseous sulfur molecules in between the layers of these Van der Waals crystals, as well as the space between them and the substrates, requires sufficient driving force,” said Rice postdoctoral researcher Jing Zhang, co-lead author of the paper with graduate student Shuai Jia. “And the driving force in our experiments is controlled by the reaction temperature.”

Close examination showed the presence of sulfur gave the material a larger band gap than molybdenum diselenide, the researchers said.

“This type of two-faced structure has long been predicted theoretically but very rarely realized in the 2-D research community,” Lou said. “The break of symmetry in the out-of-plane direction of 2-D TMDs could lead to many applications, such as a basal-plane active 2-D catalyst, robust piezoelectricity-enabled sensors and actuators at the 2-D limit.”

He said preparation of the Janus material should be universal to layered materials with similar structures. “It will be quite interesting to look at the properties of the Janus configuration of other 2-D materials,” Lou said.

 

Rechargeable batteries are essential for powering our personal electronic devices. To meet the novel functions of next-generation electronics, including foldable displays, flexible power sources are needed. However, conventional batteries are rigid and unable to adapt to the demands of flexible devices. Low-cost, rechargeable batteries containing naturally abundant elements, such as zinc, are appealing, but flexible batteries based on zinc require a different preparation method from conventional batteries.

In their article in Advanced Energy Materials, Xu Chen, Bin Liu, Cheng Zhong, and co-workers have developed a high-performance, flexible air electrode for the Zn–air battery by devising a simple fabrication technique.

The technique involves electrodeposition with fast heat treatment to grow ultrathin mesoporous Co3O4 layers on the surface of carbon fibers on a carbon cloth. These ultrathin Co3O4 layers have a maximum contact area on the conductive support, facilitating rapid electron transport and preventing the aggregation of the layers.

Benefiting from the high utilization degree of active materials and rapid charge transport, the mass activity for oxygen reduction and evolution reactions of the ultrathin electrode is more than 10 times higher than that of the carbon cloth loaded with commercial Co3O4 nanoparticles. The as-assembled flexible Zn–air battery based on the ultrathin electrode exhibits excellent rechargeability (≈1.03 V discharge voltage and ≈1.95 V charge voltage at 2 mA cm–2), with a high charge density of 546 Wh kg–1. It also has a high cycling stability, where no obvious loss occurred after 10 hours of galvanostatic discharge–charge testing or after 300 mechanical bending cycles.

The authors also integrated a flexible display into the device. Despite repeated bending and twisting, the device maintains its mechanical integrity and discharge performance. When the device is cut by scissors, there is no perceptible change in the display brightness, signaling safe and reliable operation if the device is damaged.

To find out more about this flexible battery, please visit the Advanced Energy Materials homepage.

Everspin Technologies, Inc. has begun sampling its new 1-Gigabit Spin Torque Magnetoresistive Random Access Memory (ST-MRAM) with lead customers. This product delivers a high-endurance, persistent memory with a DDR4-compatible interface. These features enable storage system vendors to enhance the reliability and performance of storage devices and systems by delivering protection against power loss without the use of supercapacitors or batteries. Enterprise SSD designers can take advantage of fast persistent memory that is inherently power fail-safe while also reducing write amplification and overprovisioning, common limitations for NAND Flash based SSDs.

The 1 Gb MRAM is produced in 28nm CMOS on 300mm wafers in partnership with GLOBALFOUNDRIES, utilizing Everspin’s patented perpendicular magnetic tunnel junction (pMTJ) technology. The rapid development of the 1Gb part is a direct result of the high degree of scalability of the pMTJ, moving from 40nm to 28nm processes in less than one year through our close partnership with Global Foundries.

“We are very excited to begin sampling our 1 Gb product,” said Phill LoPresti, Everspin’s President and CEO. “Getting our latest technology into customers’ hands so they can develop their products to take advantage of the unique capabilities of high-endurance, fast, persistent memory is a significant milestone for Everspin.”

Everspin will be demonstrating the EMD4E001G at the upcoming Flash Memory Summit in Santa Clara on August 7-10. This latest ST-MRAM product provides 4 times the capacity of Everspin’s current 256Mb DDR3 ST-MRAM and will be shown running in Everspin’s nvNITRO storage accelerator products.

 

Characterizing the thermal properties of crystalline molybdenum disulfide, an important two-dimensional (2D) material, has proven challenging. Now researchers from A*STAR have developed a simple technique that could pave the way for its use in a wide range of new applications in energy storage, optoelectronic and flexible electronic devices (Physical Review B, “Direct calculation of the linear thermal expansion coefficients of MoS2 via symmetry-preserving deformations”).

Hexagonal molybdenum disulfide (MoS2), one of the dichalcogenides — a family of semiconducting transitional metals — has attracted considerable attention as a two-dimensional (2D) material thanks to its remarkable electronic and optoelectronic properties. It is also notable for its impressive strength and flexibility, which arise from the hexagonal lattice of molybdenum atoms sandwiched between layers of sulfur atoms.

Determining the thermal characteristics of MoS2 is key to unlocking its astonishing properties, but its complex geometry and the many required calculations for phonons — the different vibrational modes of atoms in a crystal lattice — are a costly and time-consuming computational process.

Chee Kwan Gan and Yu Yang Fredrik Liu from the A*STAR Institute of High Performance Computing have now developed a numerical technique that dramatically reduces the number of calculations, allowing the thermal expansion coefficient — which determine how their shape and size change in response to changes in temperature — of MoS2 crystals to be accurately and efficiently calculated, and could also be applied to other important 2D materials.

“Think of a phonon as a particle tied to a spring, where it vibrates with a fixed pattern at a fixed frequency,” explains Gan. “There are many phonon modes in a crystal like molybdenum disulfide, and the challenge is to calculate all of them.”

By deforming a crystal of MoS2, the researchers determined the change in frequency for each phonon in the lattice structure, and by applying a numerical method, based on perturbation theory, to these altered frequencies; they were able to estimate the crystal’s thermal characteristics, known as the Grüneisen parameters. These parameters were then used to calculate the thermal expansion coefficients for hexagonal MoS2.

“Our method uses the full symmetry of the hexagonal structure to reduce the amount of computation to only four sets of phonon calculations compared with quasi-harmonic approximation — the traditional approach — that requires many more,” says Gan.

The work presents, for the first time, an accurate and simple method for determining the thermal properties of MoS2, and provides a deeper understanding of thermal conduction in 2D materials.

“Our long-term aim is to extend the approach to other technologically important semiconducting, two-dimensional materials, such as bismuth selenide,” says Gan.

Standard light-emitting diodes (LEDs) used for home lighting can now transmit data more rapidly between electronic devices, thanks to new research from A*STAR.

Wireless visible light communication—also known as Li-Fi—relies on data signals encoded in incredibly brief pulses of light, far too quick for the eye to see. By supplementing congested Wi-Fi networks, Li-Fi could increase the capacity and speed of data transmission in offices, homes and public spaces. However, white LEDs typically use a phosphor coating to create a natural-looking white light, and the time it takes for the phosphor’s glow to fade away limits how quickly the LED can transmit data.

Previous solutions typically required installing new types of white LEDs. Instead, Ee Jin Teo of the A*STAR Institute of Materials Research and Engineering, and colleagues, have developed a Li-Fi receiver that overcomes these problems. Rather than using a conventional silicon photodiode to detect transmissions, they found that an indium gallium nitride (InGaN) LED is an effective data receiver.

Crucially, the team’s InGaN LEDs can detect only the ‘fast’ blue component of the phosphor’s white light, which fades in only one nanosecond, and not the ‘slow’ yellow component which takes more than 50 nanoseconds to fade away.

The researchers also gave their InGaN LED a textured surface, so that every square centimeter was covered with one billion V-shaped pits (see image), roughly 150 nanometers deep. These V-pits scatter incoming light, allowing the LED’s active layers to absorb more than twice as much blue light as an LED with a smooth surface.

Tests with a white LED showed that the InGaN LED with V-pits was a much better receiver than a standard silicon photodetector. “Using a silicon photodetector, the white LED can reach a switching speed of five megahertz—this typically means a data transmission rate of up to 100 megabits per second,” says Teo. “With our InGaN LED as a detector, this switching speed can be increased by four times, enabling faster data transmission rates from white LEDs.”

She notes, however, that since the receiver is only picking up part of the white LED’s light, it may reduce the range over which data can be transmitted.

“The next stage of our research,” she adds, “is to implement this concept into a dongle where the same LED can be used for transmission as well as detection of data.”

A future android brain like that of Star Trek’s Commander Data might contain neuristors, multi-circuit components that emulate the firings of human neurons.

Neuristors already exist today in labs, in small quantities, and to fuel the quest to boost neuristors’ power and numbers for practical use in brain-like computing, the U.S. Department of Defense has awarded a $7.1 million grant to a research team led by the Georgia Institute of Technology. The researchers will mainly expand work on new metal oxide materials that buzz electronically at the nanoscale to emulate the way human neural networks buzz with electric potential on a cellular level.

But let’s walk expectations back from the distant sci-fi future into the scientific present: The research team has developed neuristor materials to build, for now, an intelligent light sensor, and not some artificial version of the human brain, which would require hundreds of trillions of circuits.

“We’re not going to reach circuit complexities of that magnitude, not even a tenth,” said Alan Doolittle, a professor at Georgia Tech’s School of Electrical and Computer Engineering. “Also, currently science doesn’t really know yet very well how the human brain works, so we can’t duplicate it.”

Intelligent retina

But an artificial retina that can learn autonomously appears well within reach of the research team from Georgia Tech and Binghamton University. Despite the term “retina,” the development is not intended as a medical implant, but it could be used in advanced image recognition cameras for national defense and police work.

At the same time, it significantly advances brain-mimicking, or neuromorphic, computing. The research field that takes its cues from what science already does know about how the brain computes to develop exponentially more powerful computing.

The retina is comprised of an array of ultra-compact circuits called neuristors (a word combining “neuron” and “transistor”) that sense light, compute an image out of it and store the image. All three of the functions would occur simultaneously and nearly instantaneously.

“The same device senses, computes and stores the image,” Doolittle said. “The device is the sensor, and it’s the processor, and it’s the memory all at the same time.” A neuristor itself is comprised in part of devices called memristors inspired by the way human neurons work.

Brain vs. PC

That cuts out loads of processing and memory lag time that are inherent in traditional computing.

Take the device you’re reading this article on: Its microprocessor has to tap a separate memory component to get data, then do some processing, tap memory again for more data, process some more, etc. “That back-and-forth from memory to microprocessor has created a bottleneck,” Doolittle said.

A neuristor array breaks the bottleneck by emulating the extreme flexibility of biological nervous systems: When a brain computes, it uses a broad set of neural pathways that flash with enormous data. Then, later, to compute the same thing again, it will use quite different neural paths.

Traditional computer pathways, by contrast, are hardwired. For example, look at a present-day processor and you’ll see lines etched into it. Those are pathways that computational signals are limited to.

The new memristor materials at the heart of the neuristor are not etched, and signals flow through the surface very freely, more like they do through the brain, exponentially increasing the number of possible pathways computation can take. That helps the new intelligent retina compute powerfully and swiftly.

Terrorists, missing children

The retina’s memory could also store thousands of photos, allowing it to immediately match up what it sees with the saved images. The retina could pinpoint known terror suspects in a crowd, find missing children, or identify enemy aircraft virtually instantaneously, without having to trawl databases to correctly identify what is in the images.

Even if you take away the optics, the new neuristor arrays still advance artificial intelligence. Instead of light, a surface of neuristors could absorb massive data streams at once, compute them, store them, and compare them to patterns of other data, immediately. It could even autonomously learn to extrapolate further information, like calculating the third dimension out of data from two dimensions.

“It will work with anything that has a repetitive pattern like radar signatures, for example,” Doolittle said. “Right now, that’s too challenging to compute, because radar information is flying out at such a high data rate that no computer can even think about keeping up.”

Smart materials

The research project’s title acronym CEREBRAL may hint at distant dreams of an artificial brain, but what it stands for spells out the present goal in neuromorphic computing: Cross-disciplinary Electronic-ionic Research Enabling Biologically Realistic Autonomous Learning.

The intelligent retina’s neuristors are based on novel metal oxide nanotechnology materials, unique to Georgia Tech. They allow computing signals to flow flexibly across pathways that are electronic, which is customary in computing, and at the same time make use of ion motion, which is more commonly know from the way batteries and biological systems work.

The new materials have already been created, and they work, but the researchers don’t yet fully understand why.

Much of the project is dedicated to examining quantum states in the materials and how those states help create useful electronic-ionic properties. Researchers will view them by bombarding the metal oxides with extremely bright x-ray photons at the recently constructed National Synchrotron Light Source II.

Grant sub-awardee Binghamton University is located close by, and Binghamton physicists will run experiments and hone them via theoretical modeling.

‘Sea of lithium’

The neuristors are created mainly by the way the metal oxide materials are grown in the lab, which has some advantages over building neuristors in a more wired way.

This materials-growing approach to creating part of the computational structure is conducive to mass production. Also, though neuristors in general free signals to take multiple pathways, Georgia Tech’s neuristors do it much more flexibly thanks to chemical properties.

“We also have a sea of lithium, and it’s like an infinite reservoir of computational ionic fluid,” Doolittle said. The lithium niobite imitates the way ionic fluid bathes biological neurons and allows them to flash with electric potential while signaling. In a neuristor array, the lithium niobite helps computational signaling move in myriad directions.

“It’s not like the typical semiconductor material, where you etch a line, and only that line has the computational material,” Doolittle said.

Commander Data’s brain?

“Unlike any other previous neuristors, our neuristors will adapt themselves in their computational-electronic pulsing on the fly, which makes them more like a neurological system,” Doolittle said. “They mimic biology in that we have ion drift across the material to create the memristors (the memory part of neuristors).”

Brains are far superior to computers at most things, but not all. Brains recognize objects and do motor tasks much better. But computers are much better at arithmetic and data processing.

Neuristor arrays can meld both types of computing, making them biological and algorithmic at once, a bit like Commander Data’s brain.

Rice University researchers have learned to manipulate two-dimensional materials to design in defects that enhance the materials’ properties.

The Rice lab of theoretical physicist Boris Yakobson and colleagues at Oak Ridge National Laboratory are combining theory and experimentation to prove it’s possible to give 2-D materials specific defects, especially atomic-scale seams called grain boundaries. These boundaries may be used to enhance the materials’ electronic, magnetic, mechanical, catalytic and optical properties.

The key is introducing curvature to the landscape that constrains the way defects propagate. The researchers call this “tilt grain boundary topology,” and they achieve it by growing their materials onto a topographically curved substrate — in this case, a cone. The angle of the cone dictates if, what kind and where the boundaries appear.

The research is the subject of a paper in the American Chemical Society journal ACS Nano.

Grain boundaries are the borders that appear in a material where edges meet in a mismatch. These boundaries are a series of defects; for example, when two sheets of hexagonal graphene meet at an angle, the carbon atoms compensate for it by forming nonhexagonal (five- or seven-member) rings.

Yakobson and his team have already demonstrated that these boundaries can be electronically significant. They can, for instance, turn perfectly conducting graphene into a semiconductor. In some cases, the boundary itself may be a conductive subnanoscale wire or take on magnetic properties.

But until now researchers had little control over where those boundaries would appear when growing graphene, molybdenum disulfide or other 2-D materials by chemical vapor deposition.

The theory developed at Rice showed growing 2-D material on a cone would force the boundaries to appear in certain places. The width of the cone controlled the placement and, more importantly, the tilt angle, a crucial parameter in tuning the materials’ electronic and magnetic properties, Yakobson said.

Experimental collaborators from Oak Ridge led by co-author David Geohegan provided evidence backing key aspects of the theory. They achieved this by growing tungsten disulfide onto small cones similar to those in Rice’s computer models. The boundaries that appeared in the real materials matched those predicted by theory.

“The nonplanar shape of the substrate forces the 2-D crystal to grow in a curved ‘non-Euclidian’ space,” Yakobson said. “This strains the crystal, which occasionally yields by giving a way to the seams, or grain boundaries. It’s no different from the way a tailor would add a seam to a suit or a dress to fit a curvy customer.”

Modeling cones of different widths also revealed a “magic cone” of 38.9 degrees upon which growing a 2-D material would leave no grain boundary at all.

The Rice team extended its theory to see what would happen if the cones sat on a plane. They predicted how grain boundaries would form over the entire surface, and again, Oak Ridge experiments confirmed their results.

Yakobson said both the Rice and Oak Ridge teams were working on aspects of the research independently. “It was slow going until we met at a conference in Florida a couple of years back and realized that we should continue together,” he said. “It was certainly gratifying to see how experiments confirmed the models, while sometimes offering important surprises. Now we need to do the additional work to comprehend them as well.”

GLOBALFOUNDRIES today announced that it has demonstrated silicon functionality of a 2.5D packaging solution for its high-performance 14nm FinFET FX-14 integrated design system for application-specific integrated circuits (ASICs).

The 2.5D ASIC solution includes a stitched interposer capability to overcome lithography limitations and a two terabits per second (2Tbps) multi-lane HBM2 PHY, developed in partnership with Rambus, Inc. Building on the 14nm FinFET demonstration, the solution will be integrated on the company’s next-generation FX-7 ASIC design system built on GF’s 7nm FinFET process technology.

“With the tremendous advances in interconnect and packaging technology that has occurred in recent years, the line between wafer processing and packaging has blurred,” said Kevin O’Buckley, vice president of ASIC product development at GF. “Incorporating 2.5D packaging into ASIC design boosts performance beyond scaling and is a natural evolution of our capabilities. It enables us to support our customers in a one-stop end-to-end fashion, from product design all the way through manufacturing and testing.”

The Rambus memory PHY is aimed at high-end networking and data center applications performing the most data-intensive tasks in systems requiring low-latency and high-bandwidth. The PHY is compliant with the JEDEC JESD235 HBM2 standard, supporting data rates up to 2Gbps per data pin, enabling a total bandwidth of 2Tbps.

“We strive to deliver comprehensive HBM PHY technologies that will enable data center and networking solution providers to meet today’s most demanding workloads and take advantage of compelling market opportunities,” said Luc Seraphin, senior vice president and general manager, Memory and Interfaces Division at Rambus. “Our collaboration with GF combines our HBM2 PHY with their 2.5D packaging and FX-14 ASIC design system and provides a fully-integrated solution for the industry’s fastest-growing applications.”

FX-14 and FX-7 are complete ASIC design solutions that take advantage of GF’s experience in volume production with FinFET process technology. They comprise functional modules based on the industry’s broadest and deepest intellectual property (IP) portfolio, which makes possible unique solutions for next-generation wired/5G wireless networking, cloud/data center servers, machine learning/deep neural networks, automotive, and aerospace/defense applications. GF is one of only two companies in the world that delivers best-in-class IP plus advanced memory and packaging solutions.

IntelliProp, Inc., a developer of Intellectual Property (IP) Cores and semiconductors for Data Storage and Memory applications, announced today the IPA-PM185-CT, Gen-Z Persistent Memory Controller, code named “Cobra.” This controller combines DRAM and NAND and sits on the Gen-Z fabric, not the memory bus. Cobra has the ability to support byte addressability to DRAM cache and Block addressability to NAND flash supporting up to 32GB of DRAM and 6TB of NAND. IntelliProp is a member of the Gen-Z consortium and is working closely with a number of other companies to support the first multi-company Gen-Z demo, being shown this week at Flash Memory Summit.

IntelliProp is exhibiting at Flash Memory Summit, being held at the Santa Clara Convention Center, August 8-10, 2017. IntelliProp is in booth #821. The Gen-Z “Cobra” Controller along with other IP & ASSP demos will be shown at IntelliProp’s booth. The Gen-Z Cobra controller will also be showcased in the Gen-Z Consortium demo in booth #739.

IntelliProp is also showing the NVMe Host Accelerator IP Core, the IPC-NV164-HI. This Core will find primary application with companies doing FPGA and ASIC designs who need high performance connectivity with PCIe based NVMe storage devices. Compliant with the NVMe 1.3 specification, the NVMe Host Accelerator IP Core provides a simple firmware or RTL driven interface for data movement to and from an NVMe endpoint attached to a PCIe link. “We manage the command and completion queues in hardware to accelerate performance by off-loading the processor from needing to handle numerous interrupts,” said Hiren Patel, VP of Business Development at IntelliProp. “The NVMe Host Accelerator IP Core is shipping today for all Xilinx and Altera FPGAs including the latest Ultrascale Plus and Arria 10 FPGAs.  And for those customers that want acceleration with Linux, IntelliProp has also written a Linux driver to work with the NVMe Host Accelerator IP Core,” continued Mr. Patel.

IntelliProp is excited to also announce the availability of additional NVMe products for the storage market.   IntelliProp has released the IPC-NV171A-BR, NVMe-to-NVMe Bridge and the IPP-NV186A-BR, NVMe-to-SATA Bridge. “The NVMe-to-NVMe bridge allows customers to manipulate data or commands from a PCIe root-complex such as a PC to an NVMe drive. The NVMe-to-SATA bridge allows customers to use SATA drives which will enumerate as NVMe drives in the host system,” said Hiren Patel.