Tag Archives: letter-pulse-tech

By Paul Trio

SCIS is a SEMI Technology Community that tackles critical component defectivity for the semiconductor manufacturing industry. The organization develops test methods for measuring defects in these critical components. Originally, this SEMI community was looking at challenges surrounding sub-10nm process nodes, but our constituents – Integrated Device Manufacturers (IDMs), capital equipment OEMs, and (sub)component suppliers – felt that the immediate need was for standards that would apply to process nodes that are already being used for volume semiconductor device manufacturing.

IDMs need ways to tell their supply chain how defects attributable to these critical components factor into the overall process-node defect budgets and wafer-contamination limits. Chipmakers and IDMs needed to start with a baseline: How problematic are existing critical components in the overall fab systems and how do these contaminants contribute to defects and how do they affect overall process yields?

These questions must be answered for every component in the fab’s process line including the drums that hold the fab chemistries, fluid delivery systems, and components used in the wafer-processing chamber. All of these critical fab-line components come into contact with each manufactured wafer, in one way or another, and each is a suspect with respect to contamination, defects, and yield problems. SCIS develops test methods for these fab-line critical components testing that are used to identify the defects caused by these components and for establishing baselines.

SCIS has seven working groups dealing with various critical components. Each is developing various test methods for many critical fab-line components. There are many facets with respect to testing each of these critical components.

Take something as simple as a seal, such as an FFKM (perfluoroelastomer, made from polymers) seal. These seals are ubiquitous in fab lines. In harsher environments, such as inside of a processing chamber, these seals are exposed to high temperatures and harsh chemistries. Different FFKM seals will have different characteristics such as thermal resistivity and chemical resistance, depending on customer specifications, and can also vary from one manufacturer to another. In addition, these characteristics can change depending on environmental conditions – or just the passage of time.

SCIS looks at defect traits from the perspective of each component in the fab line and decides which of the components’ parameters contribute most to process defects. Initially, the SCIS Seals & Valves Group collected a list of seal-related issues or parameters. The working group then cross-checked these parameters against different manufacturing processes used in the fab including ALD (atomic layer deposition) and CVD (chemical vapor deposition). Some processes are harder on seals than others. Then the working group prioritized these various parameters according to their contribution to the overall process defect budget. IDMs provided important input during these steps because they work with these seals on a daily basis. At this point, the SCIS working group had a prioritized list of parameters, vetted by various stakeholders in the semiconductor manufacturing industry. The group then set to develop standardized measurement methods for these critical parameters.

Based on this work, the SCIS Seals & Valves Group has already published two documents. The first is a standard that specifies methods for testing seal-induced impurities such as ashing (analysis of metals content of the ash) and TOC (total organic content).

The second document published by the Seals & Valves Group is a guide that documents BKMs (best known methods) for handling seals – from the moment they’re cured in an oven to packaging, shipping, handling in a fab, and installation – a to reduce contamination problems during use. For example, some seals are sensitive to light. Some polymer seals degrade when they come into contact with IPA (isopropyl alcohol), which is often used for prepping. A degraded seal can emit contamination particles during processing, which will cause yields to fall. (This latter bit of information came directly from a major IDM, which demonstrates the invaluable role that users of these components can play in the development of testing standards.)

The Seals & Valves Group’s current work focuses on developing a standard for measuring seal leak rates. This standard will define test methods for evaluating a seal’s ability to maintain pressure under vacuum. Although there are well-established standard for testing seal CSR (compressive stress relaxation) in the aerospace industry, there’s no such standard for the semiconductor industry. So originally, the Seals & Valves Group tried to tackle that challenge by developing a similar standard for SEMI’s constituents. However, a more practical and immediate parametric challenge turned out to be seal leakage rates.

Installed seals are exposed to high temperatures and harsh chemistries in the semiconductor fabrication process. The Seals & Valves Group decided to develop a test method that would determine how well seals perform over time with respect to leakage rates as the seals are exposed to cyclic harsh conditions. The goal is to simulate the working conditions for these seals, as closely as possible and in a repeatable manner.

There are, of course, some challenges associated with this work. For example, IDMs and equipment OEMs don’t want to reveal their exact process conditions as they are proprietary. So the Seals & Valves Group took a step back and focused on developing a test method based solely on exposure to elevated temperatures.

Development of this thermal test requires the design of a standardized test jig to help ensure consistent, repeatable tests, shown in Figure 1.

Figure 1: Elastomer seal test jig developed by the SCIS Seals & Valves Group.

The seal under test, shown in red in Figure 1, sits at the center of the jig. A second seal, shown in green, is used to seal the actual test environment. Two thermocouples in the jig’s top and bottom monitor of the temperature inside of the jig. There are gas and purge lines for controlling the ambient pressures on either side of the seal under test.

Figure 2 illustrates how the jig is connected to the gas sources.

Figure 2: The Seals Test Jig is connected to helium and nitrogen gas sources and to a calibrated leak (vacuum) line.

The seals leak test is based on a helium leak test. Helium is one of the smallest atoms so it will leak through just about any small gap and, with time, permeate through the material as well. In addition, helium is inert, and testing for helium using a mass spectrometer is a well-established technique for leak testing. Helium leak testing can be one thousand to one million times more sensitive than using mechanical, pressure-decay test techniques. The jig’s nitrogen lines serve to purge the test chambers of helium between leak tests.

Developing just a test jig is not sufficient. The Seals & Valves Group also developed a test sequence for using the jig. There were no existing standard, so the group needed to use its knowledge of the seals’ composition and operating conditions to develop certain test parameters. For example, the group elected to use 200°C as the maximum temperature for the high-temperature portion of the test because FFKM seals start to degrade at 250°C.

At this point, the Seals & Valves Group has gone through several iterations of a proposed test sequence. There was some initial reluctance to provide detailed inputs, but after a few iterations of the proposed method (and an understanding that this would become an industry standard to hold suppliers accountable), inputs have become more forthcoming.

This is an excellent example that demonstrates why it’s so important for SCIS working groups to get chipmakers, IDMs, component vendors, and even feedstock materials vendors to participate in these standardization efforts. Standards are far more useful if they’re based on real-world conditions.

Currently, the SCIS Seals & Valves Group is working towards finalizing the seals-leak test sequence. The jig has been designed in AutoCAD and a prototype will soon be manufactured. Although the test and jig have been developed with significant industry participation, the validity of the test has yet to be determined. The validity will be verified though Alpha testing before the jig design and test method are incorporated into a standard.

However, SEMI is not a test house. It’s a facilitator. The testing will therefore be performed by a neutral third party capable of carrying out the test under fab-like conditions. SEMI’s role is to work with different testing entities such as SUNY Polytechnic Institute in Utica, New York or IMEC in Belgium.

SEMI will solicit bids for this work through its SCIS Executive Advisory Committee, which consists of C-level executives from device makers, semiconductor capital equipment OEMs, and major critical component suppliers. This project has leveraged many of the relationships that SEMI has developed over the years and has broken new ground in standards making for SCIS and for SEMI.

For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

SEMI and imec are joining forces to drive innovation and deepen industry alignment on technology roadmaps and international standards while adding technology depth to SEMI’s five vertical application platforms including Smart Transportation, Smart MedTech and Smart Data.

Under a Memorandum of Understanding announced today at ISS 2019, the two organizations have set their sights on bringing together key industry players to advance cutting-edge technologies including Internet of Things (IoT), artificial intelligence (AI) and machine learning that enable new capabilities across healthcare, automotive and semiconductor manufacturing. The partnership also aims to speed the time to better business results for SEMI and imec members and partners.

SEMI brings to the partnership access to the $2 trillion global electronics manufacturing supply chain and imec its global research and development (R&D) and innovation leadership in nanoelectronics and digital technologies.

Under the MOU, the two organizations will co-produce SEMI Think Tanks, extend SEMI’s International Standards platform to non-CMOS technologies, identify and fill gaps in technology roadmaps, and tighten imec’s engagement with SEMI in European workforce development efforts.

Samsung Electronics Co., Ltd. today introduced its latest innovations in modular MicroLED display technology during its annual First Look CES event at the Aria Resort & Casino in Las Vegas. The revolutionary new MicroLED technology designs featured at the event included: a new 75” display, a 219” The Wall as well as other various groundbreaking sizes, shapes and configurations for a next-generation modular MicroLED display – a 2019 CES Best of Innovation Award winner.

“For decades, Samsung has led the way in next-generation display innovation,” said Jonghee Han, President of Visual Display Business at Samsung Electronics. “Our MicroLED technology is at the forefront of the next screen revolution with intelligent, customizable displays that excel in every performance category. Samsung MicroLED has no boundaries, only endless possibilities.”

Featuring self-emissive technology and modular capabilities, Samsung’s MicroLED displays deliver unparalleled picture quality, versatility and design. These transformative TV displays are made up of individual modules of self-emissive MicroLEDs, featuring millions of inorganic red, green and blue microscopic LED chips that emit their own light to produce brilliant colors on screen – delivering unmatched picture quality that surpasses any display technology currently available on the market.

At last year’s CES, Samsung introduced MicroLED by unveiling The Wall, the critically acclaimed, award-winning 146” MicroLED display. Due to the technical advancements in the ultra-fine pitch semiconductor packaging process that narrow the gap between the microscopic LED chips, Samsung has been able to create a stunning 4K MicroLED display in a smaller, more home-friendly 75” form factor.

Thanks to the modular nature of MicroLED, this technology offers flexibility in screen size that allows users to customize it to fit any room or space. By adding MicroLED modules, users can expand their display to any size they desire. The modular functionality of MicroLED will allow users in the future to create the ultimate display even at irregular 9×3, 1×7 or 5×1 screen sizes that suits their spatial, aesthetic and functional needs.

Samsung’s MicroLED technology also optimizes the content no matter the size and shape of the screen. Even when adding more modules, Samsung MicroLED displays can scale to increase the resolution — all while keeping the pixel density constant. Additionally, MicroLED can support everything from the standard 16:9 content, to 21:9 widescreen films, to unconventional aspect ratios like 32:9, or even 1:1 – without having to make any compromises in its picture quality.

Finally, because MicroLED displays are bezel-free, there are no borders between modules – even when you add more. The result is a seamless, stunning infinity pool effect that allows the display to elegantly blend into any living environment. The possibilities for eye-catching designs are enhanced by new Ambient Mode features.

For more detail on Samsung’s 2019 QLED 8K and MicroLED lines, please visit booth #15006 in the Central Hall of the Las Vegas Convention Center during CES 2019 (January 8-11, 2019).

UNSW researchers at the Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) have shown for the first time that they can build atomic precision qubits in a 3D device – another major step towards a universal quantum computer.

The team of researchers, led by 2018 Australian of the Year and Director of CQC2T Professor Michelle Simmons, have demonstrated that they can extend their atomic qubit fabrication technique to multiple layers of a silicon crystal – achieving a critical component of the 3D chip architecture that they introduced to the world in 2015. This new research was published today in Nature Nanotechnology.

The group is the first to demonstrate the feasibility of an architecture that uses atomic-scale qubits aligned to control lines – which are essentially very narrow wires – inside a 3D design.

What’s more, the team was able to align the different layers in their 3D device with nanometer precision – and showed they could read out qubit states single shot, i.e. within one single measurement, with very high fidelity.

“This 3D device architecture is a significant advancement for atomic qubits in silicon,” says Professor Simmons. “To be able to constantly correct for errors in quantum calculations – an important milestone in our field – you have to be able to control many qubits in parallel.

“The only way to do this is to use a 3D architecture, so in 2015 we developed and patented a vertical crisscross architecture. However, there were still a series of challenges related to the fabrication of this multi-layered device. With this result we have now shown that engineering our approach in 3D is possible in the way we envisioned it a few years ago.”

In this paper, the team has demonstrated how to build a second control plane or layer on top of the first layer of qubits.

“It’s a highly complicated process, but in very simple terms, we built the first plane, and then optimized a technique to grow the second layer without impacting the structures in first layer,” explains CQC2T researcher and co-author, Dr Joris Keizer.

“In the past, critics would say that that’s not possible because the surface of the second layer gets very rough, and you wouldn’t be able to use our precision technique anymore – however, in this paper, we have shown that we can do it, contrary to expectations.”

The team also demonstrated that they can then align these multiple layers with nanometer precision.

“If you write something on the first silicon layer and then put a silicon layer on top, you still need to identify your location to align components on both layers. We have shown a technique that can achieve alignment within under 5 nanometers, which is quite extraordinary,” Dr Keizer says.

Lastly, the researchers were able to measure the qubit output of the 3D device with what’s called single shot – i.e. with one single, accurate measurement, rather than having to rely on averaging out millions of experiments. “This will further help us scale up faster,” Dr Keizer explains.

Towards commercialisation

Professor Simmons says that this research is a major milestone in the field.

“We are working systematically towards a large-scale architecture that will lead us to the eventual commercialisation of the technology.

“This is an important development in the field of quantum computing, but it’s also quite exciting for SQC,” says Professor Simmons, who is also the founder and a director of SQC.

Since May 2017, Australia’s first quantum computing company, Silicon Quantum Computing Pty Limited (SQC), has been working to create and commercialise a quantum computer based on a suite of intellectual property developed at CQC2T and its own proprietary intellectual property.

“While we are still at least a decade away from a large-scale quantum computer, the work of CQC2T remains at the forefront of innovation in this space. Concrete results such as these reaffirm our strong position internationally,” she concludes.

MagnaChip Semiconductor Corporation (“MagnaChip” or the “Company”) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor products, announced today it now offers foundry customers its third generation 0.18 micron Bipolar-CMOS-DMOS (BCD) process technology. The technology is highly suitable for PMIC, DC-DC converters, battery charger ICs, protection ICs, motor driver ICs, LED driver ICs and audio amplifiers. The third generation 0.18 micron BCD process technology offers improved specific on-resistance (Rsp) of power LDMOS (Laterally Diffused Metal Oxide Semiconductor) that operates up to 40V with simplified manufacturing steps.

Demand is increasing for high-performance and power-efficient Power ICs processed in BCD technology in order to reduce the number of components in power modules by having multiple functions in one chip. In BCD technologies, the Rsp characteristics of power LDMOS is a key performance parameter because BCD technology with lower Rsp LDMOS helps reduce chip size and power loss of power ICs. MagnaChip has been improving the Rsp of power LDMOS for last ten years. Now, by process and device architecture optimization, MagnaChip’s third generation 0.18 micron BCD process technology reduces the Rsp by approximately 30%, as compared to the previous generation.

BCD technology requirements vary for different applications and IC design schemes. To cover various requirements, MagnaChip adopted the modular process concept that can generate diverse combinations of 1.8V, 5V, and 12~40V transistors. In addition to the current device combinations, MagnaChip intends to release new devices in 2019, such as:  tailored LDMOS devices optimized for a specific range of operational voltages and LDMOS devices with low Vgs (bias between gate to source) that are suitable for power ICs with strict operational voltage limits and other operating at high frequencies.

The third generation BCD process technology offers various optional devices to enhance design integration and flexibility. The optional devices include a high performance bipolar transistor, Zener diode, high resistance poly resistor with no additional photo layer, tantalum nitride resistor with low temperature coefficient, metal-insulator-metal capacitor, metal-oxide-metal capacitor, electrical fuse, and multi-time programmable memory.

To support power ICs for more stringent reliability requirements, as in automotive applications, this third generation BCD process technology was qualified based on the automotive grade qualification specification of AEC-Q100 with Grade1 temperature conditions between -40 to 125 °C.

YJ Kim, Chief Executive Officer of MagnaChip, commented, “Our third generation 0.18 micron BCD process technology with low specific on-resistance is highly suitable for many power IC applications because it helps  reduce  chip size and improve power efficiency. And we will continue to improve the performance of our BCD technology, as it will help our customers increase the competitiveness of their products.”

Today, Mobile Semiconductor announced their new 22nm FDX ULP (Ultra Low Power) Memory Compiler complete with a comprehensive set of features that cement their leadership position in FDX Memory Compiler offerings.

This new Memory Compiler offers an Ultra-Low Power mode at 0.65V that is useful to a wide range of wearable and battery powered devices.  The 22nm FDX ULP joins their expanding 22nm FDX Memory Compiler family that currently covers a wide range of speeds, power requirements, and ultra-low leakage offerings.  The 22nm ULP product draws from the expertise developed over the past three years with our successful 28nm and 55nm Memory Compilers.

Cameron Fisher, CEO and Founder of Mobile Semiconductor, said, “We believe our approach to anticipating the needs of engineers, and building in industry leading features, set us apart.  Examples mentioned by current customers includes low power level shifters and isolation cells.  Without these features, the designer cannot power off the memory entirely resulting in wasted energy and a substandard product.  Mobile Semiconductor Memory Compilers truly allow for complete power down and rapid start-up.”

The Mobile Semiconductor / GlobalFoundries 22FDX platform include 100% of what a design team demands:

  • 0.65V and 0.5V Logic Support
  • Integrated Power Solutions
  • Output Isolation
  • Multiple Power Modes
  • Single Port and Register File Compilers
  • Pseudo Dual Port Support
  • Flexible Reverse Body Bias Support

Fisher continued, “Mobile Semiconductor remains the leader in providing low power memory complier solutions.  But it’s not enough to have a feature rich offering on one product like the 22nm FDX ULP, we also believe that it’s our obligation to provide a range of other products such as 28nm and 55nm AND to design them with the features that best support the demands of the market segments.”

A NIMS-led research group succeeded in developing a high-quality diamond cantilever with among the highest quality (Q) factor values at room temperature ever achieved. The group also succeeded for the first time in the world in developing a single crystal diamond microelectromechanical systems (MEMS) sensor chip that can be actuated and sensed by electrical signals. These achievements may popularize research on diamond MEMS with significantly higher sensitivity and greater reliability than existing silicon MEMS.

Micrographs of the diamond MEMS chip developed through this research and one of the diamond cantilevers integrated into the chip. Credit: NIMS

MEMS sensors–in which microscopic cantilevers (projecting beams fixed at only one end) and electronic circuits are integrated on a single substrate–have been used in gas sensors, mass analyzers and scanning microscope probes. For MEMS sensors to be applied in a wider variety of fields, such as disaster prevention and medicine, their sensitivity and reliability need to be further increased. The elastic constant and mechanical constant of diamond are among the highest of any material, making it promising for use in the development of highly reliable and sensitive MEMS sensors. However, three-dimensional microfabrication of diamond is difficult due to its mechanical hardness. This research group developed a “smart cut” fabrication method which enabled microprocessing of diamond using ion beams and succeeded in fabricating a single crystal diamond cantilever in 2010. However, the quality factor of the diamond cantilever was similar to that of existing silicon cantilevers because of the presence of surface defects.

The research group subsequently developed a new technique enabling atomic-scale etching of diamond surfaces. This etching technique allowed the group to remove defects on the bottom surface of the single crystal diamond cantilever fabricated using the smart cut method. The resulting cantilever exhibited Q factor values–a parameter used to measure the sensitivity of a cantilever–greater than one million; among the world’s highest. The group then formulated a novel MEMS device concept: simultaneous integration of a cantilever, an electronic circuit that oscillates the cantilever and an electronic circuit that senses the vibration of the cantilever. Finally, the group developed a single crystal diamond MEMS chip that can be actuated by electrical signals and successfully demonstrated its operation for the first time in the world. The chip exhibited very high performance; it was highly sensitive and capable of operating at low voltages and at temperatures as high as 600°C.

These results may expedite research on fundamental technology vital to the practical application of diamond MEMS chips and the development of extremely sensitive, high-speed, compact and reliable sensors capable of distinguishing masses differing by as light as a single molecule.

A research study on low noise and high-performance transistors led by Suprem Das, assistant professor of industrial and manufacturing systems engineering, in collaboration with researchers at Purdue University, was recently published by Physical Review Applied.

The study has demonstrated micro/nano-scale transistors made of two-dimensional atomic thin materials that show high performance and low noise. The devices are less than one-hundredth of the diameter of a single human hair and could be key to innovating electronics and precision sensing.

Many researchers worldwide are focusing attention on building the next generation of transistors from atomic scale “exotic” 2D materials such as molybdenum di-selenide. These materials are promising because they show high-performance transistor-action that may, in the future, replace today’s silicon electronics. However, very few of them are looking at yet another important aspect: the inherent electronic noise in this new class of materials. Electronic noise is ubiquitous to all devices and circuits and only worsens when the material becomes atomic thin.

A recent study conducted by Das’ research team has systematically shown that if one can control the layer thickness between 10 and 15-atomic thin in a transistor, the device will not only show high performance — such as turning the switch “on” — but also experience very low electronic noise. This unique finding is essential to building several enabling technologies in electronics and sensing using a number of emerging 2D materials. This research is a comprehensive effort of a previous finding, where Das’ team conducted the first study on noise in MoSe2 transistors.

A team of researchers at the New York University Tandon School of Engineering and NYU Center for Neural Science has solved a longstanding puzzle of how to build ultra-sensitive, ultra-small electrochemical sensors with homogenous and predictable properties by discovering how to engineer graphene structure on an atomic level.

Finely tuned electrochemical sensors (also referred to as electrodes) that are as small as biological cells are prized for medical diagnostics and environmental monitoring systems. Demand has spurred efforts to develop nanoengineered carbon-based electrodes, which offer unmatched electronic, thermal, and mechanical properties. Yet these efforts have long been stymied by the lack of quantitative principles to guide the precise engineering of the electrode sensitivity to biochemical molecules.

Davood Shahrjerdi, an assistant professor of electrical and computer engineering at NYU Tandon, and Roozbeh Kiani, an assistant professor of neural science and psychology at the Center for Neural Science, Faculty of Arts and Science, have revealed the relationship between various structural defects in graphene and the sensitivity of the electrodes made of it. This discovery opens the door for the precise engineering and industrial-scale production of homogeneous arrays of graphene electrodes. The researchers detail their study in a paper published today in the journal Advanced Materials.

Graphene is a single, atom-thin sheet of carbon. There is a traditional consensus that structural defects in graphene can generally enhance the sensitivity of electrodes constructed from it.  However, a firm understanding of the relationship between various structural defects and the sensitivity has long eluded researchers. This information is particularly vital for tuning the density of different defects in graphene in order to achieve a desired level of sensitivity.

“Until now, achieving a desired sensitivity effect was akin to voodoo or alchemy — oftentimes, we weren’t sure why a certain approach yielded a more or less sensitive electrode,” Shahrjerdi said. “By systematically studying the influence of various types and densities of material defects on the electrode’s sensitivity, we created a physics-based microscopic model that replaces superstition with scientific insight.”

In a surprise finding, the researchers discovered that only one group of defects in graphene’s structure — point defects — significantly impacts electrode sensitivity, which increases linearly with the average density of these defects, within a certain range. “If we optimize these point defects in number and density, we can create an electrode that is up to 20 times more sensitive than conventional electrodes,” Kiani explained.

These findings stand to impact both the fabrication of and applications for graphene-based electrodes. Today’s carbon-based electrodes are calibrated for sensitivity post-fabrication, a time-consuming process that hampers large-scale production, but the researchers’ findings will allow for the precise engineering of the sensitivity during the material synthesis, thereby enabling industrial-scale production of carbon-based electrodes with reliable and reproducible sensitivity.

Currently, carbon-based electrodes are impractical for any application that requires a dense array of sensors: The results are unreliable due to large variations of the electrode-to-electrode sensitivity within the array. These new findings will enable the use of ultra-small carbon-based electrodes with homogeneous and extraordinarily high sensitivities in next-generation neural probes and multiplexed “lab-on-a-chip” platforms for medical diagnostics and drug development, and they may replace optical methods for measuring biological samples including DNA.

An international team of researchers has developed a technique that, for the first time, allows single-crystal hybrid perovskite materials to be integrated into electronics. Because these perovskites can be synthesized at low temperatures, the advance opens the door to new research into flexible electronics and potentially reduced manufacturing costs for electronic devices.

Hybrid perovskite materials contain both organic and inorganic components and can be synthesized from inks, making them amenable to large-area roll-to-roll fabrication. These materials are the subject of extensive research for use in solar cells, light-emitting diodes (LEDs) and photodetectors. However, there have been challenges in integrating single-crystal hybrid perovskites into more classical electronic devices, such as transistors.

Single-crystal hybrid perovskites are preferable because single-crystalline materials have more desirable properties than polycrystalline materials; polycrystalline materials contain more defects that adversely affect a material’s electronic properties.

The challenge in incorporating single-crystal hybrid perovskites into electronics stems from the fact that these macroscopic crystals, when synthesized using conventional techniques, have rough, irregular edges. This makes it difficult to integrate with other materials in such a way that the materials make the high-quality contacts necessary in electronic devices.

The researchers got around this problem by synthesizing the hybrid perovskite crystals between two laminated surfaces, essentially creating a single-crystal hybrid perovskite sandwich. The perovskite conforms to the materials above and below, resulting in a sharp interface between the materials. The substrate and superstrate, the “bread” in the sandwich, can be anything from glass slides to silicon wafers that are already embedded with electrodes – resulting in a ready-made transistor or circuit.

The researchers can further fine-tune the electrical properties of the perovskite by selecting different halides for use in the perovskite’s chemical make-up. The choice of halide determines the bandgap of the material, which affects the color appearance of the resulting semiconductor and leads to transparent and even imperceptible electronic devices when using high-bandgap perovskites.

“We have demonstrated the ability to create working field-effect transistors using single-crystal hybrid perovskite materials fabricated in ambient air,” says Aram Amassian, corresponding author of a paper on the work and an associate professor of materials science and engineering at NC State.

“That’s of interest because traditional single-crystal materials have to be manufactured in ultra-high vacuum, high-temperature environments, and often require exquisite epitaxial growth,” Amassian says. “Hybrid perovskites can be grown from solution, essentially from an ink, in ambient air at temperatures below 100 degrees Celsius. This makes them attractive from a cost and manufacturing standpoint. It also makes them compatible with flexible, plastic-based substrates, meaning that they may have applications in flexible electronics and in the internet of things (IoT).

“That said, there are still major challenges here,” Amassian says. “For example, current hybrid perovskites contain lead, which is toxic and therefore not something that’s desirable for applications like wearable electronics. However, research is ongoing to develop hybrid perovskites that don’t contain lead or that are even entirely metal-free. This is an exciting area of research, and we feel this work is a significant step forward for the device integration of these materials, leading to the development of new technological applications.”