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Using scanning capacitance microscopy with a Park Systems atomic force microscope a team at NASA successfully characterized both the spatial variations in capacitance as well as the topography of vacuum-channel nanoelectronic transistors.

BY MARK ANDREWS, Park Systems, Santa Clara, CA

Imagine the not-too-distant future when a NASA spacecraft edges silently into orbit around Mars. Its 473-million-mile journey included a trip around the sun to sling shot itself into in geosynchronous orbit. Its mission: gather new site-specific details and deploy a rover as preludes to the first human mission to the red planet. But before anyone can take ‘one giant leap’, the Mars Path Marker needs to supply fresh data to anxious scientists back on earth.

The probe cost $1.8 billion. Its planning, construction and flight time to Mars took eight years and thousands of work hours from all across the aerospace supply chain.

Red lights are now flashing all across screens back on earth at NASA’s Jet Propulsion Laboratory in Pasadena, California. The probe remains inactive while its earth-side controllers grow frantic. Path Marker should have automatically powered-up for its first mapping transit, but instead hangs quietly above the ruddy Martian landscape.

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Unbeknownst to controllers on earth, Path Marker wasn’t responding because of a short-circuit ‘latch-up’ in its silicon processors. Communications won’t resume for now—maybe not ever.

Earth could not see it happen, but when Path Marker flew around Sol, its passage coincided with an unusually large solar flare on the backside of oursun. More energy than what usually strikes Mars in six months was released in a series of coronal explosions, sending cascades of lethal, heavy ions plowing through Path Marker’s delicate solid- state transistors as if its shielding wasn’t even there.

Despite the best of plans, precautions and preparations, this spacecraft is stuck in perpetual ‘neutral.’ Mission specialistsare trying all availablemission-saving workarounds, but only time will tell.

NASA researcher Dr. Jin-Woo Han hopes to prevent a critical failure in an important mission like this fictional account of the Mars Path Marker. In reality NASA has experienced all types of solid-state electronic failures during its decades of manned and robotic explorations. In his work, Dr. Han documented nine different types of failures in 17 named missions as well as many more that did not cause a mission failure, but impeded or slowed a program.

Although the Mars Path Marker mission is fictional, the need for a better semiconductor technology for deep space exploration is very real. That need is why Dr. Han and colleagues have placed hope in a new approach to solid state transistors that utilizessome of the same principles that gave vacuum tubes their role in humanity’s first electronic products more than 100 years ago.

Han is a scientist at NASA’s Ames Research Center for Nanotechnology in Moffett Field, California. The center is led by Dr. Meyya Meyyappan; Dr. Han leads the vacuum device research team within the 20-person organization. One of his most recent research efforts is tied to his theories and practical applications that leverage the advantages of vacuum for creating better electron flow, but without the drawbacks in existing solid-state technology that NASA frequently faces. The new transistors, called vacuum-channel nanoelectronic devices, are not prone to disruption by cosmic radiation, solar flares, radical temperature changes or similar dangers that can be encountered once a spacecraft (or humans) leave earth’s magnetic fields and dense atmosphere.

The challenges of space exploration are daunting. While loss of life tops many potentially egregious outcomes, damage to spacecraft instruments occurs much more commonly than the general public may realize. This damage remains a source of concentrated research and engineering efforts to mitigate and remedy problems that can lead to lack-luster performance or full system failures. The efforts to ensure safe and productive operation in satellites, probes and spacecraft is second only to the agency’s zeal for keeping human space flight safe.

How can early 20th century vacuum tube technology solve NASA’s very 21st century problems? First of all, the vacuum nanotechnology that NASA is developing is gener- ations beyond conventional vacuum tube engineering as it stood in the early 20th century. But vacuum-channel nanostructures and conventional vacuum tubes share essential functional similarities that make Dr. Han’s devices ideal candidates to replace today’s most robust silicon-based transistors.

Transistors enjoy their role in electronic technology because of their unique abilities to amplify and switch electronic signals as well as electrical power. Power or current applied to one set of terminals controls the current as it flows to another terminal pair (emitters/ collectors). And while a practical solid-state transistor was proposed in 1926 by Canadian researchers, materials science only matured enough for production in 1947; the landmark year in which researchers at the AT&T Bell Labs (New Jersey, USA), and independently a year later in France proposed designs that would become the forefa- thers of today’s microelectronic wonders.

Practical vacuum tube components came into play before 1910, and have several important advantages compared to solid-state transistors including their superior electron mobility. Like their solid-state cousins, tube transistors function by moving electrons unidirectionally from the emitter (a cathode) to be collected by the anode across a vacuum. Tubes fell out of favor for most low and medium power applications due to the advantages of solid-state construction including much smaller size and weight, ruggedness that exceeded old-style tubes, their aggre- gation ability that enabled today’s integrated circuits (ICs), and zero warm-up time – silicon transistors requireno cathode warming function. Solid-state devices also provide substantially greater electrical current efficiency.

It’s easy to see why solid-state electronics won a place in aerospace engineering. But once we actually got into space, we learned quickly that even robust silicon transistors were no match for deep space radiation. To make the best transistors that we had “good enough” for space, NASA mastered the process of creating backup systems and a host of other measures to keep missions on track. It also partnered with other agencies like DARPA (Defense Advanced Research Projects Agency) and the US Department of Defense to develop alternate technologies such as gallium arsenide (GaAs), gallium nitride (GaN), and the latest work from Dr. Han’s nanotech vacuum team. GaAs and GaN are much more robust than silicon, but decades of research have proven them less suitable for construction complex ICs than silicon.

Although conventional solid-state transistors enjoy clear advantages in terrestrial applications, in-space damage typically comes in three forms: instantaneous, cumulative and catastrophic. While the first two effects can frequently be worked around due to NASA’s extensive reliance on back-up systems, catastrophic effects can be “mission enders.”

Dealing with likely and possible performance disruptions costs NASA dearly in terms of extra weight, design time to createmultiple backup systems that can also complicate missions while consuming valuable payload space. Imagine if using a laptop computer on earth required double or even triple the amount of vital components—that laptop would easily be a third larger and more expensive. For NASA, ignoring risks will impede success or in worst-case situations lead to a disaster that costs millions and could even endanger lives if components weretied to a human spaceflight mission.

A common way to deal with these unknowns is to overbuild—create more circuit pathways or entire redundant subsystems because some components will almost certainly be “sacrificed” during encounters with space radiation. NASA frequently must opt for “acceptable” performance instead of what might ideally be possible simply because they cannot count of systems that have optimal performance will remain that way throughout an entire mission.

The advantage a controlled vacuum has in transistors is tied to the fact that solid-state devices can experience long-term failures resulting from additive and cumulative effects from multiple bombardments of ionizing radiation that destroys device features at nanometer scale. This most commonly occurs when the total ionizing dose causes gradual parametric shifts, resulting in on-state current reductions and an increase in off-stage current leakage. A vacuum-based device does not typically suffer from these same effects in part because the absence of material (gases or solids) in the space between emitters and collectors not only speeds the flow of electrons but in essence is protective because there is very little present in this tiny void that might be damaged by ionizing radiation.

Dr. Han’s team studied several different compounds and structures that could be utilized to construct the vacuum channel nano devices that would eventually prove likely successors to conventional transistors. These materials included bulk MOS, silicon-on-insulator (SOI), gate-all- around (GAA) MOSFET and what proved to be the most promising material and design combination, a GAA nanowire in a vacuum gate dielectric (FIGURE 1).

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To be effective and meet NASA’s requirements, new transistor technology had to be manufacturable at industrial scale using existing processes and techniques common to conventional silicon fabs or similar infrastructure. The ideal design would bring the “best of both worlds” together for a solution that is electrically sound, practical and compact as well as lightweight and reliable in the face of exposure to radiation and radical temperature fluctuations.

“But we did not ever approach this as a replacement for all silicon electronics or silicon transistors at large,” said Dr. Han. “While the devices could easily be used on earth—that is where we tested them in gamma radiation chambers after all—but the cost efficiencies of regular silicon MOSFET could not very likely improved by our vacuum-channel nanoelectronic designs.”

To measure device performance Dr. Han and his team employed a Scanning Capacitance Microscope (SCM) with an Atomic Force Microscope (AFM) from Park Systems. They investigated the nanoscale properties of vacuum- channel devices, seeking to ascertain their viability as a transistor while also observing if fabrication method- ology for gate insulators can be controlled.

“SCM with AFM is a powerful combination for investigating transistor devices—together, the two methods provide the user with a non-destructive process of characterizing both charge distribution and surface topography with high spatial resolution and sensitivity,” said Byong Kim, Analytical Systems Director, Park Systems.

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Kim explained that atomic force microscopy with SCM is ideal for investigating transistor designs at the nano scale. Together, the two methods provide researchers with non-destructive processes for characterizing both charge distribution and surface topography with high spatial resolution and sensitivity. In SCM, a metal probe tip and a highly sensitive capacitance sensor augment standard AFM hardware. During testing, voltage is applied between the probe tip and the sample surface. This creates a pair of capacitors in series (when examining metal-oxide-semiconductor devices) from the insulating oxide layer on the device surface and the active depletion layer at the interfacial region located between the oxide layer and doped silicon. Total capacitance is then deter- mined by the thicknesses of the oxide layer as well as the depletion layer, which is influenced by the level of silicon substrate dopingas well as the amount of DC voltage being applied between the tip and device’s surface.

Dr. Han reported that by utilizing scanning capacitance microscopy with a Park Systems atomic force micro- scope the team successfully characterized both the spatial variations in capacitance as well as the topog- raphy of his vacuum-channel nanoelectronic transistors. By examining the line profiles of the topography and capacitance data acquired down an identical path along the device’s source-drain interface, further insight was gained into the relationship between key physical struc- tures and recorded changes in capacitance.

The nanoelectronic device’s topography (at the source- drain interface) was imaged and revealed a vacuum- channel spanning 250 nm in length with peaks and valleys separated by a distance of approximately 5 nm (FIGURES 3-5). The electrical functionality of the device was assessed through the acquisition of a capacitance map. This map revealed a relatively negatively charged (-1.4 to -1.8μV) source-drain terminal and adjacent quantum dot followed by a relatively positively charged vacuum- channel (2μV) and another dot-terminal structure (-1.4 to -1.8μV) on the other end of the source-drain interface. This alternating series of capacitance changes at key structural points suggest that the device is fully capable of functioning as an effective transistor.

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NASA is now working towards next steps to investigate the potential of producing vacuum-channel nanoelectronic devices in higher volumes for further study. The team utilized standard semiconductor manufacturing techniques, so while fabrication is within existing process and materials technologies, settling on the ideal material for the transistors is also still being investigated.

“While the work initially focused on silicon as an under- lying technology, we next want to explore silicon carbide and graphene as alternatives—technologies that are more robust. Also, the charge emission efficiency of silicon may not be sufficient and we saw some degradation due to oxidization,” he remarked. “While we have demonstrated that a silicon vacuum-channel nanoelectronic device is possible. We now need to look at better emitter efficiency and reliability, balanced against ease of manufacturing – everything is a tradeoff in some regards.”

The Ames Research Center is open to partnering through industrial and university collaboration, like the work it has done in conjunction with Park Systems. NASA is already working with additional industrial partners and welcomes further collaboration.

A key step in unlocking the potential for greener, faster, smaller electronic circuitry was taken recently by a group of researchers led by UAlberta physicist Robert Wolkow.

The research team found a way to delete and replace out-of-place atoms that had been preventing new revolutionary circuitry designs from working. This unleashes a new kind of silicon chips for used in common electronic products, such as our phones and computers.

“For the first time, we can unleash the powerful properties inherent to the atomic scale,” explained Wolkow, noting that printing errors on silicon chips are inevitable when working at the atomic scale. “We were making things that were close to perfect but not quite there. Now that we have the ability to make corrections, we can ensure perfect patterns, and that makes the circuits work. It is this new ability to edit at the atom scale that makes all the difference.”

Think of a typing mistake and the ability to go back and white it out and type it again perfectly. Now imagine that the white out is actually single hydrogen atoms, allowing a level of precision previously unattainable.

“We can precisely erase any errors and reprint that atom in the correct place. It’s not even a compromise like white out where you either have a gooey layer or indentation. It’s actually perfect,” said Wolkow, who worked with fellow scientists from the University of Alberta, the National Research Council, and Quantum Silicon Inc.

Scientists have seen many hints that atomic circuitry was within reach. However, the necessary precision was previously possible only for simple materials that had to be maintained at ultra-low temperatures, impractical for everyday applications demanded in computers and personal digital devices. Wolkow and his team have discovered methods and material to ensure stability at room temperature, challenges that he and other scientists the world over have been working for decades on overcoming.

Wolkow’s graduate students Roshan Achal and Taleana Huff together with postdoc Moe Rashidi showed they can overcome these obstacles with a modified approach to the same silicon chips that are used in today’s circuitry. While they had previously improved accuracy of atomic silicon printing, errors in the form of misplaced atoms always occurred at the one percent level. Though the placement errors were small–about one third of a nanometer–they nevertheless large enough to upset circuit operation.

The students created a reliable procedure for picking up single hydrogen atoms with their atomically sharp probe and replacing one or more hydrogen atoms to perfectly erase atomic misprints.

With their new discovery, many remaining challenges to ultra-low power atomic circuitry have also been erased. Wolkow, Achal, and Huff’s discovery has been captured in the academic paper “Atomic Whiteout,” appearing in the scientific journal ACS Nano.

 

A team of physicists featuring researchers from MIPT and ITMO University has conducted a comparative analysis of a range of materials to determine if they are applicable to dielectric nanophotonics. Their systematic study produced results that can optimize the use of known materials for building optical nanodevices, as well as encourage the search for new materials with superior properties.

In order to send, receive, and process electromagnetic signals, antennas are used. An antenna is a device capable of effectively transmitting, picking up, and redirecting electromagnetic radiation. Typically, one thinks of antennas as macroscopic devices operating in the radio and microwave range. However, there are similar optical devices. The wavelengths of visible light amount to several hundred nanometers. As a consequence, optical antennas are, by necessity, nanosized devices. Optical nanoantennas, which can focus, direct, and effectively transmit light, have a wide range of applications, including information transmission over optical channels, photodetection, microscopy, biomedical technology, and even speeding up chemical reactions.

For an antenna to pick up and transmit signals efficiently, its elements need to be resonant. In the radio band, such elements are pieces of wire. In the optical range, silver and gold nanoparticles with plasmonic resonances have long been used for this purpose. Electromagnetic fields in such particles can be localized on a scale of 10 nanometers or less, but most of the energy of the field is wasted due to Joule heating of the conducting metal. There is an alternative to plasmonic nanoparticles, which has been studied extensively for the last five years, namely particles of dielectric materials with high refractive indices at visible light frequencies, such as silicon. When the size of the dielectric particle and the wavelength of light are just right, the particle supports optical resonances of a particular kind, called Mie resonances. Because the material properties of dielectrics are different from those of metals, it is possible to significantly reduce resistive heating by replacing plasmonic nanoantennas with dielectric analogs.

The key characteristic of a material determining Mie resonance parameters is the refractive index. Particles made of materials with high refractive indices have resonances characterized by high quality factors. This means that in these materials electromagnetic oscillations last longer without external excitation. In addition, higher refractive indices correspond to smaller particle diameters, allowing for more miniature optical devices. These factors make high-index materials — i.e., those with high indices of refraction — more suitable for the implementation of dielectric nanoantennas.

In their paper published in Optica, the researchers systematically examine the available high-index materials in terms of their resonances in the visible and infrared spectral ranges. Materials of this kind include semiconductors and polar crystals, such as silicon carbide. To illustrate the behavior of various materials, the authors present their associated quality factors, which indicate how quickly oscillations excited by incident light die out. Theoretical analysis enabled the researchers to identify crystalline silicon as the best currently available material for the realization of dielectric antennas operating in the visible range, with germanium outperforming other materials in the infrared band. In the mid-infrared part of the spectrum, which is of particular interest due to possible applications, such as radiative cooling, i.e., the cooling of a heated body by means of radiating heat in the form of electromagnetic waves into the environment; and thermal camouflage — reducing thermal radiation given off by an object, thus making it invisible to infrared cameras, the compound of germanium and tellurium took the pedestal.

There are fundamental limitations on the value of the quality factor. It turns out that high refractive indices in semiconductors are associated with interband transitions of electrons, which inevitably entail the absorption of energy carried by the incident light. This absorption in turn leads to a reduction of the quality factor, as well as heating, and that is precisely what the researchers are trying to get rid of. There is, therefore, a delicate balance between a high index of refraction and energy losses.

“This study is special both because it offers the most complete picture of high-index materials, showing which of them is optimal for fabricating a nanoantenna operating in this spectral range, and because it provides an analysis of the manufacturing processes involved,” notes Dmitry Zuev, research scientist at the Metamaterials laboratory of the Faculty of Physics and Engineering, ITMO University. “This enables a researcher to select a material, as well as the desired manufacturing technique, taking into account the requirements imposed by their specific situation. This is a powerful tool furthering the design and experimental realization of a wide range of dielectric nanophotonic devices.”

According to the overview of manufacturing techniques, silicon, germanium, and gallium arsenide are the most thoroughly studied high-index dielectrics used in nanophotonics. A wide range of methods are available for manufacturing resonant nanoantennas based on these materials, including lithographic, chemical, and laser-assisted methods. However, in the case of some materials, no technology for fabrication of resonant nanoparticles has been developed. For example, researchers have yet to come up with ways of making nanoantennas from germanium telluride, whose properties in the mid-infrared range were deemed the most attractive by the theoretical analysis.

“Silicon is currently, beyond any doubt, the most widely used material in dielectric nanoantenna manufacturing,” says Denis Baranov, a PhD student at MIPT. “It is affordable, and silicon-based fabrication techniques are well established. Also, and this is important, it is compatible with the CMOS technology, an industry standard in semiconductor engineering. But silicon is not the only option. Other materials with even higher refractive indices in the optical range might exist. If they are discovered, this would mean great news for dielectric nanophotonics.”

The research findings obtained by the team could be used by nanophotonics engineers to develop new resonant nanoantennas based on high-index dielectric materials. Besides, the paper suggests further theoretical and experimental work devoted to the search for other high-index materials with superior properties to be used in new improved dielectric nanoantennas. Such materials could, among other things, be used to considerably boost the efficiency of radiative cooling of solar cells, which would constitute an important technological advance.

While the charge and spin properties of electrons are widely utilized in modern day technologies such as transistors and memories, another aspect of the subatomic particle has long remained uncharted. This is the “valley” property which has potential for realizing a new class of technology termed “valleytronics” – similar to electronics (charge) and spintronics (spin). This property arises from the fact that the electrons in the crystal occupy different positions that are quantum mechanically distinct.

Now City College of New York physicists led by Vinod Menon have demonstrated how to manipulate the “valley” property using light by placing two-dimensional semiconductors in a light trapping structure called microcavity. This gave rise to half-light-half matter quasi-particles which have the fingerprint of the “valley” property. These quasi-particles were then optically controlled using a laser to access the electrons occupying specific “valley.” The research appears in the latest issue of Nature Photonics and is a major step towards realization of “valleytronic” devices for logic gates.

“Observing this property in traditional semiconductors was not easy. However with the advent of the new class of two-dimensional semiconductors, this property became accessible to manipulation,” said Zheng Sun, a graduate student in Menon’s research group and lead author of the paper.

The ‘wonder material’ graphene has many interesting characteristics, and researchers around the world are looking for new ways to utilise them. Graphene itself does not have the characteristics needed to switch electrical currents on and off and smart solutions must be found for this particular problem. “We can make graphene structures with atomic precision. By selecting certain precursor substances (molecules), we can code the structure of the electrical circuit with extreme accuracy,” explains Peter Liljeroth from Aalto University, who conceived the research project together with Ingmar Swart from Utrecht University.

Seamless integration

The electronic properties of graphene can be controlled by synthesizing it into very narrow strips (graphene nanoribbons). Previous research has shown that the ribbon’s electronic characteristics are dependent on its atomic width. A ribbon that is five atoms wide behaves similarly to a metallic wire with extremely good conduction characteristics, but adding two atoms makes the ribbon a semiconductor. “We are now able to seamlessly integrate five atom-wide ribbons with seven atom-wide ribbons. That gives you a metal-semiconductor junction, which is a basic building block of electronic components,” according to Ingmar Swart.

Chemistry on a surface

The researchers produced their electronic graphene structures through a chemical reaction. They evaporated the precursor molecules onto a gold crystal, where they react in a very controlled way to yield new chemical compounds. “This is a different method from that currently used to produce electrical nanostructures, such as those on computer chips. For graphene, it is so important that the structure is precise at the atomic level and it is likely that the chemical route is the only effective method,” Ingmar Swart concludes.

Electronic characteristics

The researchers used advanced microscopic techniques to also determine the electronic and transport characteristics of the resulting structures. It was possible to measure electrical current through a graphene nanoribbon device with an exactly known atomic structure. “This is the first time where we can create e.g. a tunnel barrier and really know its exact atomic structure. Simultaneous measurement of electrical current through the device allows us to compare theory and experiment on a very quantitative level,” says Peter Liljeroth.

Imagine slipping into a jacket, shirt or skirt that powers your cell phone, fitness tracker and other personal electronic devices as you walk, wave and even when you are sitting.

A new, ultrathin energy harvesting system developed at Vanderbilt University’s Nanomaterials and Energy Devices Laboratory has the potential to do just that. Based on battery technology and made from layers of black phosphorus that are only a few atoms thick, the new device generates small amounts of electricity when it is bent or pressed even at the extremely low frequencies characteristic of human motion.

“In the future, I expect that we will all become charging depots for our personal devices by pulling energy directly from our motions and the environment,” said Assistant Professor of Mechanical Engineering Cary Pint, who directed the research.

The new energy harvesting system is described in a paper titled “Ultralow Frequency Electrochemical Mechanical Strain Energy Harvester using 2D Black Phosphorus Nanosheets” published Jun.21 online by the journal ACS Energy Letters.

“This is timely and exciting research given the growth of wearable devices such as exoskeletons and smart clothing, which could potentially benefit from Dr. Pint’s advances in materials and energy harvesting,” observed Karl Zelik, assistant professor of mechanical and biomedical engineering at Vanderbilt, an expert on the biomechanics of locomotion who did not participate in the device’s development.

Currently, there is a tremendous amount of research aimed at discovering effective ways to tap ambient energy sources. These include mechanical devices designed to extract energy from vibrations and deformations; thermal devices aimed at pulling energy from temperature variations; radiant energy devices that capture energy from light, radio waves and other forms of radiation; and, electrochemical devices that tap biochemical reactions.

“Compared to the other approaches designed to harvest energy from human motion, our method has two fundamental advantages,” said Pint. “The materials are atomically thin and small enough to be impregnated into textiles without affecting the fabric’s look or feel and it can extract energy from movements that are slower than 10 Hertz–10 cycles per second–over the whole low-frequency window of movements corresponding to human motion.”

Doctoral students Nitin Muralidharan and Mengya Li co-led the effort to make and test the devices. “When you look at Usain Bolt, you see the fastest man on Earth. When I look at him, I see a machine working at 5 Hertz,” said Muralidharan.

Extracting usable energy from such low frequency motion has proven to be extremely challenging. For example, a number of research groups are developing energy harvesters based on piezoelectric materials that convert mechanical strain into electricity. However, these materials often work best at frequencies of more than 100 Hertz. This means that they don’t work for more than a tiny fraction of any human movement so they achieve limited efficiencies of less than 5-10 percent even under optimal conditions.

“Our harvester is calculated to operate at over 25 percent efficiency in an ideal device configuration, and most importantly harvest energy through the whole duration of even slow human motions, such as sitting or standing,” Pint said.

The Vanderbilt lab’s ultrathin energy harvester is based on the group’s research on advanced battery systems. Over the past 3 years, the team has explored the fundamental response of battery materials to bending and stretching. They were the first to demonstrate experimentally that the operating voltage changes when battery materials are placed under stress. Under tension, the voltage rises and under compression, it drops.

The team collaborated with Greg Walker, associate professor of mechanical engineering, who used computer models to validate these observations for lithium battery materials. Results of the study were published Jun. 27 in the journal ACS Nano in an article titled “The MechanoChemistry of Lithium Battery Electrodes.”

These observations led Pint’s team to reconstruct the battery with both positive and negative electrodes made from the same material. Although this prevents the device from storing energy, it allows it to fully exploit the voltage changes caused by bending and twisting and so produce significant amounts of electrical current in response to human motions.

The lab’s initial studies were published in 2016. They were further inspired by a parallel breakthrough by a group at Massachusetts Institute of Technology who produced a postage-stamp-sized device out of silicon and lithium that harvested energy via the effect Pint and his team were investigating.

In response, the Vanderbilt researchers decided to go as thin as possible by using black phosphorus nanosheets: A material has become the latest darling of the 2D materials research community because of its attractive electrical, optical and electrochemical properties.

Because the basic building blocks of the harvester are about 1/5000th the thickness of a human hair, the engineers can make their devices as thin or as thick as needed for specific applications. They have found that bending their prototype devices produces as much as 40 microwatts per square foot and can sustain current generation over the full duration of movements as slow as 0.01 Hertz, one cycle every 100 seconds.

The researchers acknowledge that one of the challenges they face is the relatively low voltage that their device produces. It’s in the millivolt range. However, they are applying their fundamental insights of the process to step up the voltage. They are also exploring the design of electrical components, like LCD displays, that operate at lower than normal voltages.

“One of the peer reviewers for our paper raised the question of safety,” Pint said. “That isn’t a problem here. Batteries usually catch on fire when the positive and negative electrodes are shorted, which ignites the electrolyte. Because our harvester has two identical electrodes, shorting it will do nothing more than inhibit the device from harvesting energy. It is true that our prototype will catch on fire if you put it under a blowtorch but we can eliminate even this concern by using a solid-state electrolyte.”

One of the more futuristic applications of this technology might be electrified clothing. It could power clothes impregnated with liquid crystal displays that allow wearers to change colors and patterns with a swipe on their smartphone. “We are already measuring performance within the ballpark for the power requirement for a medium-sized low-power LCD display when scaling the performance to thickness and areas of the clothes we wear.” Pint said.

Pint also believes there are potential applications for their device beyond power systems. “When incorporated into clothing, our device can translate human motion into an electrical signal with high sensitivity that could provide a historical record of our movements. Or clothes that track our motions in three dimensions could be integrated with virtual reality technology. There are many directions that this could go.”

Conventional electronic devices make use of semiconductor circuits and they transmit information by electric charges. However, such devices are being pushed to their physical limit and the technology is facing immense challenges to meet the increasing demand for speed and further miniaturisation. Spin wave based devices, which utilise collective excitations of electronic spins in magnetic materials as a carrier of information, have huge potential as memory devices that are more energy efficient, faster, and higher in capacity.

While spin wave based devices are one of the most promising alternatives to current semiconductor technology, spin wave signal propagation is anisotropic in nature – its properties vary in different directions – thus posing challenges for practical industrial applications of such devices.

A research team led by Professor Adekunle Adeyeye from the Department of Electrical and Computer Engineering at the NUS Faculty of Engineering, has recently achieved a significant breakthrough in spin wave information processing technology. His team has successfully developed a novel method for the simultaneous propagation of spin wave signals in multiple directions at the same frequency, without the need for any external magnetic field.

Using a novel structure comprising different layers of magnetic materials to generate spin wave signals, this approach allows for ultra-low power operations, making it suitable for device integration as well as energy-efficient operation at room temperature.

“The ability to propagate spin waves signal in arbitrary directions is a key requirement for actual circuitry implementation. Hence, the implication of our invention is far-reaching and addresses a key challenge for the industrial application of spin wave technology. This will pave the way for non-charge based information processing and realisation of such devices,” said Dr Arabinda Haldar, who is the first author of the study and was formerly a Research Fellow with the Department at NUS. Dr Haldar is currently an Assistant Professor at Indian Institute of Technology Hyderabad.

The research team published the findings of their study in the scientific journal Science Advances on 21 July 2017. This discovery builds on an earlier study by the team that was published in Nature Nanotechnology in 2016, in which a novel device that could transmit and manipulate spin wave signals without the need for any external magnetic field or current was developed. The research team has filed patents for these two inventions.

“Collectively, both discoveries would make possible the on-demand control of spin waves, as well as the local manipulation of information and reprogramming of magnetic circuits, thus enabling the implementation of spin wave based computing and coherent processing of data,” said Prof Adeyeye.

Moving forward, the team is exploring the use of novel magnetic materials to enable coherent long distance spin wave signal transmission, so as to further the applications of spin wave technology.

Multitest’s new 0.3 mm pitch Atlas contactor successfully passed a demanding customer production floor evaluation. The customer’s evaluation measures confirmed that the Atlas did reduce the customer’s cost of test while improving test yield and increasing throughput. Based on the evaluation results, the customer ordered a significant number of Atlas 030 contactors to support their new product WLCSP production ramp.

The customer is a long time user of Multitest contactors and after reviewing the new Atlas design they were eager to evaluate it. It is the added strength of the Atlas cruciform tip that captured the customer’s attention.  Not only is the Atlas mechanically superior, the Atlas offers electrical performance that allows the customer to test to the true performance of the device. The evaluation ended with the customer placing an order for a significant quantity of Atlas 030 contactors.
The key to the WLCSP Atlas’s high performance, high reliability and superior electrical contacting is the combination of increased mechanical tip strength and short probe electrical performance.  Atlas WLCSP test contactors achieve mechanical reliability with a rigid “cruciform” tip applied to Multitest’s QuadTech flat probe technology.  The Atlas 030 offers a short electrical path, with lower capacitance and inductance that is ideal for functional and AC parametric testing of WLCSP devices that require high system bandwidth and throughput gains in large multisite test applications.

The cruciform tip provides increased tip rigidity with a much greater immunity to breakage than traditional WLCPS probes used in earlier-generation test sockets. The Atlas 030 has 0.310 mm of compliance for bump structures that requires a larger compliance window for reliable contacting in high parallel test applications.

Bert Brost, Senior Product Managers, explains: “We are very proud of the positive result of the evaluation. The evaluation by the customer confirmed what we already knew, the Atlas 030 contactor is a high performance solution for WLCSP testing.”

Advances in semiconductor and related devices are driving significant progress in our increasingly digital world, and the place to learn about cutting-edge research in the field is the annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel. Highlights for 2017 include:

  • A talk on transformative electronics by Dr. Hiroshi Amano, who received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting.
  • The above talk is part of an exceptional slate of plenary talks to be given by some of the industry’s leading figures. IEDM plenary presenters include the CEO of Advanced Micro Devices, Inc.; the research chief of TSMC, which is the industry’s largest foundry driving technology forward; a leading academic authority on energy-efficient computing, which is a key societal goal; as well as Dr. Amano’s fourth, additional plenary talk. It will be given on Wednesday, Dec. 6.
  • Focus Sessions will be held on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current status and perspectives.
  • A vendor exhibition will be held again, based on the success of last year’s first-ever such event at the IEDM.
  • The IEEE Magnetics Society will host a poster session on MRAM (magnetic RAM memories).

The IEDM paper submission deadline this year is August 2 and the deadline for late-news papers is September 11. Only a limited number of late-news papers will be accepted.

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations along with special luncheon talks and a variety of panels, special sessions, tutorials, Short Courses, IEEE/EDS award presentations and other events that highlight leading work in more diverse areas of the field than any other conference.

“This year’s IEDM will feature talks, courses and panels by world experts on what is perhaps the broadest array of topics in recent memory,” said Dr. Barbara De Salvo, Scientific Director at Leti. “The unique technical program can lead one to view the IEDM as a crystal ball of sorts, because many of the developments reported at the conference invariably make their way into commercial products a few years down the road. As an example, this year’s IEDM conference marks 10 years since the industry transition from aluminum to copper interconnect began in earnest.”

Here are details of some of the events that will take place at this year’s IEDM:

Focus Sessions

  • 3D Integration and Packaging – Packaging technology is taking on an increasingly important role in semiconductor manufacturing, and this session will provide an industry perspective on forthcoming approaches ranging from “Simpler is better” to “Advanced packaging saves the day for continued scaling.” The session will address the latest in 3D, from alternative packaging to 3D stacking, and applications and technologies for Integrated Power Microelectronics.
  • Modeling Challenges for Neuromorphic Computing – This session will address the opportunities and challenges of efficient synaptic processes, from learning models to device-circuit implementations of neuromorphic architectures.  Half of the session will discuss learning models in stochastic processes, with the other half devoted to RRAM (resistive RAM) memory for deep neural networks and neuromorphic computing.
  • Nanosensors for Disease Diagnostics — From microfluidics to nanosensing, this session will review the latest advances for the detection of diseases such as cancer, sepsis and diabetes, using biomarkers ranging from (bio)molecules and individual cells to in-vitro tissue models.
  • Silicon Photonics: Current Status and Perspectives – This session addresses the state-of-the-art in silicon photonics technology, ranging from topics on high-volume manufacturing, optical transceivers and interconnects, to femto-joule per bit integrated nanophotonics for upcoming market applications in optical computing.

90-Minute Tutorials – Saturday, Dec. 2
A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research. Advance registration is recommended.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Sundaram Venkatesh, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, IMEC

Short Courses – Sunday, Dec. 3
Short Courses provide the opportunity to learn about important areas and developments, and provide the opportunity to network with experts from around the world. Advance registration is recommended.

  • Performance Boosters and Variation Management in Sub-5nm CMOS, organized by Sandy Liao, Intel
  • Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang, TSMC

Plenary Presentations – Monday, Dec. 4

  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC
  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University

Evening Panel Session – Tuesday evening, Dec. 5
The IEDM offers attendees an evening session where panels of experts give their views on important industry topics. Audience participation is encouraged to foster an open and vigorous exchange of ideas.

  • Who Will Lead the Industry in the Future? Moderator: Prof. Philip Wong, Stanford University

Entrepreneurs Lunch
The topic and speaker are yet to be determined, but this popular luncheon jointly sponsored by IEDM and the IEEE Electron Devices Society will be held once again.

Further information about IEDM
For registration and other information, visit www.ieee-iedm.org.

SUNY Polytechnic Institute (SUNY Poly) announced today that Interim Dean of Graduate Studies Dr. Fatemeh (Shadi) Shahedipour-Sandvik and her team of collaborators have been selected to receive $720,000 in federal funding from the U.S. Department of Energy’s Advanced Research Projects Agency-Energy (ARPA-E). The grant will be used to develop more efficient and powerful high-performance power switches at SUNY Poly for power electronics applications, such as for enabling a more efficient energy grid, for example. The research is in partnership with Dr. Woongje Sung of SUNY Poly, the Army Research Lab, Drexel University, and Gyrotron Technology, Inc.

“On behalf of SUNY Poly, I am excited to congratulate Professor Shahedipour-Sandvik as her wide-bandgap-focused research is recognized by the Department of Energy for its potential to improve power devices that are all around us to make our technological world more energy efficient and robust,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “This award highlights SUNY Poly’s unique and advanced research capabilities, as well as its superb faculty who are developing the innovations of tomorrow right now in New York State.”

“This award is a strong indicator of how SUNY Poly’s resources and facilities are enabling the types of research that have the potential to improve power electronics devices which have become ubiquitous, from those utilized to make the power grid more efficient, to those that can improve electric car capabilities,” said SUNY Poly Vice President of Research Dr. Michael Liehr.

“I am proud that the U.S. Department of Energy’s ARPA-E has recognized our leading-edge power electronics-focused research, which holds the incredible potential to drive innovation for practical applications that could lead to worldwide energy savings. Advanced power electronic devices offer significant advances in power density, efficiency, and reduced total lifecycle cost,” said Prof. Shahedipour-Sandvik. “This grant allowing our SUNY Poly team and partners at the Army Research Lab, Drexel University and Gyrotron Technology, Inc. to explore advanced doping and annealing techniques for gallium nitride-based power devices is a testament to how SUNY Poly’s resources and leadership in areas like power electronics can help power the future in exciting and meaningful ways.” 

The SUNY Poly grant is part of a total of $6.9 million in funding that the U.S. Department of Energy ARPA-E is providing through its Power Nitride Doping Innovation Offers Devices Enabling SWITCHES (PNDIODES) program to seven institutions and organizations. With PNDIODES, ARPA-E is tackling a specific challenge in wide-bandgap semiconductor production. Wide-bandgap semiconductors are an important area of research because the materials, such as gallium nitride (GaN), allow for electronic devices to operate at higher temperatures and/or frequencies, for example, than current silicon-based computer chips, which is why technical advances in power electronics promise energy efficiency gains throughout the United States economy. Achieving high power conversion efficiency in these systems, however, requires low-loss power semiconductor switches. Power converters based on GaN could potentially meet the challenge by enabling higher voltage devices with improved efficiency—while also dramatically reducing size and weight of the device, for example.

The PNDIODES-funded research focuses on a process called selective area doping, in which a specific impurity is added to a semiconductor to change its electrical properties and achieve performance characteristics that are useful for electronics. Implemented well, this process can allow for the fabrication of devices at a competitive cost compared to their traditional, silicon-based counterparts. Developing a reliable and usable doping process that can be applied to specific regions of GaN and its alloys is an important obstacle in the fabrication of GaN-based power electronics devices that PNDIODES seeks to overcome. Ultimately, the PNDIODES project teams, including the Shahedipour-Sandvik team and Dr. Sung at SUNY Poly as well as the institution’s partners, will develop new ways to build semiconductors for high performance, high-powered applications like aerospace, electric vehicles, and the grid.

Prof. Shahedipour-Sandkvik team’s research, “Demonstration of PN-junctions by ion implantation techniques for GaN (DOPING-GaN),” will focus on ion implantation as the centerpiece of its approach and use new annealing techniques to develop processes to activate implanted silicon or magnesium in GaN to build p-n junctions, which are used to control the flow of electrons within an integrated circuit. Utilizing a unique technique with a gyrotron beam, a high-power vacuum tube that generates millimeter-wave electromagnetic waves, the team’s research aims to understand the impact of implantation on the microstructural properties of the GaN material and its effects on p-n diode performance.

In addition to this GaN-focused research being conducted by Prof. Shahedipour and her team at SUNY Poly, which also provides hands-on research opportunities for a number of the institution’s students, SUNY Poly and General Electric also lead the New York Power Electronics Manufacturing Consortium (NY-PEMC) with the goal of developing and producing low cost, high performance 6″ silicon carbide (SiC) wafers for power electronics applications. The consortium announced its first successful production of SiC-based patterned wafers in February at the Albany NanoTech Complex’s 150mm SiC line, with production coordinated with SUNY Poly’s Computer Chip Commercialization Center (Quad-C), located at its Utica campus where the SiC-based power chips will be packaged, a process that combines them with a housing that allows for interconnection with an application.