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When it comes to defects and contamination in the semiconductor manufacturing industry, most people tend to think of small, sub-nm defects at the transistor level. As important as those are, there are plenty of things that can go wrong and be seen at the macro level. Scratches, fingerprints, hot spots, spin defects, edge chips, poly haze, missing patterns, etc. are usually visible with the naked eye, perhaps aided by a green light or a microscope.

Fabs often do manual visual inspections, but it tends to be fairly random, only sampling a few wafers at a time. “You put some wafers on the screen, and you look sporadically at five, ten points on a few of the wafers,” notes Reiner Fenske, founder, CEO and president of Microtronic (Hawthorne, NY). “If you find something, typically it’s very difficult to feed that information forward. You might take a picture, but then where does that picture go?” It’s also difficult to compare defects, such as scratches, with previously seen defects. “How many scratches did you have last week? Does that scratch look like the one that you had last night?” Reiner asks.

An automated macro inspection tool – such as the newly released Microtronic EAGLEview 5, which will be running wafers at North Hall Booth #5467 at Semicon West this week — solves those problems, without requiring any recipes and quickly scanning every wafer in the cassette, noting and logging various defects. The EAGLEview 5 represents a big upgrade over the company’s previous offering. “There’s really a dramatic difference in terms of defect detection, defect resolution, defect sensitivity, and there’s no hit to throughput, so we’re still looking at 3,000 wafers a day, which is incredibly fast,” said Mike LaTorraca, Microtronic’s Chief Marketing Officer. Errol Akomer, Applications Director at Microtronic, adds that in addition to the higher resolution, it’s a much cleaner signal. “The signal-to- noise ratio is much better — there’s a 5X improvement in that as well,” he said. Internally developed software algorithms also results in less nuisance defects and increased defect detection.

With these new capabilities, LaTorraca said they’ve created a bridge between micro and macro, and manual and automated. “We can take manual microscope images and put them into the same software that runs on EagleView. We can start to integrate defect information and the actual defect images from the manual microscope world into our tool, and that gives the fab owners a much more unified approach, a better, more comprehensive view, to make better decisions,” he said.

EAGLEview 5 is equipped with advanced imaging technology, analytical software, robotics and a 4-cassette multi-size (100mm-300mm) wafer platform. EAGLEview ProcessGuard Client Software provides defect visualization, digital guard-banding, wafer randomization/slot positional analysis, together with integration with manual microscopes for fab-wide defect tracking and reporting.

Every wafer is automatically OCR read, imaged, 100% inspected and stored for any step throughout the manufacturing process providing a comprehensive, centralized record – or ‘waferbase’ – that is also compatible with the fab’s manual microscope inspection data providing a more integrated, wholistic view of both micro and macro defects.

EAGLEview 5 acts as a hub for defect management across the fab by integrating manual microscope inspection, high resolution EAGLEview wafer images. EAGLEview 5 replaces legacy manual/micro wafer inspection by automating and standardizing wafer inspection processes. Blindly sampling 5 sites on a wafer is no longer needed. The newly developed ProcessGuard microscope interface software records micro defect classifications. This coupled with on-board commonality analysis allows root cause to be determined for micro defects and breathes new life into existing microscope inspection strategies. EAGLEview was originally designed to be comparable to naked eye 1x green light inspection.   EAGLEview 5 shifts the line between a macro green light inspection and microscope inspection.

“You can put all the micro defects into our database in the same ways you did the macro, so you classify your macro defects and you classify all your micro defects,” Fenske explained. “Now you have a record of what, where, how many, and because we collect all the history of where the lot went to, which tools it went through, we can then use that information to do commonality studies to figure out which tool caused the problem. With the microscope, there hasn’t been that type of integration, so we can now take all of those legacy things everyone needs to use and actually give them a new life.”

What would a simple technique to remove thin layers from otherwise thick, rigid semiconductor crystals mean for the semiconductor industry? This concept has been actively explored for years, as integrated circuits made on thin layers hold promise for developments including improved thermal characteristics, lightweight stackability and a high degree of flexibility compared to conventionally thick substrates.

In a significant advance, a research group from IBM successfully applied their new “controlled spalling” layer transfer technique to gallium nitride (GaN) crystals, a prevalent semiconductor material, and created a pathway for producing many layers from a single substrate.

As they report in the Journal of Applied Physics, from AIP Publishing, controlled spalling can be used to produce thin layers from thick GaN crystals without causing crystalline damage. The technique also makes it possible to measure basic physical properties of the material system, like strain-induced optical effects and fracture toughness, which are otherwise difficult to measure.

The same 20-micron spalled GaN film, demonstrating the film's flexibility. Credit: Bedell/IBM Research

The same 20-micron spalled GaN film, demonstrating the film’s flexibility. Credit: Bedell/IBM Research

Single-crystal GaN wafers are extremely expensive, where just one 2-inch wafer can cost thousands of dollars, so having more layers means getting more value out of each wafer. Thinner layers also provide performance advantages for power electronics, since it offers lower electrical resistance and heat is easier to remove.

“Our approach to thin film removal is intriguing because it’s based on fracture,” said Stephen W. Bedell, research staff member at IBM Research and one of the paper’s authors. “First, we first deposit a nickel layer onto the surface of the material we want to remove. This nickel layer is under tensile strength — think drumhead. Then we simply roll a layer of tape onto the nickel, hold the substrate down so it can’t move, and then peel the tape off. When we do this, the stressed nickel layer creates a crack in the underlying material that goes down into the substrate and then travels parallel to the surface.”

Their method boils down to simply peeling off the tape, nickel layer and a thin layer of the substrate material stuck to the nickel.

“A good analogy of how remarkable this process is can be made with a pane of glass,” Bedell said. “We’re breaking the glass in the long direction, so instead of a bunch of broken glass shards, we’re left with two full sheets of glass. We can control how much of the surface is removed by adjusting the thickness of the nickel layer. Because the entire process is done at room temperature, we can even do this on finished circuits and devices, rendering them flexible.”

The group’s work is noteworthy for multiple reasons. For starters, it’s by far the simplest method of transferring thin layers from thick substrates. And it may well be the only layer transfer method that’s materially agnostic.

“We’ve already demonstrated the transfer of silicon, germanium, gallium arsenide, gallium nitride/sapphire, and even amorphous materials like glass, and it can be applied at nearly any time in the fabrication flow, from starting materials to partially or fully finished circuits,” Bedell said.

Turning a parlor trick into a reliable process, working to ensure that this approach would be a consistent technique for crack-free transfer, led to surprises along the way.

“The basic mechanism of substrate spalling fracture started out as a materials science problem,” he said. “It was known that metallic film deposition would often lead to cracking of the underlying substrate, which is considered a bad thing. But we found that this was a metastable phenomenon, meaning that we could deposit a thick enough layer to crack the substrate, but thin enough so that it didn’t crack on its own — it just needed a crack to get started.”

Their next discovery was how to make the crack initiation consistent and reliable. While there are many ways to generate a crack — laser, chemical etching, thermal, mechanical, etc. — it turns out that the simplest way, according to Bedell, is to terminate the thickness of the nickel layer very abruptly near the edge of the substrate.

“This creates a large stress discontinuity at the edge of the nickel film so that once the tape is applied, a small pull on the tape consistently initiates the crack in that region,” he said.

Though it may not be obvious, gallium nitride is a vital material to our everyday lives. It’s the underlying material used to fabricate blue, and now white, LEDs (for which the 2014 Nobel Prize in physics was awarded) as well as for high-power, high-voltage electronics. It may also prove useful for inherent biocompatibility, which when combined with control spalling may permit ultrathin bioelectronics or implantable sensors.

“Controlled spalling has already been used to create extremely lightweight, high-efficiency GaAs-based solar cells for aerospace applications and flexible state-of-the-art circuits,” Bedell said.

The group is now working with research partners to fabricate high-voltage GaN devices using this approach. “We’ve also had great interaction with many of the GaN technology leaders through the Department of Energy’s ARPA-E SWITCHES program and hope to use controlled spalling to enable novel devices through future partnerships,” Bedell said.

By Dave Lammers

Integrating data from various sensors in semiconductor fabs is a key focus in the industry now, and the sub-fab is an increasingly important part of the equation. As process steps become ever more sophisticated and expensive, keeping pumps and other sub-fab equipment running optimally involves integrating multiple pieces of data into useful information.

Paul Rawlings, president of the SEMI Service Division at Edwards, Ltd., said while the semiconductor industry has a history of analyzing tool data and relating it to end processes, more progress is needed in considering the entire fab as an ecosystem.

“The sub-fab equipment also has a bearing, not just in terms of how efficiently we are using data to manage the sub-fab efficiently, but also in terms of improving overall fab performance and yields,” Rawlings said.

Edwards is developing “a structured approach to the kinds of data that we have, and how we use it,” Rawlings said, including a database of best known methods (BKMs) which includes the optimum configurations for pumps, abatements and other systems.

Edwards currently is launching EdCentra, a fault detection and classification (FDC) software platform aimed at the sub-fab. It provides a comprehensive solution to vacuum security, to take one example, by combining equipment monitoring, data acquisition, and analysis of operational data.

EdCentra, Edwards Sub-Fab FDC platform, provides process-critical vacuum and abatement equipment information, complementing Fab-based platforms and supporting industry efforts to create integrated Fab data-management systems.

EdCentra, Edwards Sub-Fab FDC platform, provides process-critical vacuum and abatement equipment information, complementing Fab-based platforms and supporting industry efforts to create integrated Fab data-management systems.

Besides monitoring the performance of the equipment, the EdCentra sub-fab information management system has built-in predictive capabilities. And it complements another Edwards tools, which records service activities.

When a pump is taken back to an Edwards service center, it is stripped down and serviced. “Then we update all of that on to our central database on the lifetime and the performance of our equipment. We have an ecosystem there,” he said.

The company’s overall goal, Rawlings said, is to connect what have been “fairly separate systems,” maximizing up-times in part by comparing the performance of different tools in the same area.

By extending the data analysis ecosystem, Edwards can increase up-times and refine service scheduling. “The data is there. When we connect these systems, that’s where we get all of the benefits from the data. It’s no longer about taking data at individual points along the life cycle. It’s about connecting the data across the journey of the equipment and then looking for optimization, adjustments, and maybe upgrades on the equipment,” he said.

Engineers and data scientists throughout the semiconductor industry are developing more fab-level techniques, using multi-variate analysis of data coming off the tools, as well as other inputs.

For Edwards, that involves looking at data coming from pressure gauges, temperature sensors, the power spectrum, and, increasingly, the very useful information derived from vibration monitoring.

“What we are finding is that by looking at the combinations of data, that’s when things become really interesting. Rather than just relying on one or two points of data on the equipment, we’re starting to build up a library of different parameters. Then we are looking to see how we combine those to give us the most accurate predictions of tool lifetime,” he said.

Edwards is working closely with two fabs to develop data-sharing protocols that allow for optimum monitoring of the sub-fab equipment. “We are looking at it both from their point of view, and ours, discussing different ways of processing the data and the analysis of the performance of the equipment.”

Because of the huge amounts of data involved, Rawlings said “we only transmit data, if you like, that moves. It’s not worth sending data at 10+ Hertz when that particular parameter is not moving. It’s only worth sending that data when a change occurs.”

The work with customers is done within strict limits to ensure data security. “Clearly, you would never want to share any data that could give any indication of what customers do in their fabs and we go to great lengths to safeguard this” he said.

One encouraging sign is that, industry wide, cloud security is becoming more effective, reducing concerns about moving data to the cloud. “The way that end-user data is segregated, the built-in security, is resulting in a little bit more openness in terms of using this data,” Rawlings said.

That said, it is still a difficult area to work with customers. “I won’t mention names, but there are a few folks where we are engaged, so we can move to the next level of validation. I think it’s going to be an area of development over the next few years, as we really focus on the right parameters to measure to predict lifetimes.”

A lot of sub-fab equipment is affected by the processes, more than the basic mechanics of the equipment. It is fairly rare to have a bearing failure on a pump, for example. What is more likely is that the pump will have some process-related issues, such as corrosion or condensate build-up from materials in the fab.

“We spend a lot of time studying the process materials, temperature settings, and those kinds of things to extend equipment lifetimes, but there’s obviously always a limit to what can be achieved. What we are now doing is looking at how the different types of sensors that we have, both already on the equipment, and other ones that we’re developing, can give us the best combination, the best ways of predicting lifetimes. That’s an area that we’ll be working hard on over the next few years for our customers,” Rawlings said.

How low can we go?


July 11, 2017

By Ed Korczynski

In the advanced CMOS technology programs ongoing in the Belgium city of Leuven, imec works to extend the building-blocks of integrated circuits (IC). On the day before the opening of SEMICON West 2017, the invitation-only imec Technology Forum provided an update on the emerging opportunities in semiconductor technology and smart electronics systems. An Steegen, Executive VP Semiconductor Technology & Systems, provided the update on how small we can scale CMOS devices over the next 5-10 years. Taller finFETs will likely be used along with nano-wire FETs (NW-FET) by industry, and researchers see ways to cost-effectively combine both in future optimized System-on-Chips (SoC).

“Existing finFET technology can scale to the 5nm-node,” explained An Steegen at ITF 2017 in Antwerp, Belgium. “However, at the 3nm-node it looks like the nano-wire is comparable in performance to the finFET, but it has an additional advantage in that the nanowire is a better electro-statically controlled device so it enables gate-length scaling more than the finFET. So the contacted gate pitch (CGP) of a nano-wire can scale further than a finFET, because below ~40 nm CGP a finFET loses electro-static control which a nano-wire does not.”

While it is given that a nanowire has better electro-static control compared to a finFET, the basic trade-off is that of reduced drive current. The Figure shows that IMEC sees the possibility of System-Technology Co-Optimization (STCO) of future system-on-chip (SoC) designs using hybrid semiconductor technologies. imec’s basic process flow for NW-FETs starts with forming fins and so could be relatively easily integrated with finFETs for co-integrated hybrid CMOS.

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

“Today, this SoC is processed in one technology which means it’s sub-optimal for certain blocks on the SoC,” explained Steegen. “So imagine a future where you can choose the preferred technology for each block. I would choose finFETs for those blocks that need drive current, while I would choose nano-wire-FETs for those blocks that need more density and lower power. I would for example choose a magnetic RAM to replace my cache memory. I can optimize each sub-block for a preferred technology. Now I can do more, like sprinkle in low-energy devices like tunnel-FETs or spin-devices or 2D-materials as low-energy switches.”

Super-vias and Rutherails

Design-Technology Co-Optimization (DTCO) is imec’s term for new interconnect technologies to allow for simpler or more-compact designs. IDTCO process-scaling boosters are needed to stay with the pace of aggressive design rule targets. “We’re working on super-vias that connect more than one metal to the other and can jump a number of levels, and buried rails to support finFETs in standard-cell libraries,” explained Steegen during ITF2017.

Super-vias could be cobalt plugs that connect more than two metal levels within on-chip multi-level interconnects. The cobalt plugs would be nominally 20nm diameter and 105nm deep, and connected to a dual-damscene upper metal line. Low-k dielectric of k=2.55 uses thin silicon carbon nitride (SiCN) for definition between the damascene levels.

Ruthenium rails (Rutherails) would be buried in a front-end dielectric layer to provide electrical contacts below finFETs for 42nm CGP and 21nm MP needed for imec 3nm-Node (I3N) devices. Ruthenium rails 30nm deep and 10nm wide do not need complex barrier layers and should provide sufficient current flow for either finFETs or NW-FETs.

imec is also working on materials R&D to extend the performance of 3D-NAND. Steegen said,

“At imec we are working on improving the performance of that Flash device by introducing high-mobility channels, also by engineering the dielectric trapping layer with a barrier that can help improve the erase window and also the retention.”

A new low-temperature solution printing technique allows fabrication of high-efficiency perovskite solar cells with large crystals intended to minimize current-robbing grain boundaries. The meniscus-assisted solution printing (MASP) technique boosts power conversion efficiencies to nearly 20 percent by controlling crystal size and orientation.

The process, which uses parallel plates to create a meniscus of ink containing the metal halide perovskite precursors, could be scaled up to rapidly generate large areas of dense crystalline film on a variety of substrates, including flexible polymers. Operating parameters for the fabrication process were chosen by using a detailed kinetics study of perovskite crystals observed throughout their formation and growth cycle.

“We used a meniscus-assisted solution printing technique at low temperature to craft high quality perovskite films with much improved optoelectronic performance,” said Zhiqun Lin, a professor in the School of Materials Science and Engineering at the Georgia Institute of Technology. “We began by developing a detailed understanding of crystal growth kinetics that allowed us to know how the preparative parameters should be tuned to optimize fabrication of the films.”

The new technique is reported July 7 in the journal Nature Communications. The research has been supported by the Air Force Office of Scientific Research (AFOSR) and the National Science Foundation (NSF).

Georgia Tech Research Scientist Ming He adjusts the equipment for the meniscus-assisted solution printing (MASP) technique used to fabricate perovskite films for solar cells. (Credit: Rob Felt, Georgia Tech)

Georgia Tech Research Scientist Ming He adjusts the equipment for the meniscus-assisted solution printing (MASP) technique used to fabricate perovskite films for solar cells. (Credit: Rob Felt, Georgia Tech)

Perovskites offer an attractive alternative to traditional materials for capturing electricity from light, but existing fabrication techniques typically produce small crystalline grains whose boundaries can trap the electrons produced when photons strike the materials. Existing production techniques for preparing large-grained perovskite films typically require higher temperatures, which is not favorable for polymer materials used as substrates – which could help lower the fabrication costs and enable flexible perovskite solar cells.

So Lin, Research Scientist Ming He and colleagues decided to try a new approach that relies on capillary action to draw perovskite ink into a meniscus formed between two nearly parallel plates approximately 300 microns apart. The bottom plate moves continuously, allowing solvent to evaporate at the meniscus edge to form crystalline perovskite. As the crystals form, fresh ink is drawn into the meniscus using the same physical process that forms a coffee ring on an absorbent surface such as paper.

“Because solvent evaporation triggers the transport of precursors from the inside to the outside, perovskite precursors accumulate at the edge of the meniscus and form a saturated phase,” Lin explained. “This saturated phase leads to the nucleation and growth of crystals. Over a large area, we see a flat and uniform film having high crystallinity and dense growth of large crystals.”

To establish the optimal rate for moving the plates, the distance between plates and the temperature applied to the lower plate, the researchers studied the growth of perovskite crystals during MASP. Using movies taken through an optical microscope to monitor the grains, they discovered that the crystals first grow at a quadratic rate, but slow to a linear rate when they began to impinge on their neighbors.

“When the crystals run into their neighbors, that affects their growth,” noted He. “We found that all of the grains we studied followed similar growth dynamics and grew into a continuous film on the substrate.”

The MASP process generates relatively large crystals – 20 to 80 microns in diameter – that cover the substrate surface. Having a dense structure with fewer crystals minimizes the gaps that can interrupt the current flow, and reduces the number of boundaries that can trap electrons and holes and allow them to recombine.

Using films produced with the MASP process, the researchers have built solar cells that have power conversion efficiencies averaging 18 percent – with some as high as 20 percent. The cells have been tested with more than 100 hours of operation without encapsulation. “The stability of our MASP film is improved because of the high quality of the crystals,” Lin said.

Doctor-blading is one of the conventional perovskite fabrication techniques in which higher temperatures are used to evaporate the solvent. Lin and his colleagues heated their substrate to only about 60 degrees Celsius, which would be potentially compatible with polymer substrate materials.

So far, the researchers have produced centimeter-scale samples, but they believe the process could be scaled up and applied to flexible substrates, potentially facilitating roll-to-roll continuous processing of the perovskite materials. That could help lower the cost of producing solar cells and other optoelectronic devices.

“The meniscus-assisted solution printing technique would have advantages for flexible solar cells and other applications requiring a low-temperature continuous fabrication process,” Lin added. “We expect the process could be scaled up to produce high throughput, large-scale perovskite films.”

Among the next steps are fabricating the films on polymer substrates, and evaluating other unique properties (e.g., thermal and piezotronic) of the material.

At its annual Imec Technology Forum USA in San Francisco, imec today presented an electrically functional solution for the 5nm back-end-of-line (BEOL). The solution is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm.  Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node,” said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.

Twelve years of continuous operation. That amounts to over 18.9 billion rotations. In mid-January 2017, a Busch LLC COBRA BC dry screw vacuum pump passed this milestone in a semiconductor foundry in Germany.

The COBRA BC in question has been in continuous operation at the GlobalFoundries production site in Dresden, Germany, since 2005 and is the longest-operating COBRA BC at the site, which is known as Fab 1. Fab 1 in Dresden was the world’s first fab to manufacture microchips with copper wiring in industrial quantities – a technology that is now the basis for semiconductor production throughout the world.

A total of 203 COBRA BC 0100 dry screw vacuum pumps are installed at the Dresden site, which produces 300mm wafers for the semiconductor industry. 31 of these COBRA BCs have been in continuous operation for over 10 years, and 15 of the COBRA BCs have passed the milestone of 100,000 operating hours (over 11 years of operation). Generally, continuous operation over five or six years is the industry expectation in load-lock applications.

COBRA BC vacuum pumps are predominantly used in the load-lock applications of epitaxy and physical vapor deposition (PVD) processes, as well as in other contamination-free processes for wafer handling and metrics to assure the quality of the lithography process.

The COBRA BC 0100 is a dry screw vacuum pump within the proven COBRA BC series portfolio that is a compact load-lock solution with additional process capabilities for the most demanding solar, flat panel and semiconductor applications. It has excellent powder handling capabilities as a result of its unique screw pump design.

The COBRA BC series is also available in a COBRA BC Premium Efficiency class with a reduced energy footprint that results in lower electrical energy use of up to 40%. The Premium Efficiency class is based on the proven technology platform of the COBRA BC.

Busch Vacuum Pumps and Systems maintains a service team in Dresden, which consists of nine service technicians and one team leader in a 24/7 shift system, ensuring very high system availability of the nearly 900 installed Busch vacuum pumps. Furthermore, the service team maintains the waste gas abatement systems.

GlobalFoundries is among the top semiconductor companies in the world and manufactures at its Dresden fab 40nm to 22nm nodes. The Dresden fab is Europe’s largest fab for the production of microchips.

A new type of semiconductor may be coming to a high-definition display near you. Scientists at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) have shown that a class of semiconductor called halide perovskites is capable of emitting multiple, bright colors from a single nanowire at resolutions as small as 500 nanometers.

A 2-D plate showing alternating cesium lead chloride (blue) and cesium lead bromide (green) segments. Credit: Letian Dou/Berkeley Lab and Connor G. Bischak/UC Berkeley

A 2-D plate showing alternating cesium lead chloride (blue) and cesium lead bromide (green) segments. Credit: Letian Dou/Berkeley Lab and Connor G. Bischak/UC Berkeley

The findings, published online this week in the early edition of the Proceedings of the National Academy of Sciences, represent a clear challenge to quantum dot displays that rely upon traditional semiconductor nanocrystals to emit light. It could also influence the development of new applications in optoelectronics, photovoltaics, nanoscopic lasers, and ultrasensitive photodetectors, among others.

The researchers used electron beam lithography to fabricate halide perovskite nanowire heterojunctions, the junction of two different semiconductors. In device applications, heterojunctions determine the energy level and bandgap characteristics, and are therefore considered a key building block of modern electronics and photovoltaics.

The researchers pointed out that the lattice in halide perovskites is held together by ionic instead of covalent bonds. In ionic bonds, atoms of opposite charges are attracted to each other and transfer electrons to each other. Covalent bonds, in contrast, occur when atoms share their electrons with each other.

“With inorganic halide perovskite, we can easily swap the anions in the ionic bonds while maintaining the single crystalline nature of the materials,” said study principal investigator Peidong Yang, senior faculty scientist at Berkeley Lab’s Materials Sciences Division. “This allows us to easily reconfigure the structure and composition of the material. That’s why halide perovskites are considered soft lattice semiconductors. Covalent bonds, in contrast, are relatively robust and require more energy to change. Our study basically showed that we can pretty much change the composition of any segment of this soft semiconductor.”

In this case, the researchers tested cesium lead halide perovskite, and then they used a common nanofabrication technique combined with anion exchange chemistry to swap out the halide ions to create cesium lead iodide, bromide, and chloride perovskites.

Each variation resulted in a different color emitted. Moreover, the researchers showed that multiple heterojunctions could be engineered on a single nanowire. They were able to achieve a pixel size down to 500 nanometers, and they determined that the color of the material was tunable throughout the entire range of visible light.

The researchers said that the chemical solution-processing technique used to treat this class of soft, ionic-bonded semiconductors is far simpler than methods used to manufacture traditional colloidal semiconductors.

“For conventional semiconductors, fabricating the junction is quite complicated and expensive,” said study co-lead author Letian Dou, who conducted the work as a postdoctoral fellow in Yang’s lab. “High temperatures and vacuum conditions are usually involved to control the materials’ growth and doping. Precisely controlling the materials composition and property is also challenging because conventional semiconductors are ‘hard’ due to strong covalent bonding.”

To swap the anions in a soft semiconductor, the material is soaked in a special chemical solution at room temperature.

“It’s a simple process, and it is very easy to scale up,” said Yang, who is also a professor of chemistry at UC Berkeley. “You don’t need to spend long hours in a clean room, and you don’t need high temperatures.”

The researchers are continuing to improve the resolution of these soft semiconductors, and are working to integrate them into an electric circuit.

Two European research institutes today announced their new collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.

Leti, a research institute of CEA Tech in Grenoble, France, and the Berlin-based Fraunhofer Group for Microelectronics, Europe’s largest R&D provider of smart systems, will initially focus on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in the Internet of Things, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries.

The agreement was signed today by Leti CEO Marie Semaria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner during Leti Innovation Days, which are marking Leti’s 50th anniversary.

“The ability to, one, develop key enabling technologies that overcome the formidable technical challenges that our leading technology companies will face, and, two, transfer them quickly to industry, is an essential focus for research institutes and industrials in France and Germany,” Semaria said. “Building on our previous, successful collaborations, Leti and the Fraunhofer Group for Microelectronics will bring our complementary strengths to the task of keeping France and Germany’s microelectronics industries in the forefront – and offer our innovations across Europe.”

“Micro-/nanoelectronics and smart systems are key enabling technologies for the economic success of Europe, especially in France and Germany. Thus, Europe can no longer afford to scatter its research competences. For the benefit of industry, joining forces will become more and more important, not only for industry but also for RTOs,” Lakner explained. “The new cooperation agreement will be the starting point for a strategic research cooperation of the two countries in order to jointly support the upcoming EC initiative, Important Project of Common European Interest (IPCEI), on micro- and nanoelectronics.”

Specific R&D projects that the collaboration will focus on include:

o    Silicon-based technologies for next-generation CMOS processes and products, including design, simulation, unit process and material development as well as production techniques

o    Extended More than Moore technologies for sensing and communication applications

o    Advanced-packaging technologies.

The second phase of the collaboration may be expanded with additional academic partners and other countries, as needed.

The SEMI Foundation and the Micron Technology Foundation announced their partnership this week to deliver the 213th SEMI High Tech U (HTU) program which kicks off in earnest today at Micron’s facilities in Milpitas. Forty students from local high schools are attending the three-day science, technology, engineering and math (STEM) program.

The nonprofit SEMI Foundation has been holding its flagship program, SEMI High Tech U, at industry sites around the world since 2001 to emphasize the importance of STEM skills and inspire young people to pursue careers in high technology fields. HTU allows students to meet engineers and volunteer instructors from industry in a face-to-face setting with tech-related, hands-on activities such as etching wafers, making circuits, coding and professional interviews training.

“We are delighted to partner with Micron in our common goal to motivate the next generation of innovators,” said Ajit Manocha, president and CEO of SEMI and the SEMI Foundation. “HighTech U has reached more than 6,000 students in eleven states as well as nine countries internationally. We are pleased to join with Micron to serve students here in Silicon Valley.”

“Micron Technology Foundation has been inspiring learners of all ages and supporting early exposure to technology through our own Micron Chip Camp for 17 years,” said Sanjay Mehrotra, Micron president and CEO. “SEMI High Tech U is complementary to these efforts and we are proud to partner with the SEMI Foundation to deliver our first joint program focused on high school students to promote careers in STEM-related high tech industries such as semiconductor manufacturing.”

 

Ajit Manocha, president and CEO of SEMI, and Sanjay Mehrotra, president and CEO of Micron, with SEMI High Tech U students.

Ajit Manocha, president and CEO of SEMI, and Sanjay Mehrotra, president and CEO of Micron, with SEMI High Tech U students.

Manocha and Mehrotra jointly welcomed participating students to the SEMI HTU program and shared highlights of their professional experience during a pre-event kick-off at Micron in Milpitas on Monday, June 26. Students will spend Tuesday at Micron working on STEM focused, hands-on activities. Micron team members will assist in teaching the modules, offering students a connection to semiconductor professionals. On Wednesday, the program convenes at San Jose State University where students will learn about etching wafers and tour the SJSU campus. The program will culminate Thursday at Micron with critical thinking and soft skills development activities along with mock interviews. Students will “graduate” from SEMI High Tech U on Thursday afternoon at Micron.