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EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced it is demonstrating optimized pre-processing solutions for the implementation of plasma dicing for advanced semiconductor packaging applications. EVG’s latest products and process development services support this emerging semiconductor back-end fabrication process by protecting bumps and other topography with highly uniform resist layer and lithographic patterning of narrow dicing streets. By combining EVG’s systems with third-party dry plasma dicing systems, customers can obtain a complete solution that will enable highly parallel, high-throughput, debris-free die singulation without risking bump reliability or impacting structured surfaces. EVG’s offerings address the critical pre-processing requirements for mid-end-of-line (MEOL) and back-end-of-line (BEOL) processing of MEMS, power devices, RFID components, image sensors, logic and memory.

Thinner and smaller semiconductor chips are required to support the latest generation of mobile and wearable devices as well as to facilitate the Internet of Things (IoT). Plasma dicing offers numerous advantages for die singulation, such as reducing dicing street widths, providing flexible chip layouts as well as eliminating sidewall damage, chipping and wafer breakage. However, plasma dicing also brings new pre-process requirements, including the need for protecting top-side or bottom-side structures prior to singulation, conformal coating of severe topography features, thick resists for deep etching, and lithography to open up the dicing lanes.

EVG’s high-quality, low cost-of-ownership resist processing and lithography systems address all of the pre-processing steps needed for advanced plasma dicing, including resist coating and development, as well as mask alignment lithography:

  • EVG’s proprietary OmniSpray technology enables uniform coating of high-topography surfaces and bumps across the wafer—where traditional spin-coating techniques are limited—with sufficient thickness to fully protect bumps during plasma processing while providing the base for lithographic patterning of dicing streets.
  • EVG’s mask aligners provide optimal patterning quality with spray coating resists, including excellent depth of focus, high uniformity over topography, high throughput, and high resolution in deep cavities and trenches (down to 10µm even for large proximity gaps wider than 100µm), making them ideally suited to expose and open up the dicing lines.
  • The pre-processing line is completed with EVG’s high-throughput development systems.
  • All systems can be provided in semi-automated and fully automated configurations, and are fully compatible with film-frame handling, making them ideally suited for die singulation in advanced packaging.

“The semiconductor industry is increasingly driving device performance through vertical stacking on thinner substrates. This trend is leading to greater demand not only for new wafer dicing technologies, but also for the supporting pre-processing equipment such as our coat, develop and mask alignment systems,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “We are pleased to offer demonstrations of our complete line of R&D and volume-production pre-processing systems for plasma dicing at our demo labs in Austria, the U.S. and Japan, where customers can witness the yield and cost-of-ownership benefits of this powerful end-to-end wafer dicing solution for their custom advanced packaging needs.”

EVG will also showcase its latest suite of lithography and resist processing solutions for advanced packaging applications at SEMICON West, to be held July 11-13 at the Moscone Convention Center in San Francisco, Calif. Attendees interested in learning more can visit EVG at Booth #7211 in the West Hall.

Synopsys, Inc. (Nasdaq: SNPS) today announced the enablement of the Synopsys Design Platform and DesignWare Embedded Memory IP on GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET process technology. Synopsys and GF collaboration on the new process addressed several new challenges specific to the 7LP process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF’s 14nm FinFET process. Designers of premium mobile processors, cloud servers and networking infrastructure can take advantage of these benefits by confidently deploying the silicon-proven Synopsys Design Platform and Embedded Memory IP.

“GF’s leading-performance 7nm platform is exceeding initial performance targets and is now ready for customer designs,” said Alain Mutricy, senior vice president of product management at GF. “GF and Synopsys have collaborated to provide designers with tools and methodology that fully leverage the power and highest absolute performance of our 7LP technology, and will allow customers to create innovative products across a range of high-performance applications.”

GF and Synopsys worked together to ensure support of the comprehensive suite of Synopsys Design Platform digital implementation solutions for GF 7LP, including Design Compiler Graphical synthesis, IC Compiler II place-and-route, IC Validator physical verification, PrimeTime static timing analysis and StarRC extraction. To enable designers to achieve the full benefit of the GF 7LP process, the Synopsys tools employ advanced techniques including color track generation, pin color alignment checking and legalization, mixing of single-height and double-height physical boundary cells, power grid alignment to track and color-track aware routing.

The two companies are also collaborating on the development of Synopsys DesignWare Memory Compilers to deliver leading performance, power, area and yield for GF’s 7nm process technology. This joint effort consists of optimizing the GF 7LP process design rules and line patterns to achieve the best results. Early versions of the memory compilers will be on the GF 7LP process qualification vehicle.

“Synopsys and GF have always worked closely to address our customers’ needs, including collaborations on FDSOI and 14nm FinFET processes,” said Michael Jackson, corporate vice president of marketing and business development in the Design Group at Synopsys. “With today’s announcement, we are ready to enable designs on the 7LP process. We will continue to collaborate and ensure that our customers can get superior quality of results and faster time to results by using the Synopsys Design Platform and DesignWare Embedded Memory IP.”

MagnaChip Semiconductor Corporation (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed-signal semiconductor platform solutions for communications, IoT, consumer, industrial and automotive applications, announced today it now offers 0.13 micron BCD process technology integrated with high-density embedded Flash. This BCD process offers 40V power LDMOS and delivers 64K Bytes flash memory, making it suitable for programmable PMIC, wireless power chargers and USB-C power-delivery IC products.

Increasingly, products such as programmable PMICs, wireless power chargers and USB-C power-delivery ICs require embedded non-volatile memory and other functions to be integrated onto a single Power IC.  Aside from embedded non-volatile memory, which is used for program code storage, these products require power LDMOS, which is well suited for high-power requirements. The inclusion of embedded FLASH is crucial in order to minimize chip size when high non-volatile memory density is required.  For IoT and automotive applications, this BCD process provides 1.5V and 5V CMOS devices with a very low leakage current level that enables low-power consumption.  Furthermore, this new BCD process has various option devices for Hall sensors, varactors, inductors, and RF CMOS devices that are useful for highly integrated IC solutions, which yield smaller system size and lower system cost.

MagnaChip’s 30V high voltage with embedded Flash process for touch IC is already in volume production, and the new BCD with embedded Flash 40V process announced today is now being adopted by foundry customers. Embedded Flash IP, designed and verified by MagnaChip, reduces foundry customers’ design time by providing proven intellectual property (IP) with a range of diverse memory densities. MagnaChip also verifies and provides key analog intellectual property, such as ADC (Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), LDO (Low Dropout Regulator), POR (Power On Reset), PLL (Phase Locked Loop), OSC (Oscillator), which reduces design time.

YJ Kim, Chief Executive Officer of MagnaChip, commented, “The combination of analog-based BCD and non-volatile memory is ideal for producing power management solutions and power ICs used in smartphones, IoT devices and for USB-C applications.” Mr. Kim added, “Our goal is to continue to develop specialized process technologies that meet the increasing needs for the application-specific solutions of our foundry customers.”

The problem is a fundamental incompatibility in communication styles.

That conclusion might crop up during divorce proceedings, or describe a diplomatic row. But scientists designing polymers that can bridge the biological and electronic divide must also deal with incompatible messaging styles. Electronics rely on racing streams of electrons, but the same is not true for our brains.

“Most of our technology relies on electronic currents, but biology transduces signals with ions, which are charged atoms or molecules,” said David Ginger, professor of chemistry at the University of Washington and chief scientist at the UW’s Clean Energy Institute. “If you want to interface electronics and biology, you need a material that effectively communicates across those two realms.”

Lead author Rajiv Giridharagopal, left, and co-author Lucas Flagg, right, standing next to an atomic force microscope. Credit: Dane deQuilettes

Lead author Rajiv Giridharagopal, left, and co-author Lucas Flagg, right, standing next to an atomic force microscope. Credit: Dane deQuilettes

Ginger is lead author of a paper published online June 19 in Nature Materials in which UW researchers directly measured a thin film made of a single type of conjugated polymer — a conducting plastic — as it interacted with ions and electrons. They show how variations in the polymer layout yielded rigid and non-rigid regions of the film, and that these regions could accommodate electrons or ions – but not both equally. The softer, non-rigid areas were poor electron conductors but could subtly swell to take in ions, while the opposite was true for rigid regions.

Organic semiconducting polymers are complex matrices made from repeating units of a carbon-rich molecule. An organic polymer that can accommodate both types of conduction — ion and electrons — is the key to creating new biosensors, flexible bioelectronic implants and better batteries. But differences in size and behavior between tiny electrons and bulky ions have made this no easy task. Their results demonstrate how critical the polymer synthesis and layout process is to the film’s electronic and ionic conductance properties. Their findings may even point the way forward in creating polymer devices that can balance the demands of electronic transport and ion transport.

“We now understand the design principles to make polymers that can transport both ions and electrons more effectively,” said Ginger. “We even demonstrate by microscopy how to see the locations in these soft polymer films where the ions are transporting effectively and where they aren’t.”

Ginger’s team measured the physical and electrochemical properties of a film made out of poly(3-hexylthiophene), or P3HT, which is a relatively common organic semiconductor material. Lead author Rajiv Giridharagopal, a research scientist in the UW Department of Chemistry, probed the P3HT film’s electrochemical properties in part by borrowing a technique originally developed to measure electrodes in lithium-ion batteries.

The approach, electrochemical strain microscopy, uses a needle-like probe suspended by a mechanical arm to measure changes in the physical size of an object with atomic-level precision. Giridharagopal discovered that, when a P3HT film was placed in an ion solution, certain regions of the film could subtly swell to let ions flow into the film.

“This was an almost imperceptible swelling — just 1 percent of the film’s total thickness,” said Giridharagopal. “And using other methods, we discovered that the regions of the film that could swell to accommodate ion entry also had a less rigid structure and polymer arrangement.”

More rigid and crystalline regions of the film could not swell to let in ions. But the rigid areas were ideal patches for conducting electrons.

Ginger and his team wanted to confirm that structural variations in the polymer were the cause of these variations in electrochemical properties of the film. Co-author Christine Luscombe, a UW associate professor of materials science and engineering and member of the Clean Energy Institute, and her team made new P3HT films that had different levels of rigidity based on variations in polymer arrangement.

By subjecting these new films to the same array of tests, Giridharagopal showed a clear correlation between polymer arrangement and electrochemical properties. The less rigid and more amorphous polymer layouts yielded films that could swell to let in ions, but were poor conductors of electrons. More crystalline polymer arrangements yielded more rigid films that could easily conduct electrons. These measurements demonstrate for the first time that small structural differences in how organic polymers are processed and assembled can have major consequences for how the film accommodates ions or electrons. It may also mean that this tradeoff between the needs of ion and electrons is unavoidable. But these results give Ginger hope that another solution is possible.

“The implication of these findings is that you could conceivably embed a crystalline material — which could transport electrons — within a material that is more amorphous and could transport ions,” said Ginger. “Imagine that you could harness the best of both worlds, so that you could have a material that is able to effectively transport electrons and swell with ion uptake — and then couple the two with one another.”

New research into the largely unstudied area of heterostructural alloys could lead to greater materials control and in turn better semiconductors, advances in nanotechnology for pharmaceuticals and improved metallic glasses for industrial applications.

Heterostructural alloys are blends of compounds made from materials that don’t share the same atom arrangement. Conventional alloys are isostructural, meaning the compounds they consist of, known as the end members, have the same crystal structure.

“Alloys are all around us,” said study co-author Janet Tate, a physicist at Oregon State University. “An example of an istostructural alloy is an LED; you have a semiconductor like aluminum gallium arsenide, dope it with a particular material and make it emit light, and change the color of the light by changing the relative concentration of aluminum and gallium.”

Structure and composition are the two means of controlling the behavior of materials, Tate said. Combining materials gives the alloy properties between those that the end members have on their own.

“If two materials have different structures, as you mix them together it’s not so clear which structure will win,” said Tate, the Dr. Russ and Dolores Gorman Faculty Scholar in the College of Science. “The two together want to take different structures, and so this is an extra way of tuning an alloy’s properties, a structural way. The transition between different crystal structures provides an additional degree of control.”

Tate and collaborators from around the world, including the National Renewable Energy Laboratory, published their findings in Science Advances.

“This is a very interesting piece of materials science that represents a somewhat uncharted area and it may be the beginning something quite important,” Tate said. “The heterostructural alloy concept had been known before, but it’s different enough that it hadn’t really been explored in a detailed phase diagram – the mapping of exactly how, at what temperature and what concentration, it goes from one structure to another.

“This paper is primarily the NERL’s theoretical work being supported by other collaborators’ experimental work,” Tate said. “Our involvement at OSU was in making one of the kinds of heterostructural alloys used in the research, the combination of tin sulfide and calcium sulfide.”

Tate and graduate student Bethany Matthews have been focusing on the semiconductor application.

“Tin sulfide is a solar cell absorber, and the addition of calcium sulfide changes the structure and therefore the electrical properties necessary for an absorber,” Tate said “Combining tin sulfide with calcium sulfide makes it more isotropic – properties being the same regardless of orientation – and that’s usually a useful thing in devices.”

In this study, thin-film synthesis confirmed the metastable phases of the alloys that had been predicted theoretically.

“Many alloys are metastable, not stable – if you gave them enough time and temperature, they’d eventually separate,” Tate said. “The way we make them, with pulsed laser deposition, we allow the unstable structure to form, then suppress the decomposition pathways that would allow them to separate; we don’t give them enough time to equilibrate.”

Metastable materials – those that are thermodynamically stable provided they are not subjected to large disturbances – are in general understudied, Tate said.

“When theorists predict properties, they tend to work with materials that are stable,” she said. “In general the stable compounds are easier to attack. The idea here with heterostructural alloys is that they give us a new handle, a new knob to turn to change and control materials’ properties.”

Researchers from MIPT’s Center of Shared Research Facilities have found a way to control oxygen concentration in tantalum oxide films produced by atomic layer deposition. These thin films could be the basis for creating new forms of nonvolatile memory. The paper was published in the journal ACS Applied Materials & Interfaces, which has an impact factor of 7.14.

Want nonvolatile memory that’s fast as RAM and has the capacity of flash?

Because data storage and processing solutions are so central to modern technology, many research teams and companies are pursuing new types of computer memory. One of their major goals is to develop universal memory — a storage medium that would combine the high speed of RAM with nonvolatility of a flash drive.

A promising technology for creating such a device is resistive switching memory, or ReRAM. It works by changing the resistance across a memory cell as a result of applied voltage. Since each cell has a high- and a low-resistance state, it can be used to store information, e.g., in the form of zeros and ones.

A ReRAM cell can be realized as a metal-dielectric-metal structure. Oxides of transition metals such as hafnium and tantalum have proved useful as the dielectric component of this layered structure. Applying voltage to a memory cell that is based on these materials causes oxygen migration, changing its resistance. This makes the distribution of oxygen concentration in the oxide film a crucial parameter determining the functional properties of the memory cell.

However, despite significant advances in ReRAM development, flash memory shows no sign of losing ground. The reason for this is that flash memory allows for three-dimensional memory cell stacking, which enables a much greater storage density. In contrast to this, oxygen-deficient film deposition techniques normally used in ReRAM design are not applicable to functional 3-D architectures.

That’s where atomic layer deposition comes in

In a bid to find an alternative technique, MIPT researchers turned to atomic layer deposition, a chemical process by which thin films can be produced on the surface of a material. During the last decade, ALD has become increasingly widespread, with numerous applications in nanoelectronics, optics, and the biomedical industry. There are two major advantages to atomic layer deposition. The first one is the unprecedented control over film thickness: It is possible to deposit films that are several nanometers thick with an error of a fraction of a nanometer. The other advantage is that ALD enables conformal coating of 3-D structures, which is problematic for most of the currently used nanofilm deposition techniques.

In an ALD process, a substrate is sequentially exposed to two chemicals that are known as the precursor and the reactant. It is the chemical reaction between these two substances that produces a coating layer. In addition to the element used in the coating, precursors contain other compounds — e.g., of carbon or chlorine — called ligands. They facilitate the reaction but, in an ideal ALD process, have to be completely removed from the resulting film once the interaction with the other chemical (reactant) has occurred. It is vital to choose the right substances for use in atomic layer deposition. Although it proves difficult to deposit oxide films with variable oxygen concentration by ALD, they are essential for ReRAM.

“The hardest part in depositing oxygen-deficient films was finding the right reactants that would make it possible to both eliminate the ligands contained in the metallic precursor and control oxygen content in the resulting coating,” says Andrey Markeev, who holds a PhD in physics and mathematics and is a leading researcher at MIPT. “We achieved this by using a tantalum precursor, which by itself contains oxygen, and a reactant in the form of plasma-activated hydrogen.” Confirming the experimental findings turned out to be a challenge in itself. As soon as the experimental sample is removed from the vacuum chamber, which houses it during ALD, and exposed to the atmosphere, this causes modifications in the top layer of the dielectric, making it impossible to detect oxygen deficiency using analytic techniques such as electron spectroscopy, which target the surface of the sample.

“In this study, we needed not just to obtain the films containing different amounts of oxygen but also to confirm this experimentally,” says Konstantin Egorov, a PhD student at MIPT. “To do this, our team worked with a unique experimental cluster, which allowed us to grow films and study them without breaking the vacuum.”

A new type of scattered light measurement method will be presented, capable of measuring the full wafer surface of a 300 mm wafer in less than 30 seconds. Besides the roughness, the sensor simultaneously measures warpage, waviness and defects.

BY R. BRODMANN, B. BRODMANN, K. KONOVALENKO, and C. WIEHR, OptoSurf GmbH CHING-HSIEN HUANG, YA-LENG CHEN, Amkor Technology, Inc.

The trend towards very small and high-density electronics requires advanced processes to meet the specifications of thickness and thermal properties of the devices. This means that the processed silicon wafers have to be thinned from their original thickness of more than 700 μm down to 50 μm or less. The most common and relative low cost thinning method is back grinding by means of mechanical removal of the residual silicon. The wafer is fixed on a porous vacuum chuck with the IC (integrated circuit) side down. The rotation axis of the grinding wheel is positioned off-axis to the rotation axis of the wafer (distance is the radius of the wafer). The chuck has a slightly conical shape which deforms the wafer with a very little tilt to ensure that the grinding wheel only contacts half of the wafer during the grinding process. Due to the rotation of the chuck and simultaneously rotation of the grinding wheel a typical spiral pattern of scratches on the wafer surface is generated.

Depending on the grit size of the grinding wheel and the machining parameters as rotation speed and feed rate, this mechanical impact is responsible for the roughness, stress and induced subsurface damage. Therefore, a modern wafer grinding machine begins with a coarse grinding wheel to get a fast removal of the silicon and at the end follows a fine grinding process step with small grit size grinding wheel. This final process is absolute necessary when thinning down to 50 μm in order to minimize subsurface damage and stress. The roughness of the surface should be often in the range of Ra <10 nm or even 1 nm which is a challenge for mechanical grinding machines. Is the roughness too high or not uniformly distributed on the wafer surface, the later process steps as wire bonding, flip chip assembling, molding and testing can damage the thin chip through breakage. Besides a low surface roughness, the fracture strength of the die after dicing also depends on the orientation of the grinding marks. The correlation of die strength with roughness and surface texture is described in Ref. 1 and 2.

The interaction of the grinding wheel with its large number of single cutting edges, undergoing non-uniform wear, and the silicon surface, in particular when applying the fine grinding procedure is a rather complex process. Therefore, it is not possible to predict the quality of the entire wafer surface after grinding by means of a few small area roughness measurements with an AFM, a WLI or CFM, which is the standard today. Typically, the assessed area of one single measurement is 20 μm x 20 μm in case of an AFM and 160 μm x 160 μm with a CFM or WLI. Each measurement takes about 20 s-30 s and requires anti-vibration equipment to avoid influence from environmental mechanical noise.

In order to get information of the entire wafer surface, much faster and more robust measurement techniques are necessary. Scattered light measurement is the only method which can achieve these requirements. In the present paper, results of a new measurement machine (WaferMaster 300) are discussed which uses a scattered light sensor [4] to measure the roughness of a full 300 mm wafer surface in less than 30 s. Due to a special design of the sensor the WaferMaster can measure in addition the warpage, waviness and defects.

Measurement principle and surface characterization

Using scattered light to measure surface defects and roughness is already well known for CMP polished bare wafers, pattered wafer, hard disks, mirror surfaces and high quality fine machined automotive parts. The new type of scattered light sensor to measure back- grinding wafer is shown in FIGURE 1.

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The light source (1) illuminates nearly perpendicular the wafer surface with a 670 nm red LED spot of 0.9 mm spot size (2). This is the standard modus for fast measurement with medium lateral resolution. For high lateral resolution, another spot with 0.03 mm diameter from a laser source with the same wavelength can be switched on. The optics (3) collect the scattered light in an angle range of 32° and guides it to the linear detector (4). In contrast to other scattered light sensors this sensor measures the specular light (0°-part of the surface) together with the scattered light created by the microstructures of the surface. The advantage of this set-up is the capability to use the center of gravity of the scattered light distribution (5) as signal of the local geometrical deformation of the surface. Knowing the local slope angle of the surface and measuring continuously the surface in equal distance (created by an encoder signal) the local height can be calculated and, by integration of all angles, the entire profile of the surface.

The chuck with the wafer (6) rotates continuously during the measurement and the sensor moves linearly from the wafer edge to the center. Subsequently the sensor measures the entire wafer surface and assesses on a 300 mm wafer in the standard modus (0.9 mm spot) about 60.000 single roughness measurements in 30 s. Very important is an additional rotation (7) of the sensor because the linear detector should be always orien- tated normal to the grinding marks to get the maximum roughness value. As roughness parameter, the variance of the scattered light distribution Aq is calculated (FIGURE 2). ψi are the single scattered angles, M is the center of gravity and p(ψ) is the distribution curve.

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The advantage of Aq is the close relation with the profile slope parameter Rdq which describes surface friction very well. To follow the Semi standards in which the mean roughness Ra is established as roughness value, the Aq parameter was correlated with Ra by comparison measure- ments of different wafers with a confocal micro- scope. Due to the stochastically property of the amplitude distribution of the ground surface there is a rather good correlation between Aq and Ra even when using different grit size of the grinding wheel. But it should be taken into account that Aq is a more versatile parameter, because it reacts on both the vertical and lateral structures of a profile whereas Ra only measures the mean vertical height. This property of Aq could be interesting for characterizing die strength and should be investigated in more details in the future. In FIGURE 3 the measured correlation is shown. Several wafers were in- vestigated on different areas and ground with different grit sizes from #2000 to #8000. In addition, a CMP polished wafer with a Ra value <1nm was measured to check the accuracy of the system. In order to calculate the Ra-value the fitted correlation equation is used in the WaferMaster machine.

Screen Shot 2017-06-16 at 12.51.51 PM

As already mentioned, the scattered light sensor has a second evaluation channel to measure warpage and waviness by means of slope angle analysis. As shown in Fig. 2,the measurement beam is deflected under 2x the local slope angle θ. Therefore, the scattered light distribution is shifted on the linear detector by the angle value M. θ can be measured by using the first statistical moment of the scattered light distribution curve. Knowing the step size ∆x from an encoder and the focal length of the optics, the local height ∆y can be calculated and by sum up, the height profile can be generated.

Results

In FIGURE 4 the roughness results of 3 wafers are shown, each 300 mm size. They all were ground with the same grinding wheel (grit size #4000), but using different grinding machines. In total 40.000 measurements were taken in 25s with the 0.9mm spot. Besidesthe difference in the mean roughness value, it demonstrates in particular that the machines did leave its own characteristic pattern. The interpretation might be interesting to analyze in detail the grinding parameters as feed rate, chuck geometry, rotation speed, and others.

Screen Shot 2017-06-16 at 12.51.58 PM

An example of the simultaneous measurement of roughness, form (warp) and waviness of a 200 mm back grinding wafer can be seen in FIGURE 5. Although the grinding wheel was also grit size #4000, the mean Ra value is a bit higher. From the grinding marks pattern, it can be seen that the rotation was counterclockwise which changes the orientation from left to right. The warp is rather high because no vacuum was used. The waviness was calculated by applying a 50 waves high-pass filter. The filter is working on the circumference which means that the center area is filtered strongly than at the edge and middle area. Different filter method will be used in the future. The waviness structure follows the roughness pattern, but there are also visible some superimposed weak linear stripes from left to right. These stripes are more prominent in the following measurement (FIGURE 6), which is the result of another 200 mm wafer but ground with a #2000 grit wheel. The interesting point is not the higher roughness, which is induced by the coarser grinding wheel, but that the stripes here are more prominent than the waviness pattern of the grinding marks. The peak to valley height evaluated from A to B is more than 1 μm, which is about 10 times the profile height of the grinding marks waviness.

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The linear stripes are probably caused by the previous wire sawing process, which did not vanish after the grinding process. This could happen, because the wafer is fixed by vacuum on the chuck during grinding which makes the surface temporarily flat. When the wafer is released after the grinding process the waviness structures return. This phenomenon is investigated and described by Pei et al [3]. Furthermore, if the chuck is not cleaned very well the same characteristic can create bumps and dimples. An example of dimples is shown in FIGURE 7. The waviness map of a 300 mm polished wafer is covered with 2 larger and some smaller dimples. By using the 0.03 mm sensor spot the larger dimples where measured again with higher local resolution and represented in a 3D map. The width is in the mm range whereas the depth does not exceed 1 μm.

Screen Shot 2017-06-16 at 12.52.28 PM

Another example of high resolution measurement can be seen in Fig. 8. These measurements were done with an x/y-scanning module covering an area of 40 mm x 20 mm, also by using the small spot size of 0.03 mm. The measurements represent the waviness structures (after applying a 25 waves high pass filter). The mean roughness is 5 nm Ra. Near the center of this section another dimple is visible. The selected profile (a) shows the general waviness with a peak to valley height of about 30 nm. Repeatability measurements have shown that structures of 1 nm height could be resolved.

This makes the WaferMaster moreover interesting for the assessment of nanotopography structures to measure the planarization quality after CMP processes. Also, as can be seen in the 3D graphic, the small spot is able to detect single defects (red peak at the right side) and it has to be investigated, what the limit of lowest defects is. Certainly, it cannot compete with the much more powerful scattered light systems, especially designed for small defect detection in the front-end industry, but it is sufficient to use this function in backend processes.

Summary

A new scattered light sensor technique was presented to measure wafer surfaces, particular in the field of back grinding. The sensor combines surface roughness measurement by means of evaluating the variance (Aq) of the scattered light distribution and use additionally the method of deflectometry to assess form (warpage) and waviness. The Ra evaluation is based on correlation measurements with a confocal microscope. It could be shown that the sensitivity of roughness measurements is going down to Ra = 1 nm with an accuracy of 0.1 nm. The advantage of this technique is the speed (25 s for a whole 300 mm wafer scan) and the ruggedness against environmental mechanical noise. The capability of the full area representation of roughness, warpage and waviness opens new possibilities to characterize and improve the grinding processes as well as checking the quality from the edge area to the center completely.

Depending on the packaging design and the sensitivity of the processes which follow after the back grinding, the difference of the roughness from edge to the center and along the circumference, as well as strong warpage, waviness and defects can influence the final function and performance of the singulated chips. Die breakage e.g. directly depends on the roughness and in particular on the grinding marks orientation. Therefore, a fast and continuous measurement of the back-grinding quality can help to improve the yield in the backend process.

Acknowledgement

We would like to give special thanks to Kevin Hsu from Sanpany and Ian Chen, Honjang Global Technology for their kindly support in organizing the wafer samples and to confirm our CFM measurements with an WLI microscope.

References

[1] Michael Raj Marks, Zainuriah Hassan, Kuan Yew Cheong, Ultrathin Wafer Pre-Assembly and Assembly Process Technologies; Critical Reviews in Solid State and Materials Sciences, 40:251–290, 2015, DOI: 10.1080/10408436.2014.992585
[2] Desmond Y.R. Chong, W.E. Lee, B.K. Lim, John H.L. Pang, T.H. Low, Mechanical characterization in failure, strength of silicon dice, 2004 Inter Society Conference on Thermal Phenomena, 2004 IEEE
[3] Z.J. Pei, Graham R. Fisher, J.Liu, Grinding of Silicon Wafers: A review from historical perspectives, international Journal of Machine Tools & Manufacture, 48 (2008) 1297-1307
[4] Seewig, J., Beichert, G., Brodmann, R., Bodschwinna, H., and Wendel, M. 2009. Extraction of shape and roughness using scattering light. In Proceedings of SPIE. Optical metrology, Systems for Industrial Inspection VI 7389.

Samsung Electronics Co., Ltd. today announced that it has begun mass producing a new mid-power LED package, the LM301B, which features the industry’s highest luminous efficacy of 220 lumens per watt. The package is well suited for a range of LED lighting applications including ambient lighting, downlights and most retrofit lamps.

Samsung was able to achieve its industry-leading efficacy (@ 65mA, 5000K, CRI 80+) by incorporating an advanced flip-chip package design and state-of-the-art phosphor technology. The LM301B’s flip-chip design uses a highly reflective layer-formation technology to enhance light efficacy at the chip level. Also, a complete separation between its red phosphor film and green phosphors allows minimal interference during the phosphor conversion process, resulting in higher efficacy than conventional phosphor structures. These combined technology enhancements enable a 10-percent increase in overall efficacy compared to competing 3030 platform packages, without compromising on premium-quality light output.

“With our LM301B, we are able to deliver even greater mid-power value and help lower the total cost of ownership for LED lighting manufacturers,” said Jacob Tarn, Executive Vice President of LED Business Team at Samsung Electronics. “Thanks to advancements like the LM301B, Samsung will continue to drive innovation in next-generation LED technologies.”

Samples of the LM301B are available now.

Samsung_LED_Mid-power_package_LM301B

 

Javier Vela, scientist at the U.S. Department of Energy’s Ames Laboratory, believes improvements in computer processors, TV displays and solar cells will come from scientific advancements in the synthesis of low-dimensional nanomaterials.

Ames Laboratory scientists are known for their expertise in the synthesis and manufacturing of materials of different types, according to Vela, who is also an Iowa State University associate professor of chemistry. In many instances, those new materials are made in bulk form, which means micrometers to centimeters in size. Vela’s group is working with tiny, nanometer, or one billionth of a meter sized, nanocrystals.

“We’re trying to find out what happens with materials when we go to lower particle sizes, will the materials be enhanced or negatively impacted, or will we find properties that weren’t expected,” Vela said. “Our goal is to broaden the science of low-dimensional nanomaterials.” In an invited paper published in Chemistry of Materials entitled, “Synthetic Development of Low Dimensional Materials”, Vela and coauthors Long Men, Miles White, Himashi Andaraarachchi, and Bryan Rosales discussed highlights of some of their most recent work on the synthesis of low dimensional materials.

One of those topics was advancements in the synthesis of germanium-based core-shell nanocrystals. Vela says industry is very interested in semiconducting nanocrystal-based technologies for applications such as solar cells.

Small particle size can affect many things from transport properties (how well a nanocrystal conducts heat and electricity) to optical properties (how strong it interacts with light, absorbs light and emits light). This is especially true in photovoltaic solar cells “Let’s say you’re using a semiconductor material to make a solar device, there’s often different performance when solar cells are made from bulk materials as opposed to when they are made with nanomaterials. Nanomaterials interact with light differently; they absorb it better. That’s one way you can manipulate devices and fine tune their performance or power conversion efficiency,” said Vela.

Beyond solar cells, Vela says there’s tremendous interest in using nanocrystals in quantum dot television and computer displays, optical devices like LEDs (light-emitting diodes), biological imaging, and telecommunications.

He says there are many challenges in this area because depending upon the quality of the nanocrystals used, you can see different emission properties, which can affect the purity of light. “Ultimately the size of the nanocrystals being used can make a huge difference in the cleanliness or crispness of colors in TV and computer displays,” said Vela. “Television and computer technology is a multibillion dollar business worldwide, so you can see the potential value our understanding of properties of nanocrystals could bring to these technologies.”

In the paper, Vela’s group also discussed advancements made in the study of synthesis and spectroscopic characterization of organolead halide perovskites, which Vela says are some of the most promising semiconductors for solar cells because of their low cost and easier processability. He adds photovoltaics made of these materials now reach power conversion efficiencies of greater than 22 percent. Vela’s research in this area has focused on mixed-halide perovskites. He says his group has discovered these materials exhibit interesting chemical and photo physical properties that people hadn’t realized before, and now they are trying to better understand the correlation between the structure and chemical composition of perovskites and how they behave in solar cells. “One of our goals is to use what we’ve learned to help lower the cost of solar cells and produce them more reliably and readily,” Vela said.

In addition, Vela’s group is studying how to replace lead in traditional organolead halide perovskites with something less toxic, like germanium. “In principle, this is an area that should be much better known, but it’s not,” said Vela. “When we’ve been able to substitute germanium for lead, we have been able to produce a lighter perovskite, which he says could positively impact the automotive industry, for example.

“This could have great implications for transportation applications where you don’t want a lot of lead because it’s so heavy,” said Vela. Going forward Vela says his group’s focus will be on advancing the science in low-dimensional materials.

“We’re not working with well-known materials, but the newest; the most recently discovered,” Vela said. “And every time we can advance the science we’re one step closer to opportunities for more commercialization, more production, more manufacturing and more jobs in the U.S.”

Queen’s University Belfast researchers have discovered a new way to create extremely thin electrically conducting sheets, which could revolutionise the tiny electronic devices that control everything from smart phones to banking and medical technology.

Through nanotechnology, physicists Dr Raymond McQuaid, Dr Amit Kumar and Professor Marty Gregg from Queen’s University’s School of Mathematics and Physics, have created unique 2D sheets, called domain walls, which exist within crystalline materials.

The sheets are almost as thin as the wonder-material graphene, at just a few atomic layers. However, they can do something that graphene can’t – they can appear, disappear or move around within the crystal, without permanently altering the crystal itself.

This means that in future, even smaller electronic devices could be created, as electronic circuits could constantly reconfigure themselves to perform a number of tasks, rather than just having a sole function.

Professor Marty Gregg explains: “Almost all aspects of modern life such as communication, healthcare, finance and entertainment rely on microelectronic devices. The demand for more powerful, smaller technology keeps growing, meaning that the tiniest devices are now composed of just a few atoms – a tiny fraction of the width of human hair.”

“As things currently stand, it will become impossible to make these devices any smaller – we will simply run out of space. This is a huge problem for the computing industry and new, radical, disruptive technologies are needed. One solution is to make electronic circuits more ‘flexible’ so that they can exist at one moment for one purpose, but can be completely reconfigured the next moment for another purpose.”

The team’s findings, which have been published in Nature Communications, pave the way for a completely new way of data processing.

Professor Gregg says: “Our research suggests the possibility to “etch-a-sketch” nanoscale electrical connections, where patterns of electrically conducting wires can be drawn and then wiped away again as often as required.

“In this way, complete electronic circuits could be created and then dynamically reconfigured when needed to carry out a different role, overturning the paradigm that electronic circuits need be fixed components of hardware, typically designed with a dedicated purpose in mind.”

There are two key hurdles to overcome when creating these 2D sheets, long straight walls need to be created. These need to effectively conduct electricity and mimic the behavior of real metallic wires. It is also essential to be able to choose exactly where and when the domain walls appear and to reposition or delete them.

Through the research, the Queen’s researchers have discovered some solutions to the hurdles. Their research proves that long conducting sheets can be created by squeezing the crystal at precisely the location they are required, using a targeted acupuncture-like approach with a sharp needle. The sheets can then be moved around within the crystal using applied electric fields to position them.

Dr Raymond McQuaid, a recently appointed lecturer in the School of Mathematics and Physics at Queen’s University, added: “Our team has demonstrated for the first time that copper-chlorine boracite crystals can have straight conducting walls that are hundreds of microns in length and yet only nanometres thick. The key is that, when a needle is pressed into the crystal surface, a jigsaw puzzle-like pattern of structural variants, called “domains”, develops around the contact point. The different pieces of the pattern fit together in a unique way with the result that the conducting walls are found along certain boundaries where they meet.

“We have also shown that these walls can then be moved using applied electric fields, therefore suggesting compatibility with more conventional voltage operated devices. Taken together, these two results are a promising sign for the potential use of conducting walls in reconfigurable nano-electronics.”