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A team of researchers at the Israel Institute of Technology has developed a new capacitor with a metal-insulator-semiconductor (MIS) diode structure that is tunable by illumination. The capacitor, which features embedded metal nanoparticles, is similar to a metal-insulator-metal (MIM) diode, except that the capacitance of the new device depends on illumination and exhibits a strong frequency dispersion, allowing for a high degree of tunability.

This new capacitor has the potential to enhance wireless capability for information processing, sensing and telecommunications. The researchers report their findings this week in the Journal of Applied Physics, from AIP Publishing.

“We have developed a capacitor with the unique ability to tune the capacitance by large amounts using light. Such changes are not possible in any other device,” said Gadi Eisenstein, professor and director of the Russell Berrie Nanotechnology Institute at the Technion Israel Institute of Technology in Haifa and a co-author of the paper. “The observed photo sensitivity of this MIS diode structure expands its potential in optoelectronic circuits that can be used as a light-sensitive variable capacitor in remote sensing circuits.”

MIM diodes are common elements in electronic devices, especially those utilizing radio frequency circuits. They comprise thin-film metal plate electrodes that are separated by an insulator. Like the MIM structure, the researchers’ new MIS capacitor is bias independent, meaning the constant capacitance is independent of its supply voltage. Bias-independent capacitors are important for high linearity, and therefore straightforward predictability, of circuit performance.

“We have demonstrated that our MIS structure is superior to a standard MIM diode,” said Vissarion (Beso) Mikhelashvili, senior research fellow at the Israel Institute of Technology and also a co-author of the paper. “On one hand, it has all the features of an MIM device, but the voltage independent capacitance is tunable by light, which means that the tuning functionality can be incorporated in photonic circuits.”

“The illumination causes a twofold effect,” Eisenstein said. “First, the excitation of trap states enhances the internal polarization. Second, it increases the minority carrier density (due to photo generation) and reduces the depletion region width. This change modifies the capacitance.”

The researchers created three MIS structures, fabricated on a bulk silicon substrate, based on a multilayer dielectric stack, which consisted of a thin thermal silicon dioxide film and a hafnium oxide layer. The two layers were separated by strontium fluoride (SrF2) sublayers in which ferrum (Fe, iron) or cobalt (Co) nanoparticles were embedded.

The researchers found that the fluoridation-oxidation process of the iron atoms causes the formation of a gradient in the valence state of iron ions across the active layer, which results in the generation of an electronic polarization. The polarization causes a bias-independent depletion region and hence an MIM-type characteristic.

Four additional structures were prepared for comparison: Two lacked the SrF2 sublayers and one of them was prepared without the iron film. The other two structures contained SrF2: One did not have cobalt and the second included a one-nanometer Co layer.

The comparison with other MIS capacitors that contained the metal nanoparticles with or without the SrF2 sublayers led to the unequivocal conclusion that only devices consisting of the combination of Fe and SrF2 turn the MIS structure into a photo-sensitive MIM-like structure.

An engineer with the Erik Jonsson School of Engineering and Computer Science at The University of Texas at Dallas has designed a novel computing system made solely from carbon that might one day replace the silicon transistors that power today’s electronic devices.

“The concept brings together an assortment of existing nanoscale technologies and combines them in a new way,” said Dr. Joseph S. Friedman, assistant professor of electrical and computer engineering at UT Dallas who conducted much of the research while he was a doctoral student at Northwestern University.

The resulting all-carbon spin logic proposal, published by lead author Friedman and several collaborators in the June 5 issue of the online journal Nature Communications, is a computing system that Friedman believes could be made smaller than silicon transistors, with increased performance.

Today’s electronic devices are powered by transistors, which are tiny silicon structures that rely on negatively charged electrons moving through the silicon, forming an electric current. Transistors behave like switches, turning current on and off.

In addition to carrying a charge, electrons have another property called spin, which relates to their magnetic properties. In recent years, engineers have been investigating ways to exploit the spin characteristics of electrons to create a new class of transistors and devices called “spintronics.”

Friedman’s all-carbon, spintronic switch functions as a logic gate that relies on a basic tenet of electromagnetics: As an electric current moves through a wire, it creates a magnetic field that wraps around the wire. In addition, a magnetic field near a two-dimensional ribbon of carbon — called a graphene nanoribbon — affects the current flowing through the ribbon. In traditional, silicon-based computers, transistors cannot exploit this phenomenon. Instead, they are connected to one another by wires. The output from one transistor is connected by a wire to the input for the next transistor, and so on in a cascading fashion.

In Friedman’s spintronic circuit design, electrons moving through carbon nanotubes — essentially tiny wires composed of carbon — create a magnetic field that affects the flow of current in a nearby graphene nanoribbon, providing cascaded logic gates that are not physically connected.

Because the communication between each of the graphene nanoribbons takes place via an electromagnetic wave, instead of the physical movement of electrons, Friedman expects that communication will be much faster, with the potential for terahertz clock speeds. In addition, these carbon materials can be made smaller than silicon-based transistors, which are nearing their size limit due to silicon’s limited material properties.

“This was a great interdisciplinary collaborative team effort,” Friedman said, “combining my circuit proposal with physics analysis by Jean-Pierre Leburton and Anuj Girdhar at the University of Illinois at Urbana-Champaign; technology guidance from Ryan Gelfand at the University of Central Florida; and systems insight from Alan Sahakian, Allen Taflove, Bruce Wessels, Hooman Mohseni and Gokhan Memik at Northwestern.”

While the concept is still on the drawing board, Friedman said work toward a prototype of the all-carbon, cascaded spintronic computing system will continue in the interdisciplinary NanoSpinCompute research laboratory, which he directs at UT Dallas.

Silicon based CMOS (Complementary metal-oxide semiconductors) technology has truly shaped our world. It enables most of the electronics that we rely on today including computers, smartphones and digital cameras. However, to continue the path of progress in the electronics industry new technology must be developed and a key feature of this is the ability to integrate CMOS with other semiconductors. Now, Graphene Flagship researchers from ICFO (The Institute of Photonic Sciences in Barcelona) have shown that it is possible to integrate graphene into a CMOS integrated circuit.

This is graphene integrated onto CMOS pixels. Credit: Fabien Vialla

This is graphene integrated onto CMOS pixels. Credit: Fabien Vialla

In their paper published in the journal Nature Photonics they combine this graphene-CMOS device with quantum dots to create an array of photodetectors, producing a high resolution image sensor. When used as a digital camera this device is able to sense UV, visible and infrared light at the same time. This is just one example of how this device might be used, others include in microelectronics, sensor arrays and low-power photonics.

“The development of this monolithic CMOS-based image sensor represents a milestone for low-cost, high-resolution broadband and hyperspectral imaging systems” ICREA Professor at ICFO, Frank Koppens, highlights. He assures that “in general, graphene-CMOS technology will enable a vast amount of applications, that range from safety, security, low cost pocket and smartphone cameras, fire control systems, passive night vision and night surveillance cameras, automotive sensor systems, medical imaging applications, food and pharmaceutical inspection to environmental monitoring, to name a few”.

These results were enabled by the collaboration between Graphene Flagship Partner Graphenea (a Spanish graphene supplier) and ICFO, within the optoelectronics workpackage of the Graphene Flagship.

By creating a hybrid graphene and quantum dot system on a CMOS wafer using a layering and patterning approach, the Flagship team solved a complex problem with a simple solution. First the graphene is deposited, then patterned to define the pixel shape and finally a layer of PbS colloidal quantum dots is added. The photoresponse of this system is based on a photogating effect, which starts as the quantum dot layer absorbs light and transfers it as photo-generated holes or electrons to the graphene, where they circulate due to a bias voltage applied between two pixel contacts. The photo signal is then sensed by the change in conductivity of the graphene, with graphene’s high charge mobility allowing for the high sensitivity of the device.

As Stijn Goossens comments, “No complex material processing or growth processes were required to achieve this graphene-quantum dot CMOS image sensor. It proved easy and cheap to fabricate at room temperature and under ambient conditions, which signifies a considerable decrease in production costs. Even more, because of its properties, it can be easily integrated on flexible substrates as well as CMOS-type integrated circuits.”

The commercial applications of this research and the potential for imaging and sensing technology are now being explored in ICFO’s Launchpad incubator.

Professor Andrea Ferrari, Science and Technology Officer and Chair of the Management Panel of the Graphene Flagship added: “The integration of graphene with CMOS technology is a cornerstone for the future implementation of graphene in consumer electronics. This work is a key first step, clearly demonstrating the feasibility of this approach. The Flagship has put a significant investment in the system level integration of graphene, and this will increase as we move along the technology and innovation roadmap”.

Graphene and related two dimensional (2D) materials have raised massive interest and investment during the last years. However, the amount of 2D-materials-based commercial devices available in the market is still very low.

This image shows resistive random access memory made of graphene electrodes and hexagonal boron nitride dielectric. Credit: American Institute of Physics 2017.

This image shows resistive random access memory made of graphene electrodes and hexagonal boron nitride dielectric. Credit: American Institute of Physics 2017.

The research group led by Dr. Mario Lanza, a Young 1000 Talent Professor born in Barcelona (Spain) and based in Soochow University (China), is leading a global effort to investigate the properties of layered dielectrics. In their recent investigation, published in the journal 2D Materials, Prof. Lanza and co-workers synthesized a resistive random access memory (RRAM) using graphene/hexagonal-boron-nitride/graphene (G/h-BN/G) van der Waals structures. Furthermore, they developed a compact model to accurately describe its functioning. The model is based on the nonlinear Landauer approach for mesoscopic conductors, in this case atomic-sized filaments formed within the 2D materials system. Besides providing excellent overall fitting results (which have been corroborated in log-log, log-linear and linear-linear plots), the model is able to explain the dispersion of the data obtained from cycle-to-cycle in terms of the particular features of the filamentary paths, mainly their confinement potential barrier height.

The development of theoretical models to describe the functioning of electronic devices is one essential step enabling device/systems simulation, which is essential before device mass production. The device selected in this case, the RRAM device, is the most promising technology for future high-density information storage.

Currently, most parts of a smart phone are made of silicon and other compounds, which are expensive and break easily, but with almost 1.5 billion smart phones purchased worldwide last year, manufacturers are on the lookout for something more durable and less costly.

Dr. Elton Santos from Queen's University Belfast Credit: Queen's University Belfast

Dr. Elton Santos from Queen’s University Belfast
Credit: Queen’s University Belfast

Dr. Elton Santos from Queen’s University’s School of Mathematics and Physics, has been working with a team of top-notch scientists from Stanford University, University of California, California State University and the National Institute for Materials Science in Japan, to create new dynamic hybrid devices that are able to conduct electricity at unprecedented speeds and are light, durable and easy to manufacture in large scale semiconductor plants.

The team found that by combining semiconducting molecules C60 with layered materials, such as graphene and hBN, they could produce a unique material technology, which could revolutionise the concept of smart devices.

The winning combination works because hBN provides stability, electronic compatibility and isolation charge to graphene while C60 can transform sunlight into electricity. Any smart device made from this combination would benefit from the mix of unique features, which do not exist in materials naturally. This process, which is called van der Waals solids, allows compounds to be brought together and assembled in a pre-defined way.

Dr. Elton Santos explains: “Our findings show that this new ‘miracle material’ has similar physical properties to Silicon but it has improved chemical stability, lightness and flexibility, which could potentially be used in smart devices and would be much less likely to break.

“The material also could mean that devices use less energy than before because of the device architecture so could have improved battery life and less electric shocks.”

He added: “By bringing together scientists from across the globe with expertise in chemistry, physics and materials science we were able to work together and use simulations to predict how all of the materials could function when combined – and ultimately how these could work to help solve every day problems.

“This cutting-edge research is timely and a hot-topic involving key players in the field, which opens a clear international pathway to put Queen’s on the road-map of further outstanding investigations.”

The project initially started from the simulation side, where Dr. Santos predicted that such assembly of hBN, graphene and C60 could result in a solid with remarkable new physical and chemical properties. Then, he talked with his collaborators Professor Alex Zettl and Dr. Claudia Ojeda-Aristizabal at the University of California, and California St University in Long Beach (CA) about the findings. There was a strong synergy between theory and experiments throughout the project.

Dr. Santos said: “It is a sort of a ‘dream project’ for a theoretician since the accuracy achieved in the experiments remarkably matched what I predicted and this is not normally easy to find. The model made several assumptions that have proven to be completely right.”

The findings, which have been published in one of the most prestigious journals in the world ACS Nano, open the doors for further exploration of new materials. One issue that still needs to be solved with the team’s current research is that graphene and the new material architecture is lacking a ‘band gap’, which is the key to the on-off switching operations performed by electronic devices.

However, Dr. Santos’ team is already looking at a potential solution – transition metal dichalcogenides (TMDs). These are a hot topic at the moment as they are very chemically stable, have large sources for production and band gaps that rival Silicon.

He explains: “By using these findings, we have now produced a template but in future we hope to add an additional feature with TMDs. These are semiconductors, which by-pass the problem of the band gap, so we now have a real transistor on the horizon.”

Scientists have developed a new method of characterizing graphene’s properties without applying disruptive electrical contacts, allowing them to investigate both the resistance and quantum capacitance of graphene and other two-dimensional materials. Researchers from the Swiss Nanoscience Institute and the University of Basel’s Department of Physics reported their findings in the journal Physical Review Applied.

Graphene consists of a single layer of carbon atoms. It is transparent, harder than diamond and stronger than steel, yet flexible, and a significantly better conductor of electricity than copper. Since graphene was first isolated in 2004, scientists across the world have been researching its properties and the possible applications for the ultrathin material. Other two-dimensional materials with similarly promising fields of application also exist; however, little research has been carried out into their electronic structures.

No need for electrical contacts

Electrical contacts are usually used to characterize the electronic properties of graphene and other two-dimensional materials. However, these can significantly alter the materials’ properties. Professor Christian Schönenberger’s team from the Swiss Nanoscience Institute and the University of Basel’s Department of Physics has now developed a new method of investigating these properties without applying contacts.

To do this, the scientists embedded graphene in the isolator boron nitride, placed it on a superconductor and coupled it with a microwave resonator. Both the electrical resistance and the quantum capacitance of the graphene affect the quality factor and resonance frequency of the resonator. Although these signals are very weak, they can be captured using superconducting resonators.

By comparing the microwave characteristics of resonators with and without encapsulated graphene, the scientists can determine both the electrical resistance and quantum capacitance. “These parameters are important in the determination of graphene’s exact properties and in the identification of limiting factors for its application,” explains Simon Zihlmann, a PhD student in Schönenberger’s group.

Also suitable for other two-dimensional materials

The boron nitride-encapsulated graphene served as a prototype material during the method’s development. Graphene integrated into other materials can be investigated in the same way. In addition, other two-dimensional materials can also be characterized without the use of electrical contacts; for example, the semiconductor molybdenum disulfide, which has applications in solar cells and optics.

Imec, a research and innovation hub in nano-electronics and digital technologies, and Cascade Microtech, a FormFactor company, announced the successful development of a fully-automatic system for pre-bond testing of advanced 3D chips. Pre-bond testing is important to increase the yield of 3D stacked chips. The new system enables probing and hence testing of chips with large arrays of 40µm-pitch micro-bumps, on 300mm wafers. The relevance of this new tool is underlined by winning the 2017 National Instruments Engineering Impact Award yesterday at a ceremony in Austin, Texas.

As an emerging technology, 3D IC stacking still has many open options and technical challenges. One of these challenges is probing of the individual chips, before being stacked, to ensure a good yield of the 3D stacked ICs. The inter-chip connections of 3D stacked ICs are made by large arrays of fine-pitch micro-bumps which makes probing these bumps a challenge. Until today, the probing solution is to add dedicated pre-bond probe pads to the to-be-stacked dies, but this requires extra space and design effort and increases test time.

Imec and Cascade Microtech have now developed a fully automatic test cell that can provide test access by probing large arrays of fine-pitch micro-bumps. The system is based on a Cascade Microtech CM300 probe station and National Instruments PXI test instrumentation, complemented by in-house developed software for automatic test generation, data analysis, and visualization. The system allows testing of wafers up to 300mm diameter, including thinned wafers on tape frame with exposed through-silicon vias. After several years of intense collaboration between imec and Cascade Microtech, partly supported by the EU-funded FP7 SEA4KET project, good results were achieved with Cascade Microtech’s Pyramid Probe prototype RBI probe cards on imec’s 300mm wafers with 40µm-pitch micro-bumped chips.

“Imec provided us with unique early insights into the test requirements for 3D ICs, which drove the development of this system,” said Jörg Kiesewetter, director of engineering at Cascade Microtech Dresden. “Also the availability of imec’s dedicated micro-bump test wafers has helped us to fine-tune both the probe station and the probe cards for this application.”

“At imec, we are using the system now on a routine basis to test our 40µm-pitch micro-bumped wafers,” stated Erik Jan Marinissen, principal scientist at imec. “As everything in the semiconductor realm, also micro-bumps are subject to downscaling. Hence, with Cascade, we have started experiments to also probe our 20µm-pitch micro-bump arrays, and those look promising.”

The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held at the Hilton San Francisco Union Square hotel December 2-6, 2017, has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development.

The paper submission deadline this year is Wednesday, August 2, 2017. For the second year in a row the IEDM submission deadline is about 1½ months later than what had been the norm, reducing the time between paper submissions and publication of the cutting-edge research results for which the conference is known. Authors are asked to submit four-page camera-ready abstracts (instead of the traditional three pages), which will be published as-is in the proceedings.

Only a very limited number of late-news papers will be accepted. Authors are asked to submit late-news abstracts announcing only the most recent and noteworthy developments. The late-news submission deadline is September 11, 2017.

“Based on the success of the later paper-submission deadline last year, we have decided to make it an IEDM tradition,” said Dr. Barbara DeSalvo, Chief Scientist at Leti. “This helps ensure a rich and unique technical program.”

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics gather to participate in a technical program consisting of more than 220 presentations, along with special luncheon presentations and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events highlighting leading work in more areas of the field than any other conference.

This year special emphasis is placed on the following topics:
Advanced memory technologies
More-than-Moore device concepts
Neuromorphic computing/machine learning
Optoelectronics, photonics, displays and imaging systems
Package-device level interactions
Sensors and MEMS devices for biological/medical applications
Spin for memory and logic
Steep subthreshold devices
Technologies for 5nm and beyond

Overall, papers in the following areas of technology are encouraged:

  • Circuit and Device Interaction
  • Characterization, Reliability and Yield
  • Compound Semiconductor and High-Speed Devices
  • Memory Technology
  • Modeling and Simulation
  • Nano Device Technology
  • Optoelectronics, Displays and Imagers
  • Power Devices
  • Process and Manufacturing Technology
  • Sensors, MEMS and BioMEMS

As consumers around the world have become increasingly dependent on electronics, the transistor, a semiconductor component central to the operation of these devices, has become a critical subject of scientific research. Over the last several decades, scientists and engineers have been able to both shrink the average transistor size and dramatically reduce its production costs. The current generation of smartphones, for example, relies on chips that each feature over 3.3 billion transistors.

Most transistors are silicon-based and silicon technology has driven the computer revolution. In some applications, however, silicon has significant limitations. These include use in high power electronic devices and in harsh environments like the engine of a car or under cosmic ray bombardment in space. Silicon devices are prone to faltering and failing in difficult environments.

Addressing these challenges, Jiangwei Liu, from Japan’s National Institute for Materials Sciences, and his colleagues describe new work developing diamond-based transistors this week in the journal Applied Physics Letters, from AIP Publishing.

“Silicon-based transistors often suffer from high switching loss during power transmission and fail when exposed to extremely high temperatures or levels of radiation,” Liu said. “Given the importance of developing devices that use less power and perform under harsh conditions, there has been a lot of interest within the broader scientific community in determining a way to build transistors that utilizes manufactured diamonds, which are a very durable material.”

And with this very interest in mind, the team developed a new fabrication process involving diamond, bringing “hardened electronics” closer to realization.

“Manufactured diamonds have a number of physical properties that make them very interesting to researchers working with transistors,” said Yasuo Koide, a professor and senior scientist at the National Institute for Materials Science leading the research group. “Not only are they physically hard materials, they also conduct heat well which means that they can cope with high levels of power and operate in hotter temperatures. In addition, they can endure larger voltages than existing semiconductor materials before breaking down.”

The research group focused their work on enhancement-mode metal-oxide-semiconductor field-effect transistors (MOSFETs), a type of transistor that is commonly used in electronics. One of the distinguishing features of transistors is inclusion of an insulated terminal called a “gate” whose input voltage determines whether the transistor will conduct electricity or not.

“One of the developments that makes our fabrication process innovative is that we deposited yttrium oxide (Y2O3) insulator directly onto the surface of the diamond [to form the gate],” said Liu. “We added the yttrium oxide to the diamond with a technique known as electron beam evaporation, which involves using a beam of electrons to transform molecules of yttrium oxide from the solid state to the gaseous state so that they can be made to cover a surface and solidify on it.”

According to Liu, yttrium oxide has many desirable qualities, including high thermal stability, strong affinity to oxygen and wide band gap energy, which contributes to its capabilities as an insulator.

“Another innovation was that the yttrium oxide was deposited as a single layer,” Liu said. “In our previous work, we have created oxide bi-layers, but a single layer is appealing because it’s less difficult and less expensive to manufacture.”

Liu and his colleagues hope to refine their understanding of electron movement through the diamond transistor with future research projects.

“We work with a type of manufactured diamond that has a hydrogen layer on its surface. One of the important challenges going forward will be to understand the mechanism of electron conduction through this carbon-hydrogen layer,” said Liu.

“Ultimately, our team’s goal is to build integrated circuits with diamonds,” Koide said. “With this in mind, we hope our work can support the development of energy-efficient devices that can function in conditions of extreme heat or radiation.”

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has achieved an industry milestone with more than 1100 EVG wafer bonding chambers installed at customer facilities worldwide to date. This milestone cements EVG’s technology and market leadership in wafer bonding, which is an enabling process for volume manufacturing of semiconductor advanced packaging, MEMS, CMOS image sensors, and radio frequency (RF) devices. The EVG 500, EVG 850, GEMINI and ComBond series of wafer bonding solutions, in particular, are seeing strong demand due to their performance and cross-platform compatibility, which allows customers to more easily ramp up their R&D processes to high-volume manufacturing.

Every four seconds, a wafer is bonded with an EVG system. Shown here is a 300-mm bond chamber in an EVG®560 Automated Wafer Bonding System. The EVG560 accepts up to four bond chambers with various configuration options for all bonding processes, including anodic, thermo compression, fusion bonding and LowTemp™ plasma bonding.

Every four seconds, a wafer is bonded with an EVG system. Shown here is a 300-mm bond chamber in an EVG®560 Automated Wafer Bonding System. The EVG560 accepts up to four bond chambers with various configuration options for all bonding processes, including anodic, thermo compression, fusion bonding and LowTemp™ plasma bonding.

“For our high-volume customers, it is essential that they have ready access to industry-proven, cost-effective and high-yielding process solutions. EV Group has closely collaborated with customers and partners for nearly three decades to innovate wafer bonding technology, which has led to the establishment of our technology as the de-facto industry standard for high-volume manufacturing,” stated Hermann Waltl, executive sales and customer support director at EV Group. “Our product offerings span the entire manufacturing chain from R&D and small-scale production environments to full-scale, high-volume production. This enables us to support our customers throughout as they transform new ideas into real-world products.”

EVG’s wafer bonding solutions for adhesive and fusion/hybrid bonding, metal bonding (such as solder and eutectic), and high-vacuum encapsulation undergo continuous innovation in a variety of critical areas, including temperature and process uniformity, vacuum control, wafer alignment and ease of use to ensure a high-yielding and high-throughput bonding process. Manual and semi-automated wafer bonders are fully compatible with EVG production bonding systems, which shortens the development time for customers to bring new innovative devices to market.

For adhesive, solder and eutectic bonding, the EVG500 series of semi-automated wafer bonders and GEMINI series of fully-automated wafer bonders support non-hermetic, cost-efficient encapsulation of CMOS image sensors, surface acoustic wave (SAW) filters for wireless RF chips, and other devices for mobile phones and other high-volume consumer applications. Additionally, tool configurations can be tailored to more demanding bond processes such as hermetic encapsulation for MEMS devices.

For high-vacuum encapsulation bonding, the new EVG ComBond automated high-vacuum wafer bonder provides ultra-high vacuum encapsulation (10-8 mbar) needed for next-generation MEMS devices, such as gyroscopes, microbolometers, and advanced sensors used in autonomous cars, virtual reality headsets and other applications.

For fusion bonding, the EVG850LT and the GEMINI FB automated fusion bonders enable manufacturing of high-accuracy optical devices, image sensors, and engineered substrates such as silicon-on-insulator (SOI), silicon carbide (SiC) and gallium nitride (GaN) for RF, power and other high-speed/high-efficiency devices.

Added Waltl, “EVG is continuously improving our process solutions in order to address wider market applications and more stringent industry requirements. This has paid off for our customers, which in turn has enabled us to maintain our leadership position in the wafer bonding market. Every four seconds, a wafer is bonded with an EVG system. We are proud to bring our expertise gained from this far-reaching installed base to our customers around the world.”