Tag Archives: letter-pulse-tech

Discovery of new PVD chalcogenide materials for memory applications

April 28, 2017

A case study is presented based on the use of high throughput experimentation (HTE) for the discovery of new memory materials.

BY LARRY CHEN, MARK CLARK, CHARLENE CHEN, SUSAN CHENG and MILIND WELING, IMI Inc., San Jose, CA

The ever increasing demands for data translate into more sophisticated and specific thin film requirements for semiconductor materials. Each film layer has to not only demonstrate desired film properties, but also show good interfacial behavior with neighboring layers to contribute to the performance of the whole film stack or device. As a result, modern thin film material systems are including more elements from the periodic table with more complex compositions. The demand for short time to market has also increased, making the development of new materials even more difficult. In this paper, we present a case study of using high throughput experimentation (HTE) for the discovery of new memory materials. By using a combinatorial approach of sputtering technology, HTE can be applied to PVD chalcogenides and other materials targeted at memory semiconductors.
PVD background

Ever since the deposition of materials by magnetron sputtering was introduced by F. M. Penning, the technology has become a major method for industrial thin film deposition, which typically generates dense, hard, and robust thin film materials at relatively low production cost. The technology has been applied to major industries such as semiconductors, photovoltaics, optical coatings, displays, hard mechanical coatings, and so on. However, optimizing the magnetron sputtering processes has always been challenging to process and hardware design engineers, since material properties like density, crystalline structure, grain size, optical indices of a deposited film strongly depend on various process parameters, such as power, pressure, substrate temperature, sputter gas type, plasma type, sputter source to substrate distance, substrate bias, and pumping throughput. Additionally, the material properties heavily depend on the underlying layers, including the chosen substrate, below a film stack due to a texture effect in film structure and a formation of interfacial layers which comes from the intermixing of both materials. All the above parameters contribute to increasing the level of complexity of the development.

The semiconductor industry is constantly searching for new materials with unprecedented physical, optical, electrical, and mechanical properties, not only as a single film but also as a component of complex featured film stacks or functioning devices. This requires exploration of new materials not limited to pure or binary systems, but to ternary, quaternary systems and beyond. A very efficient solution to cope with the increasing complexity of development and the demand for short development time is a combinatorial approach.

The combinatorial approach can be defined as a process that couples the capability for parallel production of large arrays of diverse materials together with different high-throughput measurement techniques for various intrinsic and performance properties supported by data analytics for identifying lead materials [3]. For magnetron sputtering technology, the optimization of process param- eters has to be included as a major component of combinatorial approach. Considering all the multi-dimensional space of the development mentioned above, the combinatorial approach can be an excellent and efficient way of developing new materials in magnetron sputtering in terms of cost and time.

HTE methodology for PVD materials discovery

Platform Considerations As all process parameters in magnetron sputtering are somewhat correlated, it has been challenging for process engineers to come up with fully optimized process parameters for thin film production. In addition, semiconductor production facilities are typically optimized for consistent, efficient, high volume production of a single product at a time, and not for a wide range of simultaneous experiments. These factors make it challenging for memory manufacturers to test multiple materials, conditions and devices in an efficient manner, and without compromising either data quality or production throughput.

IMI’s high throughput experimentation (HTE) platform is set up for accelerated experimentation. Its combina- torial PVD tool typically has four sputter guns and one additional port at the center. All sputter guns can be equipped with various types of target materials including chalcogenides, puremetals, oxides, and nitrides, and each sputter source can be operated by different plasma modes independently, such as direct current (DC), pulsed direct current (PDC), and radio frequency (RF) with the ability to co-sputter with all four guns. The additional port at the center can be equipped with an ion beam source for ion beam assisted deposition, or ion beam cleaning, or an additional sputter gun which enables five gun co-sputtering operation. Process parameter windows can cover larger regimes than most production tool process parameters (Table 1).

FIGURE 1 shows an example of a multi-target sputter chamber capable of controllably forming a variety of compounds in an array across a 300 mm substrate and an example substrate shown at right. The materials can also be deposited on a die-to-die basis (not shown) over a 300mm wafer test vehicle for direct device testing without the need for patterning. The effectiveness of the combinatorial screening can be increased by guiding the selection of material compositions using both semi-phenomenological and DFT-based modeling, as well as relating the experimental data to the results obtained from simulated annealing using ab-initio molecular dynamics and further DFT analysis of the simulated quasi-amorphous structures.

Deposition methodology

Two different methods can be used to deposit the combinatorial films of interest: site isolated spot and gradient approaches. For the site isolated spot approach, multiple numbers of spots were deposited on a substrate. Each individual spot represents a split condition from a design of experiment (DOE). Film composition can be controlled through the co-sputter of guns, which are equipped with targets consisting of different materials. Also, the process condition of each spot can be varied through the process parameter settings. All deposition conditions and procedures are fully automated.

In the gradient approach, non-uniform film in terms of composition and thickness is intentionally generated on top of a substrate by co-sputtering through an open large area aperture. A semi-empirical model is used for the control of non-uniformity. The modeling also helps in controlling the film composition throughout a target’s lifetime. In this approach, composition gradients and the thickness gradients can be generated by a single film deposition on a substrate. Theoretically, an infinite number of variations can be analyzed within a film, which is only limited by the spatial resolution of metrologies.

Characterization and device performance

Once films have been deposited via PVD, characterization can be carried out, including testing of physical, optical and electrical parameters. These can range from general film characteristics including composition, thickness and crystallinity, to device-specific electrical parameters such as leakage, threshold voltage, and On/ Off ratio.

Measuring and analyzing large numbers of data generated from HTE methodology can be time- consuming. By using the automated metrology tools and a unified database system, measurements and analysis steps can be expedited to limit bottlenecks and deliver data most efficiently. A multi-stage approach can also help to prioritize and focus experimental resources on the most promising candidates.

HTE vs traditional methods

Key benefits of the HTE approach include the expedited learning cycle, cost reduction, and improved data quality. For semiconductor applications, a single 200mm or 300mm wafer can hold more than 30 splits, which can lead to a reduction in cycle of learning time (one device wafer instead of more than 30). Additionally, as all spots on a single wafer go through the same follow-up device fabrication steps together, data can be free from unexpected fluctuations of subsequent steps. Overall, the HTE approach can expedite the learning cycle by 5 ~ 10 times compared to single substrate based approach. A comparison of both HTE with traditional methods is summarized in Table 2.

A case study in NVM

New materials for memory elements such as non-volatile memory (NVM) selectors must meet a wide range of performance parameters (FIGURE 3 shows a typical memory cell with the selector element called out), in order to reduce sneak currents and manage variability in memory arrays.

Table 3 lists some of the key parameters desired in a memory selector material.

Of course, optimizing all of these parameters simultaneously in a single element or compound (and one that is practical for high volume memory manufacturing) is challenging. IMI’s HTE methodology enables rapid and simultaneous optimization of key trade-offs between performance, reliability and integration, in the quest for an ideal selector.

HTE for NVM selector materials

Use of a HTE methodology allows rapid screening of NVM selector candidate material compounds, compo- sitions and stacks. IMI has conducted multiple customer engagements in memory selector materials screening, and a typical experimental workflow is outlined in FIGURE 4, showing progression from PVD deposition, through physical and electrical characterizations of films and devices.

This experimental process can be carried out multiple times, through subsequently more advanced stages on a fewer number of samples, as promising candidates are narrowed down and further optimized. FIGURE 5 shows a possible strategy for testing a series of candi- dates through three different stages. In the earlier stages, a wide range of options could be screened quickly, but the more extensive (and time consuming) characterization and analysis can be saved for later stages, when only the best performing candidates are already selected. This enables the best use of deposition and testing resources, leading to optimal results in an efficient timeframe.

Fast and high-quality experimental results

IMI has extensive experience in working both on dynamic random access memory (DRAM) as well as NVM materials. In DRAM, the company has worked on development of dielectric, electrode and interface layer materials. IMI’s process engineers, materials scientists and electrical engineers work upfront with a customer on the design of experiments to ensure the delivery of rapid cycles of learning with the most efficient use of resources.

A typical customer project might range between a few months up to a year or more, encompassing hundreds or even thousands of different experiments. In NVM selectors alone, IMI has conducted:
• 2500+experiments on Metal Chalcogenides
• 2000+ experiments on MIEC
• 1000+experiments on Transition Metal Oxides

Conclusion

High throughput experimentation can offer rapid, high quality materials data when effectively applied to PVD memory selector development. However it does require an advanced platform, and a facility and team experienced in efficient deposition and testing of the materials and devices. Materials and device expertise is also helpful in managing and optimizing the experimental workflow for maximum efficiency and high quality data.

Dawn of organic single crystal electronics

April 28, 2017

Researchers at the Institute for Molecular Science, National Institutes of Natural Sciences (Japan) have developed a method for high performance doping of organic single crystal. Furthermore, they succeeded in the Hall effect measurement of the crystal — the world’s first case. The research has been published in the Advanced Materials.

Controlling “holes” and “electrons” responsible for electric conduction of p-type and n-type semiconductors by doping — adding a trace amount of impurity — had been the central technology in the 20th century’s inorganic single crystal electronics represented by silicon chips, solar cells, and light emitting diodes. The number of carriers (holes and electrons) created by doping and their moving speed (mobility) can be freely evaluated by “Hall effect measurement” using a magnetic field. However, in the field of organic electronics emerging in the 21th century, no one has ever attempted to dope impurities into an organic single crystal itself nor measure its Hall effect.

“We have combined the rubrene organic single crystal growth technique with our original ultra-slow deposition technique of one billionth of a nanometer (10- 9 nm) per second, which includes a rotating shutter having aperture.” explains Chika Ohashi, a PhD student, SOKENDAI in the group. “For the first time, we have succeeded in producing the 1 ppm doped organic single crystal and have detected its Hall effect signal.” The doping efficiency of the organic single crystal was 24%, which is a much higher performance compared to 1% for the vacuum deposited amorphous film of the same material.

Lab head Prof. Masahiro Hiramoto sees the present results have the meaning of dawn of organic single crystal electronics similar to the silicon single crystal electronics. In future, devices such as high performance organic single crystal solar cells may be developed.

Diamond quantum sensor reveals current flows in next-gen materials

April 27, 2017

Researchers at the University of Melbourne are the first in the world to image how electrons move in two-dimensional graphene, a boost to the development of next-generation electronics.

Capable of imaging the behaviour of moving electrons in structures only one atom in thickness, the new technique overcomes significant limitations with existing methods for understanding electric currents in devices based on ultra-thin materials.

“Next-generation electronic devices based on ultra-thin materials, including quantum computers, will be especially vulnerable to contain minute cracks and defects that disrupt current flow,” said Professor Lloyd Hollenberg, Deputy Director of the Centre for Quantum Computation and Communication Technology (CQC2T) and Thomas Baker Chair at the University of Melbourne.

A team led by Hollenberg used a special quantum probe based on an atomic-sized ‘colour centre’ found only in diamonds to image the flow of electric currents in graphene. The technique could be used to understand electron behaviour in a variety of new technologies.

“The ability to see how electric currents are affected by these imperfections will allow researchers to improve the reliability and performance of existing and emerging technologies. We are very excited by this result, which enables us to reveal the microscopic behaviour of current in quantum computing devices, graphene and other 2D materials,” he said.

“Researchers at CQC2T have made great progress in atomic-scale fabrication of nanoelectronics in silicon for quantum computers. Like graphene sheets, these nanoelectronic structures are essentially one atom thick. The success of our new sensing technique means we have the potential to observe how electrons move in such structures and aid our future understanding of how quantum computers will operate.”

In addition to understanding nanoelectronics that control quantum computers, the technique could be used with 2D materials to develop next generation electronics, energy storage (batteries), flexible displays and bio-chemical sensors.

“Our technique is powerful yet relatively simple to implement, which means it could be adopted by researchers and engineers from a wide range of disciplines,” said lead author Dr Jean-Philippe Tetienne from CQC2T at the University of Melbourne.

“Using the magnetic field of moving electrons is an old idea in physics, but this is a novel implementation at the microscale with 21st Century applications.”

The work was a collaboration between diamond-based quantum sensing and graphene researchers. Their complementary expertise was crucial to overcoming technical issues with combining diamond and graphene.

“No one has been able to see what is happening with electric currents in graphene before,” said Nikolai Dontschuk, a graphene researcher at the University of Melbourne School of Physics.

“Building a device that combined graphene with the extremely sensitive nitrogen vacancy colour centre in diamond was challenging, but an important advantage of our approach is that it’s non-invasive and robust – we don’t disrupt the current by sensing it in this way,” he said.

Tetienne explained how the team was able to use diamond to successfully image the current.

“Our method is to shine a green laser on the diamond, and see red light arising from the colour centre’s response to an electron’s magnetic field,” he said.

“By analysing the intensity of the red light, we determine the magnetic field created by the electric current and are able to image it, and literally see the effect of material imperfections.”

First EUV lithography high-volume manufacturing solution for N5 BEOL

April 27, 2017

Immersion-based self-aligned quadruple patterning is combined with EUV lithography block patterning to achieve metal layers with pitches as small as 32nm.

BY JOOST BEKAERT and MING MAO, imec, Leuven, Belgium

At the 2017 SPIE Advanced Lithography conference, imec – in close collaboration with its suppliers – presented an industry relevant platform for patterning the most advanced back-end-of- line metal layers, conform with the foundry N5 technology node. Imec’s solution includes two scenarios for EUV lithography insertion, as well as proposals for design rules, masks, photoresists, etching, metrology and variation assessment. In this article, one of these scenarios is described in more detail. It combines immersion-based self-aligned quadruple patterning with EUV lithography block patterning, to achieve metal layers with pitches as small as 32nm. To assess the platform’s suitability for high- volume manufacturing, the uniformity of the layers and their local variability is discussed.

The patterning of advanced logic back-end-of-line layers

As we move towards more advanced technology nodes, the patterning of critical back-end-of-line (BEOL) metal layers with ever more aggressive pitches (e.g. 32nm) has become very challenging. In these BEOL layers, typically, trenches are created which are then filled with metal in a final metallization step. In order to create a disconnection in the continuous trenches, block layers perpendicular to the trenches are added, resulting in small metal tip-to-tips. In the industry, various options are considered to pattern the most aggressive BEOL layers and blocks. One option is to use immersion lithography in combination with so-called self-aligned quadruple patterning (SAQP) for the metal lines, and triple patterning for the block layers. This option however requires a triple block mask and a triple litho-etch process flow, which adds to the cost and complexity of the proposed solution. Another option is to pattern the BEOL metal layers directly with EUV lithography (EUVL) in one single exposure. Although this direct EUVL integration flow is very simple and cost-effective, pattern fidelity (e.g. the shape of the pattern) and pattern variability, as well as mask making are expected to be extremely challenging, especially for very small tip-to-tips.

One of the alternatives imec is evaluating is a ‘hybrid’ option, in which immersion-based SAQP of metal lines is combined with a direct EUV print of the block layer – using ASML’s NXE:3300 scanner.

The imec N7 (iN7) EUV platform

To evaluate the viability of this ‘SAQP + EUV block patterning’ option, imec makes use of its iN7 platform. This platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. The platform considers two layers: metal1, with 42nm pitch, and metal2, with 32nm pitch and 7.5 track design. Via1 connects the two metal layers using a dual damascene process flow. With these aggressive pitches, iN7 corresponds to IDM N7 and foundry N5 requirements for the BEOL. The patterning of both metal1 and via1 can be achieved through EUV single exposure. The iN7 platform is used to evaluate the hybrid immersion/EUVL solution for patterning metal2.

Optimizing design rules, mask and etch process

Prior to printing and evaluating the pattern, considerable efforts and innovations were performed in various litho-related areas. First, imec developed compliant design and design rules to support the possible patterning schemes. Also, an appropriate resist material was chosen for the EUV block process, and its impact on the optical proximity correction was studied – leading to a 2D OPC full-chip model. This model and other computational lithography techniques were used to design and fabricate the right EUV block masks. And finally, new chemistries and novel integration schemes for the etch process have been developed.

Creating SAQP lines and EUV blocks

SAQP (or self-aligned quadruple patterning) is a double spacer technique that is already well established in industry.Basically,this process uses one lithography step and additional deposition and etch steps to define spacer- like features.

Imec’s process flow starts from metal2 core lines, i.e. a (pre) pattern of lines created by immersion lithography (using the ASML NXT:1970i immersion scanner). On top of this pattern, a layer of spacer material is deposited. Then, the spacer is etched and the core material is removed. This second ‘core’ pattern is then used to apply the second spacer, by re-iterating the sequence of spacer deposition, spacer etch and core removal. After these steps, each edge of a core line results in a doublet of spacer lines. As a final result, groups of 6 spacer lines are created with a 4x denser pitch (16nm half pitch) than the initial (pre)pattern. This grating is then transferred into SiN, leaving a pattern of SiN lines on top of a TiN layer (FIGURE 1).

In a next step, block features are added on top of the SAQP pattern. First, spin-on carbon (SoC) is coated on top of the spacer pattern. After resist coating, EUV exposure on the ASML NXE:3300 scanner then creates the block features in the resist material on top of the SoC. After SoC etch, pillar-like SoC block features of 65nm height stand on the spacer lines. This joint SAQP + block pattern is then patterned into the underlying TiN layer, which serves as a hard mask. By etching the trenches within this pattern into the low-k dielectric layer below, and metallizing them, the final metal2 pattern is obtained. The width of the block features determines the metal2 tip-to-tip critical dimension (FIGURE 2).

Assessing pattern fidelity and local variability

An important part of this work is to qualify the pattern fidelity and variability, as this will contribute to the viability of the proposed solutions for industrial manufac- turing. At this small pitch of 32nm, even minor process variations in EUV lithography may have significant impact on the device performance. Such variations are due to overlay and CD uniformity, but also to stochastic effects in the resist.

In particular, the uniformity of the width and length of the block features are important parameters. The width of a block at the location of a trench determines the resulting metal tip-to-tip on that trench. The final target for the iN7 design is to achieve a critical dimension of 21nm metal tip-to-tip after low-k etch. The experiments show that the critical dimension is sufficiently uniform over the wafer. With further fine-tuning, it is expected to remain below 1nm 3sigma. Also the local variation of the block width and placement are important and determine the overlap of the metal line-end with the via that connects to a layer above or below. The major contributor to the local variation turns out to be the stochastic noise, coming from statistical variations in how the available photons interact with the resist. Added to the overlay (which involves the ability of the scanner to align the various layers accurately on top of each other), an edge placement error of the metal tip position of ~5nm 3sigma is obtained. Whether this provides sufficient overlap with the via layer, will depend on the design rule. For example, if no direct neighboring vias are allowed, there will be sufficient margin through the design extension of the metal tip over the via.

Another critical dimension is related to the length of the block, as this will be critical in determining the metal trench ‘blocking’ efficiency. A too short block feature could lead to an incomplete cut of the metal trench, and a too long feature can pinch neighboring metal trenches. Ideally, the block end is positioned halfway the spacer line. The maximum budget for the variation of the block end vs. the spacer edges is +/- 8nm. The dominant consumers of this budget are again the overlay and stochastics, adding to a local variation of ~6nm 3sigma. Thus, with a 3sigma requirement and if other contrib- utors (such as intra-wafer CDU) can be kept small, the spacer width (16nm) is expected to provide sufficient budget to enable the SAQP + block technology for the iN7 (FIGURE 3).

Towards EUV implementation for high-volume manufacturing

Imec researchers have investigated the use of SAQP in combination with a single EUV blocking step for printing the critical 32nm pitch metal2 layer in the back-end-of- line. An important finding is that the current imaging performance of the ASML NXE:3300 is sufficient to print the metal2 block layer. The results clearly show the successful integration capability of the EUVL defined block. However, overlay and stochastics came forward as key attention points and will need further improvement, especially if further downscaling is pursued.

The proposed solution is a viable alternative to SAQP + immersion triple block patterning of the 32nm metal layer. From a cost perspective, a 20% cost reduction can be expected from the ‘hybrid’ solution with direct EUV block print, and EUV print of the vias. An additional cost reduction of 3% is expected from a scenario that uses only EUV in one single exposure for patterning the BEOL metal layers. First results point towards pattern fidelity and mask making as the main challenges for this option. Optimizations for this option are ongoing.

As pitch-only scaling doesn’t meet the full require- ments for the foundry N5 node, the solutions have been complemented by co-optimizing the technology and the standard cell libraries, resulting in significantly lower standard cell heights. This will allow a full node definition whereby the wafer cost increase of scaling boosters (approx. 3%) is offset by an area reduction gain of approx. 21%.

Including the proposals for design rules, masks, photo- resists, etching and metrology, for which imec worked in close collaboration with equipment and material suppliers, all these studies form the first comprehensive solution towards EUVL enablement for high-volume manufacturing.

Model for multivalley polaritons

April 25, 2017

Everything we experience is made of light and matter. And the interaction between the two can bring about fascinating effects. For example, it can result in the formation of special quasiparticles, called polaritons, which are a combination of light and matter. A team at the Center for Theoretical Physics of Complex Systems, within the Institute for Basic Science (IBS), modeled the behavior of polaritons in microcavities, nanostructures made of a semiconductor material sandwiched between special mirrors (Bragg mirrors). Published in Scientific Reports, this research brings new ideas to the emerging valleytronics field.

Minimal energy locations, called valleys, are shown with white crosses. Credit: IBS

Emerging from the coupling of light (photons) and matter (bound state of electrons and holes known as excitons), polaritons have characteristics of each. They are formed when a light beam of a certain frequency bounces back and forth inside microcavities, causing the rapid interconversion between light and matter and resulting in polaritons with a short lifetime. “You can imagine these quasiparticles as waves that you make in water, they move together harmoniously, but they do not last very long. The short lifetime of polaritons in this system is due to the properties of the photons,” explains Mr Meng Sun, first author of the study.

Researchers are studying polaritons in microcavities to understand how their characteristics could be exploited to outperform the present semiconductor technologies. Modern optoelectronics read, process, and store information by controlling the flow of particles, but looking for new more efficient alternatives, other parameters, like the so-called ‘valleys’ could be considered. Valleys can be visualized by plotting the energy of the polaritons to their momentum. Valleytronics aims to control the properties of the valleys in some materials, like transition metal dichalcogenides (TMDCs), indium gallium aluminum arsenide (InGaAlAs), and graphene.

Being able to manipulate their features would lead to tunable valleys with two clearly different states, corresponding for example to 1 bit and 0 bit, like on-off states in computing and digital communications. A way to distinguish valleys with the same energy level is to obtain valleys with different polarization, so that electrons (or polaritons) would preferentially occupy one valley over the others. IBS scientists have generated a theoretical model for valley polarization that could be useful for valleytronics.

Although polaritons are formed by the coupling of photons and excitons, the research team modeled the two components independently. “Modeling potential profiles of photons and excitons separately is the key to find where they overlap, and then determine the minimal energy positions where valleys occur,” points out Sun.

A crucial feature of this system is that polaritons can inherit some properties, like polarization. Valleys with different polarization form spontaneously when the splitting of the transverse (i.e. perpendicular) electronic and magnetic modes of the light beam is taken into consideration (TE-TM splitting).

Since this theoretical model predicts that valleys with opposite polarization can be distinguished and tuned, in principle, different valleys could be selectively excited by a polarized laser light, leading to a possible application in valleytronics.

Wonder material? Novel nanotube structure strengthens thin films for flexible electronics

April 24, 2017

Reflecting the structure of composites found in nature and the ancient world, researchers at the University of Illinois at Urbana-Champaign have synthesized thin carbon nanotube (CNT) textiles that exhibit both high electrical conductivity and a level of toughness that is about fifty times higher than copper films, currently used in electronics.

Scanning Electron Microscope Images of architectured carbon nanotube (CNT) textile made at Illinois. Colored schematic shows the architecture of self-weaved CNTs, and the inset shows a high resolution SEM of the inter-diffusion of CNT among the different patches due to capillary splicing. Credit: University of Illinois

“The structural robustness of thin metal films has significant importance for the reliable operation of smart skin and flexible electronics including biological and structural health monitoring sensors,” explained Sameh Tawfick, an assistant professor of mechanical science and engineering at Illinois. “Aligned carbon nanotube sheets are suitable for a wide range of application spanning the micro- to the macro-scales including Micro-Electro-Mechanical Systems (MEMS), supercapacitor electrodes, electrical cables, artificial muscles, and multi-functional composites.

“To our knowledge, this is the first study to apply the principles of fracture mechanics to design and study the toughness nano-architectured CNT textiles. The theoretical framework of fracture mechanics is shown to be very robust for a variety of linear and non-linear materials.”

Carbon nanotubes, which have been around since the early nineties, have been hailed as a “wonder material” for numerous nanotechnology applications, and rightly so. These tiny cylindrical structures made from wrapped graphene sheets have diameter of a few nanometers–about 1000 times thinner than a human hair, yet, a single carbon nanotube is stronger than steel and carbon fibers, more conductive than copper, and lighter than aluminum.

However, it has proven really difficult to construct materials, such as fabrics or films that demonstrate these properties on centimeter or meter scales. The challenge stems from the difficulty of assembling and weaving CNTs since they are so small, and their geometry is very hard to control.

“The study of the fracture energy of CNT textiles led us to design these extremely tough films,” stated Yue Liang, a former graduate student with the Kinetic Materials Research group and lead author of the paper, “Tough Nano-Architectured Conductive Textile Made by Capillary Splicing of Carbon Nanotubes,” appearing in Advanced Engineering Materials. To our knowledge, this is the first study of the fracture energy of CNT textiles.

Beginning with catalyst deposited on a silicon oxide substrate, vertically aligned carbon nanotubes were synthesized via chemical vapor deposition in the form of parallel lines of 5μm width, 10μm length, and 20-60μm heights.

“The staggered catalyst pattern is inspired by the brick and mortar design motif commonly seen in tough natural materials such as bone, nacre, the glass sea sponge, and bamboo,” Liang added. “Looking for ways to staple the CNTs together, we were inspired by the splicing process developed by ancient Egyptians 5,000 years ago to make linen textiles. We tried several mechanical approaches including micro-rolling and simple mechanical compression to simultaneously re-orient the nanotubes, then, finally, we used the self-driven capillary forces to staple the CNTs together.”

“This work combines careful synthesis, and delicate experimentation and modeling,” Tawfick said. “Flexible electronics are subject to repeated bending and stretching, which could cause their mechanical failure. This new CNT textile, with simple flexible encapsulation in an elastomer matrix, can be used in smart textiles, smart skins, and a variety of flexible electronics. Owing to their extremely high toughness, they represent an attractive material, which can replace thin metal films to enhance device reliability.”

In addition to Liang and Tawfick, co-authors include David Sias and Ping Ju Chen.

Analog Devicesâ MEMS accelerometers deliver compelling noise performance for condition monitoring applications

April 24, 2017

Analog Devices, Inc. (ADI) today announced two high frequency, low noise MEMS accelerometers designed specifically for industrial condition monitoring applications. The ADXL1001 and ADXL1002 MEMS accelerometers deliver the high resolution vibration measurements necessary for early detection of bearing faults and other common causes of machine failure. Historically, inadequate noise performance of available high frequency MEMS accelerometers compared with legacy technology held back adoption, failing to take advantage of MEMS reliability, quality and repeatability. Today, the ADXL1001 and ADXL1002 noise performance over high frequencies is on par with available PZT technology, and make ADI MEMS accelerometers a compelling option for new condition monitoring products. The ADXL1001 and ADXL1002 are the latest examples of high performance precision sensing technology from Analog Devices, providing high quality and accurate data for Smart Factory Internet of Things applications, and enabling intelligent sensing from the edge of the network.

The ADXL1001 and ADXL1002 MEMS accelerometers deliver ultra-low noise density over an extended bandwidth with high-g range. The accelerometers are available in two models with full-scale ranges of ±100g (ADXL1001) and ±50g(ADXL1002). Typical noise density for the ADXL1002 is 25 μg/√Hz, with a sensitivity of 40mV/g, and 30 μg/√Hz for ADXL1001 with sensitivity 20mV/g. Both accelerometers operate on single voltage supply from 3.0V to 5.25V, and offer useful features such as complete, electrostatic self-test and over range indicator. The ADXL1001 and ADXL1002 are rated for operation over a -40°C to +125°C temperature range.

Product Pricing and Availability Product Pricing and Availability

Product

Output
Interface

Full-scale
Range

Product
Availability

Price Each
per 1,000

Packaging

ADXL1001

Analog

±100 g

Now

$29.61

32 lead 5×5 mm
LFCSP

ADXL1002

Analog

±50 g

Now

$29.61

32 lead 5×5 mm
LFCSP

Reducing down to 1/3 of thermal resistance by WOW technology for 3D DRAM application

April 24, 2017

Researcher team led by Professor Takayuki Ohba at Tokyo Institute of Technology, ICE Cube Center, in collaboration with the WOW (Wafer-on-Wafer) Alliance(^{term 2}), an Industry-academic collaborative research organization consisting of multiple semiconductor related companies aiming for practical applications of 3D IC technology, demonstrated the thermal resistance of the 3D stacked device can be reduced down to less than 1/3 relative to the conventional one bonded by bump(^{term 3}) 3D IC in Through-Silicon-Via (TSV) wiring(^{term 4}). Since semiconductor circuits are highly heat-generating bodies during operation, when heat is hard to be released, the temperature of the semiconductor results in highly rise, which leads to be a malfunction. The development of heat dissipation technology has been a big challenge.

To address this challenge, Ohba and colleagues analyzed thermal properties in 3D IC using finite element method (FEM)(^{term 5}) and thermal network calculation method. The study identified three main factors of thermal resistance; the interconnection layers, dielectric layers and organic layers in the conventional bump type device. Contrary to the bump type, the thermal performance of a bumpless 3D IC was almost 150 times better than that of a conventional IC at the same TSV density. The researchers demonstrated to reduce the total thermal resistance to 0.46 Kcm2/W, whereas the conventional method is 1.54 Kcm2/W. This suggests that the bumpless enables lower temperature rise and three to four times further DRAM stacking.

This is a cross-sectional structure of micro bump and bumpless. Credit: Tokyo Institute of Technology

Based on their demonstration experiments, the scientists will work toward practical use of large-capacity memory technology for mobile terminals and servers.

Conax Technologies announces the acquisition of Arizona-based Quartz Engineering

April 24, 2017

Conax Technologies announced the acquisition of Quartz Engineering, a manufacturer of quartz sheaths for temperature sensors headquartered in Tempe, AZ. S. K. Choi, former President of Quartz engineering, will stay on and help with the integration of Quartz Engineering and Conax. Choi has 40 years of experience in the semiconductor segment of the quartz industry and 20 years of experience in the fabrication of the specific type of sheaths primarily used by Conax.

This acquisition represents a commitment to improving the company’s responsiveness and the quality of products the company can provide to customers in the semiconductor industry.

Conax Business Unit Manager Michael Ferraro stated, “We’re expanding our focus in the growing Semiconductor industry. Many of the temperature sensors used inside process chambers need a semiconductor-grade quartz sheath to protect them from the chemicals and temperatures present. With the acquisition of Quartz Engineering, we now have in-house capabilities to design and manufacture quartz sheaths for temperature sensors.”

Ferraro explained, “By producing the sheaths in-house, we maintain greater control over quality and supply; and we can provide our customers with the solutions they need faster.”

Manufacturing operations will remain at the Tempe, AZ facility. Headquartered in Buffalo, NY, Conax Technologies is a designer and manufacturer of standard and custom engineered temperature sensors, compression seal fittings and feedthroughs, probes, sensors, wires, electrodes and fiber optic cables. The company has locations on the US west coast, as well as in Canada, Europe and Asia.

Engineering technique is damaging materials, research reveals

April 21, 2017

A technique that revolutionised scientists’ ability to manipulate and study materials at the nano-scale may have dramatic unintended consequences, new Oxford University research reveals.

Felix Hofmann and Edmund Tarleton, both authors of the paper, at the FIB instrument at the Department of Materials, University of Oxford, UK. Credit: Oxford University

Focused Ion Beam Milling (FIB) uses a tiny beam of highly energetic particles to cut and analyse materials smaller than one thousandth of a stand of human hair.

This remarkable capability transformed scientific fields ranging from materials science and engineering to biology and earth sciences. FIB is now an essential tool for a number of applications including; researching high performance alloys for aerospace engineering, nuclear and automotive applications and for prototyping in micro-electronics and micro-fluidics.

FIB was previously understood to cause structural damage within a thin surface layer (tens of atoms thick) of the material being cut. Until now it was assumed that the effects of FIB would not extend beyond this thin damaged layer. Ground-breaking new results from the University of Oxford demonstrate that this is not the case, and that FIB can in fact dramatically alter the material’s structural identity. This work was carried out in collaboration with colleagues from Argonne National Laboratory, USA, LaTrobe University, Australia, and the Culham Centre for Fusion Energy, UK.

In research newly published in the journal Scientific Reports, the team studied the damage caused by FIB using a technique called coherent synchrotron X-ray diffraction. This relies on ultra-bright high energy X-rays, available only at central facilities such as the Advanced Photon Source at Argonne National Lab, USA. These X-rays can probe the 3D structure of materials at the nano-scale. The results show that even very low FIB doses, previously thought negligible, have a dramatic effect.

Felix Hofmann, Associate Professor in Oxford’s Department of Engineering Science and lead author on the study, said, “Our research shows that FIB beams have much further-reaching consequences than first thought, and that the structural damage caused is considerable. It affects the entire sample, fundamentally changing the material. Given the role FIB has come to play in science and technology, there is an urgent need to develop new strategies to properly understand the effects of FIB damage and how it might be controlled.”

Prior to the development of FIB, sample preparation techniques were limited, only allowing sections to be prepared from the material bulk, but not from specific features. FIB transformed this field by making it possible to cut out tiny coupons from specific sites in a material. This progression enabled scientists to examine specific material feature using high-resolution electron microscopes. Furthermore it has made mechanical testing of tiny material specimens possible, a necessity for the study of dangerous or extremely precious materials.

Although keen for his peers to heed the serious consequence of FIB, Professor Hofmann said, “The scientific community has been aware of this issue for a while now, but no one (myself included) realised the scale of the problem. There is no way we could have known that FIB had such invasive side effects. The technique is integral to our work and has transformed our approach to prototyping and microscopy, completely changing the way we do science. It has become a central part of modern life.”

Moving forward, the team is keen to develop awareness of FIB damage. Furthermore, they will build on their current work to gain a better understanding of the damage formed and how it might be removed. Professor Hofmann said, “We’re learning how to get better. We have gone from using the technique blindly, to working out how we can actually see the distortions caused by FIB. Next we can consider approaches to mitigate FIB damage. Importantly the new X-ray techniques that we have developed will allow us to assess how effective these approaches are. From this information we can then start to formulate strategies for actively managing FIB damage.”