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By David W. Price, Douglas G. Sutherland, Jay Rathert, John McCormack and Barry Saville

Author’s Note:The Process Watch series explores key concepts about process control—defect inspection, metrology and data analytics—for the semiconductor industry. This article is the third in a series on process control strategies for automotive semiconductor devices. For this article, we are pleased to include insights from our colleagues at KLA-Tencor, John McCormack and Barry Saville. 

Semiconductors continue to grow in importance in the automotive supply chain, requiring IC manufacturers to adapt their processes to produce chips that meet automotive quality standards. The first article in this series1 focused on the fact that the same types of IC manufacturing defects that cause yield loss also cause poor chip reliability and can lead to premature failures in the field. To achieve the high reliability required in automotive ICs, additional effort must be taken to ensure that sources of defects are eliminated in the manufacturing process. The second article in this series2 outlined strategies, such as frequent tool monitoring and a continuous improvement program, that reduce the number of defects added at each step in the IC manufacturing process. This article explores how to drive tool monitoring to a higher level of performance in order to help automotive IC manufacturers achieve chip failure rates below the parts per billion level.

As a reminder, tool monitoring is the established best practice for isolating the source of random defectivity contributed by the fab’s process tools. During tool monitoring, a bare wafer is inspected to establish its baseline defectivity, run through a specific process tool (or chamber), and then inspected again. Any defects that were added to the wafer must have come from that specific process tool. This method can reveal the cleanest “golden” tools in the fab, as well as the “dog” tools that contribute the most defects and require corrective action. With plots of historical defect data from the process tools, goals and milestones for continuous improvement can be implemented.

When semiconductor fabs design their tool monitoring strategy, they must decide on the minimum size of defects that they want to detect and monitor. If historical test results have shown that smaller defects do not impact yield, then fabs will run their inspection tools at a lower sensitivity so that they no longer detect these smaller defects. By doing this, they can focus only on the larger yield-killer defects, avoiding distraction from the smaller “nuisance” defects. This approach works for a consumer fab that is only trying to optimize yield, but what about the automotive fab? Recall that yield and reliability issues are caused by the same defects types – yield and reliability defects differ only in their size and/or where they land on the device pattern.2 Therefore, a tool monitoring strategy that leaves the fab blind to smaller defects may be missing the very defects that will be responsible for future reliability issues.

Moreover, it’s important to understand that defects that seem small and inconsequential at one process layer may have a dramatic impact later in the process flow – their impact can be exacerbated by the subsequent process steps. The two SEM images in figure 1 were taken at exactly the same location on the same wafer, but at different steps of the manufacturing process. The image on the left shows a single, small defect that was found on the wafer after a deposition layer. This defect was previously thought to be a nuisance defect with no negative effect on the die pattern or chip performance. The image on the right shows that same deposition defect after metal 1 pattern formation. The presumed nuisance defect has altered the quality of the metal line printed several process steps later. This chip might pass electrical wafer sort, but this type of metal deformity could easily become a reliability issue in the field when activated by automotive environmental stressors.

Figure 1. The left image shows small particle created at a deposition layer. The right image shows the exact same location on the wafer after the metal 1 pattern formation. The metal line defect was caused by the small particle at the prior deposition layer. This type of deformity in the metal line could easily become a reliability issue in the field.

So how does an automotive IC fab determine the smallest defect size that will pose a reliability risk? To start, it is important to understand the impact of different defect sizes on reliability. Consider, for example, the different magnitudes of a line open defect shown in figure 2. A chip that has a pattern structure with a full line open will likely fail at electrical wafer sort and thus does not pose any reliability risk. A chip with a 50% line open – a line that is pinched or otherwise restricted to ~50% of its cross-sectional area – will likely pass electrical wafer sort but poses a significant reliability risk in the field. If this chip is used in a car, environmental conditions such as heat, humidity and vibrations, can cause degradation of this defect to a full line open, resulting in chip failure.

Figure 2. The image on the left shows a full line open, while the right image shows a ~50% line open. The chip on the left will fail at sort (assuming there is no redundancy). The chip on the right may pass electrical wafer sort but is a reliability risk in the field.

As a next step, it is important to understand how different size defects affect a chip’s pattern integrity. More specifically, what is the smallest defect that will result in a line open? What is the smallest defect that will result in a 50% line open?

Figure 3 shows the results of a Monte Carlo simulation that models the impact of different size defects introduced at a BEOL film deposition step. Minimum defect size is plotted on the vertical axis against varying metal layer pitch dimensions. This data corresponds to the metal 1 spacing for the 7nm, 10nm, 14nm and 28nm design nodes, respectively.

The green data points correspond to the smallest defects that will cause a full line open and the orange data points correspond to the smallest defects that will produce a 50% line open (i.e., a potential reliability failure). In each case the smallest defect that will cause a potential reliability failure is 50-75% of the smallest defect that will cause a full line open.

Figure 3. The green data points show the minimum defect size required to cause a full line open at the minimum metal pitch. The orange data points show the minimum defect size needed to cause a 50% line open. The x-axis is the metal 1 spacing for the 7nm (far left data point), 10nm, 14nm and 28nm (far right data point) design nodes.

These modeling results imply that to control for, and reduce, the number of reliability defects present in the process, fabs need to capture smaller defects. Therefore, they require higher sensitivity inspections than what is required for yield optimization. In general, detection of reliability defects requires an inspection sensitivity that is one node ahead of the current design node plan for yield alone. Simply put, a fab’s previous standards for reducing defectivity to optimize yield will not be sufficient to optimize reliability.

Increasing the sensitivities of the tool monitoring inspection recipes, or in some cases, using a more capable inspection system, will find smaller defects and possibly reveal previously hidden signatures of defectivity, as in Figure 4 below. While these signatures may have had a tolerable impact on yield in a consumer fab, they represent an unacceptable risk to reliability for automotive fabs pursuing continuous improvement and Zero Defect standards.

Figure 4: Hidden defect signatures that may impact reliability are often revealed with appropriate tool monitoring sensitivity. Zero Defect standards require corrective action on the process tool contributing these defects.

There are several important unpatterned wafer defect inspection factors for a fab to consider when creating a strategy to improve tool monitoring inspection sensitivity to find the small, reliability-related defects contributed by process tools. First, it is important to recognize that in a mature fab where yields are already high, there is rarely a single process layer or module that will be the “silver bullet” to reducing defectivity adequately to meet reliability improvement goals. Rather, it is sum of small gains across many layers that produce the desired gains in reliability. Because yield and the associated reliability improvements are cumulative across layers, reliability gains achieved through process tool monitoring using unpatterned wafer inspection are best demonstrated using a multi-layer regression model:

Yield = f(Ys)+f(SFS1)+f(SFS2)+ f(SFS3)+ ….. f(SFSN) + error

  • Ys = systematic yield loss (not particles related)
  • SFSx = cumulative Sursfcan unpatterned wafer inspection detected particles for many layers
  • Error = Yield loss mechanisms not detected by Surfscan

This implies that reliability improvements require a fab’s commitment to continuous improvement in defectivity levels across all processes and process modules.

Second, the fab should consider the quality of the bare wafer used for process tool monitoring. Recycling bare wafers increases the surface roughness with each cycle, an attribute known as haze. This haze level is fundamentally noise that affects the inspection system’s ability to differentiate the signal of smaller defects. Variability in haze across the population of test wafers acts as a limit to overall inspection recipe capability, requiring normalization, calibration and haze limits to reduce the impact of this noise source on defect sensitivity.

Next, the fab should ensure that the monitor step closely mimics the process that a production, patterned wafer follows. Small time-saving deviations in the monitor wafer flow to short cut the process may inadvertently skip the causal mechanism of defectivity. Furthermore, an over-reliance on mechanical handling checks alone bypasses the process completely and misses the critical contribution the process plays in particle generation.

When increasing the inspection recipe sensitivity, the fab must co-optimize both the “pre” and “post” inspection together. Often cycling the bare wafer through a process step can “decorate” small pre-existing defects on the wafer that were initially below the detection threshold. Once decorated, the defects now appear bigger and are more easily detected. In an unoptimized “post” inspection, these decorated defects can look like “adders,” leading to a false alarm and inadvertent process tool down time. Optimizing the inspections together maximizes the sensitivity and increases the confidence in the excursion alarms while avoiding time-consuming false alarms.

Lastly, it is important to review and classify the defects found during unpatterned inspection to correlate their relevance to the defects found at the equivalent patterned wafer process step. Only then can the fab be confident that the source of the defects has been isolated and appropriate corrective action has been taken.

To meet the high reliability demands of the automotive industry, IC manufacturers will need to go beyond simply monitoring and controlling the number of yield limiting defects on the wafer. They will need to improve the sensitivity of their tool monitoring inspections to one node smaller than what would historically be considered relevant. Only with this extra sensitivity can they detect and eliminate defects that would otherwise escape the fab and cause premature reliability failures. Additionally, when implementing a tool monitoring strategy, fabs need to carefully consider multiple factors, such as monitor wafer recycling, pre and post inspection sensitivity and the importance of a fab-wide continuous improvement program. With so much riding on automotive semiconductor reliability, increased sensitivity to smaller defects is an essential part of an optimal Zero Defect continuous improvement program.

About the Authors:

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including implementation of strategies for automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

John McCormack is a Senior Director at KLA-Tencor. Barry Saville is Consulting Engineer at KLA-Tencor. John and Barry both have over 25 years of experience in yield improvement and defectivity reduction, working with many IC manufacturers around the world.

References:

  1. Price, Sutherland and Rathert, “Process Watch: The (Automotive) Problem With Semiconductors,” Solid State Technology, January 2018.
  2. Price, Sutherland and Rathert, “Process Watch: Baseline Yield Predicts Baseline Reliability,” Solid State Technology, March 2018.

Layout schema generation generates random, realistic, DRC-clean layout patterns of the new design technology for use in test vehicles.

BY WAEL ELMANHAWY and JOE KWAN, Mentor Graphics, Beaverton, OR

Predicting and improving yield in the early stages of technology development is one of the main reasons we create test macros on test masks. Identifying potential manufacturing failures during the early technology development phase lets design teams implement upstream corrective actions and/or process changes that reduce the time it takes to achieve the desired manufacturing yield in production. However, while conventional yield ramp techniques for a new technology node rely on using designs from previous technology nodes as a starting point to identify patterns for design of experiment (DoE) creation, what do you do in the case of a new design technology, such as multi- patterning, that did not exist in previous nodes? The human designer’s experience isn’t applicable, since there isn’t any knowledge about similar issues from previous designs. Neither is there any prior test data from which designers can draw feedback to create new test structures, or identify process or design style optimizations that can improve yield more quickly.

An innovative new technology, layout schema gener- ation (LSG), enables design teams to generate additional macros to add to test structures without relying on past designs for input. These macros are based on the gener- ation and random placement of unit patterns that can construct more meaningful larger patterns. Specifications governing the relationships between those unit patterns can be adjusted to generate layout clips that look like realistic designs. Those layout clips can then be used in design of experiment (DoE) trials to predict yield, and identify potential design and process optimizations that will help improve yield. By using this new LSG process, designers can significantly reduce the time it takes to achieve the desired yield for designs that include new design techniques.

Issues affecting yield

Wafer yield is typically reduced by three categories of defects. The first category comprises random defects, which occur due to the existence of contamination particles in the different process chambers. A conducting particle can short out two or more neighboring wires, or create a leakage path. A non-conducting particle or a void can open up a wire or a via, or create high resistive paths. FIGURE 1 shows scanning electron microscope (SEM) images of these two types of random defects.

The second category contains systematic defects, which occur due to an imperfect physical layout architecture, or the impact of non-optimized optical process recipes and/ or equipment. Systematic defects are typically the biggest source of yield detraction [1], but a majority of them can be eliminated through design-technology co-optimization (DTCO), in which the design and process sides commu- nicate more freely to achieve faster rates of improvement.

The third category, which we’re not addressing in this article, includes parametric defects (such as a lack of uniformity in the doping process) that may affect the reliability of devices.

Layout schema generation

To demonstrate the use and applicability of the LSG process, let’s look at designs that use the self-aligned multi-patterning (SAMP) process. Multi-patterning (MP) technology with ArF 193i lithography is currently the preferred choice over extreme ultraviolet (EUV) lithography for advanced technology nodes from 20nm on down. At 7 nm and 5 nm nodes, the SAMP process appears to be one of the most effective MP techniques in terms of achieving a small pitch of printed lines on the wafer, but its yield is in question. Of course, before being deployed in production, it must be thoroughly tested on test vehicles. However, without any previous SAMP designs, design of an appropriate test vehicle is challenging. In addition to the lack of historical test data, the unidirectional nature of the SAMP design complicates the design of the conven- tional serpentine and comb test shapes, which contain bidirectional components.

Self-aligned multi-patterning process

In the SAMP process [3], the first mask is known as the mandrel mask. Sacrificial mandrel shapes are printed with a relaxed pitch, and then used to develop sidewalls. The sidewalls are at half the mandrel’s pitch. Depending on the tone, target shapes may exist in the spaces between the sidewalls. The target shapes can be reused as sacrificial mandrel shapes to form another generation of sidewalls. Wafer shapes that don’t have corresponding mask shapes are called non-mandrel shapes. This process can be repeated to achieve SAMP layouts with a reduced pitch. The SAMP process (FIGURE 2) restricts the designs to be almost unidirectional. Generated parallel lines will be cut later by a cut mask at the desired line ends to form the correct connectivity.

Test vehicles

A test vehicle is typically a subset of the masks for a design, designed specifically to induce potential systematic failures or lithographic hotspots on the layer under test. It may also contain some test structures specially designed for the detection of random defects. The main compo- nents in a test vehicle for any new node are serpentine and comb shapes (to capture random defects), and preliminary standard cell designs (with many variations, to assess their quality). Other structures are typically added based on experience derived from production chips of previous nodes.

In a new node, all test structures on the test vehicle are vital for process training and characterization. Feedback from the test process is used for design style optimization. For example, when “bad” layout geometries are discovered after manufacturing, they can be captured as patterns, assigned low scores, and stored in a design for manufacturing (DFM) pattern library [2]. The designer can then use DFM analysis to find the worst patterns in a given layout, and modify or eliminate them. Such early DTCO provides a faster yield ramp for new nodes. Even in mature nodes, test structures are used on production wafers to identify additional opportunities for process refinement and optimization, which will have a positive impact on future yield.

One of the obstacles in test vehicle design is that it depends mainly on human designer’s experience and memory. Although experienced designers have seen multiple design styles in older nodes, the design shapes they are familiar with are limited to those styles. It typically takes a long time to design new test structures that cover new shapes, especially for a new process. The LSG solution adds more macros (generated in a random fashion) to the standard test structures strategy to speed up new shape yield analysis.

Random test pattern generation

The key component of the LSG solution is a method for the random generation of realistic design-like layouts, without design rule violations. The LSG process uses a Monte Carlo method to apply randomness in the generation of layout clips by inserting basic unit patterns in a grid. These unit patterns represent simple rectangular and square polygons, as well as a unit pattern for inserting spaces in the design. Unit pattern sizes depend on the technology pitch value. During the generation of the layouts, known design rules are applied as constraints for unit pattern insertion. Once the rules are configured, an arbitrary size of layout clips can be generated (FIGURE 3).

To begin, the SAMP design rules are converted to a format readable by an automated LSG tool like the Calibre® LSG tool from Mentor, a Siemens Business. Once the rules are configured, the Calibre LSG process can automatically generate an arbitrarily wide area of realistic DRC-clean SAMP patterns. The area is only limited by the floorplan of the designated macro of SAMP test structures. Test patterns can be also generated with power rails to mimic the layouts of standard cells. FIGURE 4 shows a sample clip of the generated output layout. To be ready for the experiments, the SAMP design is decomposed into the appropriate mandrel and cut masks, according to the decomposition rules. This operation also distinguishes between mandrel and non-mandrel shapes.

Design of Experiment

In the design phase of the test vehicle, the generated SAMP patterns are added to the typical contents of regular test patterns. The random SAMP patterns are electrically meaningless, unless they are connected to other layers to set up the required experiment. The DoE determines the way the connections are made from the patterns up to the testing pads, to detect different fail modes. Fail modes include short circuits due to lithographic bridging or conducting particles, and open circuits due to lithographic pinching, non-conducting particles, voids, or open vias.

A via chain can be constructed to connect the random DoE of SAMP structures through a routing layer to external pads for electrical measurement. These clips are decomposed according to the decomposition rules of the technology into the appropriate mandrel and cut masks. The decomposed clips can be tested through simulations, or electrically on silicon to discover hotspots. The discovered hotspots can be analyzed to determine root cause, which can be used to modify design layouts and/or optimize the fabrication process and models to eliminate these hotspots in future production. They can also be used as learning patterns for DFM rule deck devel- opment. By expanding the size of the randomly generated test structures, more hotspots can be detected, which can provide an even faster way to enhance the yield of a new technology node.

To demonstrate the effectiveness of the LSG process, we performed two experiments on a set of SAMP patterns similar to those shown in FIGURE 4.

Detecting random conducting particles

The first experiment collected data about random defects caused by conducting particles. In this experiment, all mandrel shapes are connected through the upper (or lower) via and metal layers, up to a testing pad. All non-mandrel shapes are connected in the same way to another testing pad. The upper routing layer forms two interdigitated comb shapes. FIGURE 5 shows a layout snippet of the connections. All via placements and upper metal routings were made with a custom script, without the intervention of a human designer. Ideally the two testing pads should be disconnected, as no mandrel shape can touch a non-mandrel shape. If the testing probes are found to be connected, this likely indicates a random conducting particle defect, or a lithographic bridge. The localization and analysis of such defects [4] can help with yield estimation and enhancement.

Detecting systematic cut mask resolution problems

One example of a systematic lithographic defect found in SAMP designs is when the cut mask is not resolved correctly. This causes two shapes on the same track to be shorted out through the unresolved cut shape. The testing of such a case requires connecting every other polygon on the same track. This was done with a generating script, without the intervention of human designers. FIGURE 6 shows a snippet of the generated layout with the connections. If the test probes are found to be connected while the two pads (ideally) are disconnected, this may indicate an unresolved cut shape. The analysis of the defect location and data from multiple wafers can prove the root cause of the defect.

Results

The two experiments described above were placed on a test vehicle of an advanced node. The test macro containing the first experiment setup successfully detected several conducting particle defects. A sample SEM image of the discovered defect is shown in FIGURE 7. Statistical data from multiple wafers were used to model the defect density and estimate the yield target.

Repetitive fail data from the test macro of the second experiment indicated systematic failures at particular locations. The analysis showed that the root cause of the failure was a poorly resolving cut shape in some process corners, as was predicted in the DoE. FIGURE 8 shows a snippet of the generated layout and its contour simulation.

To test the effectiveness of the random approach in capturing defects, 20 SAMP design clips were generated with linearly increasing sizes, such that the 20th clip was 20X bigger than the first clip. Lithography simulations were executed on the cut mask to inspect potential failures. The contours were checked, and potential failures were identified and categorized. FIGURE 9 shows the number of the unique hotspots found in each clip. The graph shows that the number of identified hotspots tends to saturate with the chip size. The second clip has 2X the number of unique hotspots found in the first clip, while the 20th clip only sees around a 6X increase. This result is expected, as many hotspots in the larger clips are just replicas of those found in the small clips. Assuming that the LSG tool is configured correctly, this result means most of the potential hotspots can be covered in a reasonable size test vehicle.

Conclusion

Test vehicles are vital for yield ramp up in new technologies and yield enhancement in mature nodes, but it can be difficult to design accurate test structures for new design styles and technologies that have no relevant history. Innovative techniques are needed to achieve comprehensive coverage of potential manufacturing failures created by new design styles, while ensuring full compliance with known design rule checks. A new solution using layout schema generation generates random, realistic, DRC-clean layout patterns of the new design technology for use in test vehicles. Experiments with this technology show it can provide high coverage of new design styles for an arbitrarily-wide design area. Circuitry can be added to the generated clips to make them electrically measurable for the detection of potential failures. The ability to discover lithographic hotspots and systematic failures early in the technology development process is significantly improved, at the expense of additional testing area. This design/technology co-optimization speeds up the yield optimization for new technology nodes, improving a critical success factor for market success.

References

1. Lee, J.H., Lee, J.W., Lee, N.I., Shen, X., Matsuhashi, H., Nehrer, W., “Proactive BEOL yield improvement methodology for a successful mobile product,” Proc. IEEE ISCDG, 93-95 (2012).
2. Park, J., Kim, N., Kang, J.-H., Paek, S.W., Kwon, S., Shafee, M., Madkour, K., Elmanhawy, W., Kwan, J., et al., “High coverage of litho hotspot detection by weak pattern scoring,” Proc. SPIE 9427, 942703 (2015)
3. Bencher, C., Chen, Y., Dai, H., Montgomery, W., Huli, L., “22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP),” Proc. SPIE 6924, 69244E (2008)
4. Schmidt, M., Kang, H., Dworkin, L., Harris, K., Lee, S., “New methodology for ultra-fast detection and reduction of non-visual defects at the 90nm node and below using comprehensive e-test structure infrastructure and in-line DualBeamTM FIB,” IEEE/ SEMI ASMC, 12-16 (2006).

Source Photonics, a global provider of optical transceivers, today announced it recently closed more than $100M in equity to support its growing data center and 5G business.

The funding will be used to further increase the scale of Source Photonics’ operations, as LightCounting reported that the sales of optical components and modules to Cloud Companies grew by 63% in 2016 and 64% in 2017. The growth rate will average roughly 20% per year through 2023. Higher growth rates in 2020-2022 will be driven by first volume deployments of 400GbE. This is a result of the rise of 5G and the cloud.

Planned developments include the creation of a new laser fab, upgrades to existing production facilities and increased investment in the research and development of next-generation technologies, ensuring Source Photonics continues its position as a leading innovator.

“Exciting new applications such as the Internet of Things (IoT), Virtual Reality, and cloud services are growing in popularity every day,” said Doug Wright, CEO at Source Photonics. “These applications all depend on the next standard of connectivity, and 5G depends on the backing of a world-class optical network. We are extremely proud that our investors have shown this confidence in us and are confident that the investment will support our ongoing work to enable the next era of connectivity.”

Upgrades to Source Photonics’ fab in Taiwan have already been completed and production operations have begun for a new fab in Jintan, China, using the latest funding. The funding will also be used towards technology investments for advanced coating technologies to enable next-generation lasers and transceivers for the fast-growing 5G and data center markets.

Source Photonics’ latest range of cutting-edge technology will be exhibited at OFC 2019 at booth 4021. Products on display will include its new 400G-LR8 and DR4 QSFP-DD solutions, which are the latest addition to its PAM4-based optical transceivers portfolio. Other products which will be showcased at OFC, in San Diego, on March 4-7, 2019, include several QSFP28 solutions such as the 100G-DR/FR, 100G-SR4, 100G CWDM4, and 100G-LR4. The company will also demonstrate some of its solutions for the 5G market such as the 50G-ER QSFP28 and 25G LAN DWM SFP28.

The IC industry has been on a mission to pare down older capacity (i.e., ≤200mm wafers) in order to produce devices more cost-effectively on larger wafers.  In its recently released Global Wafer Capacity 2019-2023 report, IC Insights shows that due to the surge of merger and acquisition activity in the middle of this decade and with more companies producing IC devices on sub-20nm process technology, suppliers are eliminating inefficient wafer fabs. Over the past ten years (2009-2018), semiconductor manufacturers around the world have closed or repurposed 97 wafer fabs, according to findings in the new report.

Figure 1 shows that since 2009, 42 150mm wafer fabs and 24 200mm wafer fabs have been shuttered. 300mm wafer fabs have accounted for only 10% of total fab closures since 2009.  Qimonda was the first company to close a 300mm wafer fab after it went out of business in early 2009.

Figure 1

Three 150mm wafer fabs were closed or repurposed in 2018.  Two of these fabs belonged to Renesas.  Renesas closed one fab in Konan, Kochi, Japan that produced analog, logic, and some older microcomponent devices.  A second Renesas fab in Otsu, Shiga, Japan was repurposed and now makes only optoelectronic devices.  A third fab, Fab 1 belonging to Polar Semiconductor (now Sanken) in Bloomington, Minnesota, also was closed.  This fab manufactured analog, discretes, and offered some foundry services.

Given the skyrocketing cost of new wafer fabs and manufacturing equipment, and as more IC companies transition to a fab-lite or fabless business model, IC Insights anticipates there will be additional fab closures in the next few years.  Five closures/repurposed fabs have already been publicly announced. Samsung’s 300mm memory fab (Line 13) will be fully converted this year to produce image sensors and TI’s 200mm analog GFAB in Greenock, Scotland, is expected to close by June 2019.  Renesas plans to close two 150mm fabs (Otsu, Shiga and Ube, Yamaguchi, Japan) in 2020 or 2021, and Analog Devices plans to close its 150mm wafer fab in Milpitas, California in February 2021.

Semiconductor suppliers in Japan have closed a total of 36 wafer fabs since 2009, more than any other country/region.   In the same period, 31 fabs were closed in North America, 18 fabs were shuttered in Europe, and 12 wafer fabs were closed throughout the Asia-Pacific region (Figure 2).  With 36 fab closures and very few new fabs going up there, it is little wonder that Japan now accounts for only 5% of worldwide semiconductor capital spending.

Figure 2

ON Semiconductor (Nasdaq: ON) today announced its top distribution partners for 2018. These awards honor the distributor in each region that led overall channel sales, grew market share, captured increased sales of products and scored highly on overall process excellence in an evolving semiconductor market.

The top 2018 distribution partners are:

  • Americas: Future Electronics
  • APAC: WPI
  • EMEA: Avnet/Silica
  • Japan: OS Electronics
  • Global High Service Distributor: Mouser Electronics
  • Global Distributor: Avnet

ON Semiconductor is an industry leader in leveraging partnerships in the global distribution channel. Approximately 60 percent of the company’s business results from distribution sales, and distribution remains the fastest channel to market. Over the past few years, ON Semiconductor has grown distribution sales, which has attributed to over half of the company’s revenue dating back to 2015.

“Distribution sales accounted for approximately 60 percent of ON Semiconductor’s 2018 annual revenues,” said Jeff Thomson, vice president of global channel sales for ON Semiconductor. “The support of our worldwide distribution partners is fundamental to the success of our company’s ongoing plans to increase market penetration and continue revenue growth at a faster pace than the industry. The collaborative relationships and progressive sales programs we foster with our channel partners are an integral part of comprehensive solution selling. As advocates of these goals, each of the 2018 distribution partner award winners successfully grew product sales, generated significant new business, and effectively supported both our customers’ needs and our company initiatives for operational excellence. We thank our outstanding channel partners for their valuable contributions throughout 2018 and look forward to continued success in the coming year.”

In the third quarter of 2018, ON Semiconductor announced a monumental milestone in the company’s history by reaching over $1 billion in distribution resales. ON Semiconductor distribution partners, and this year’s honorees, have been instrumental to this tremendous milestone. In addition to this accomplishment, ON Semiconductor was recognized in 2018 as a Fortune 500 company, was named as one of Fortune’s 100 Fastest Growing Companies, was listed on the Dow Jones Sustainability Index and received recognition from Ethisphere for the fourth year in a row as one of the World’s Most Ethical Companies.

By Serena Brischetto

The SEMI Europe Industry Strategy Symposium (ISS Europe) returns in Milan, Italy, this year from 31st March to 2nd April, 2019 to explore new opportunities and challenges in the digital economy. Serena Brischetto of SEMI spoke with GreenWaves Technologies CEO and co-founder Loïc Lietar about the semiconductor start-up and its Internet of Things (IoT) ultra-low-power processing technology ahead of the summit.

SEMI: What are the mission and vision of GreenWaves Technologies?

Lietar: GreenWaves Technologies is a fabless semiconductor start-up that is designing disruptive ultra-low power embedded solutions for image, sound and vibration artificial intelligence (AI) processing in sensing devices. It was founded in late 2014 with the mission to enable the market for intelligent in-device sensors using ultra-low energy and cost-efficient computing solutions. As a result, the GreenWaves GAP8 is the industry’s first ultra-low-power processor to enable battery-operated AI in Internet of Things (IoT) applications.

SEMI: How did you move from the semiconductor industry to the start-up ecosystem?

Lietar: I worked 25 years for STMicroelectronics then four years ago left because a project didn’t materialize. At the same time, I became involved a bit by chance in the founding of GreenWaves, which turned out to be an amazing journey that I rapidly got entirely – and deadly – committed to.

SEMI: Semiconductors are usually not associated with the idea of start-up. What is the key to the success of GreenWaves and its positioning?

Lietar: Start-ups have played a significant role in the formation of our industry and in bringing innovations and disruptions to the market. But as it became more complicated to finance start-ups because of exploding development costs, the number of semiconductor start-ups shrank significantly in the past 10 years.

At GreenWaves we develop and sell IoT application processors – processors tuned for a given class of applications. In our case, we focused on machine learning inference processors and more generally signal processing and IoT for ultra-low power. We typically process and analyze images, sounds and vibrations and our technology is more than one order of magnitude more energy efficient than existing processors. For example, our processor, coupled with an infra-red sensor, can count the number of people present in a room once a minute for more than five years on a single charge.

Our architecture uses RISC-V cores. This free and open Instruction Set Architecture is seeing huge momentum and a rapidly growing community. Second, we leverage an open source project called PULP developed by the Italian Università di Bologna and the Federal Polytechnical School ETH in Zurich. While open source is a well-established model for software, this is pretty unchartered territory in the semiconductor industry. It is working very well for us, as we benefit from robust technology we can incrementally innovate on. This is why we have been able to develop our first product with 4 million Euro.

Competition is now emerging, and this is a good sign: We are not alone in believing in this market but we remain very differentiated!

SEMI: One of the reasons why semiconductor start-ups were no longer attractive to VCs is the amount of capital that start-ups need to invest. Did public funding help you too?

Lietar: Yes, public funding played a crucial role at the beginning. We received rather classically 300K Euro of French grants and then we were lucky enough to win a very selective H2020 grant, the SME instrument, for 1.2M€. In France there is a very powerful scheme of research tax credit that covers more than 30 percent of our R&D costs and French banks know how to lend money to start-ups, with a state warranty.

Source: SEMI Blog

SEMI, the global industry association serving the electronics manufacturing supply chain, today announced SEMI Works, a comprehensive program to attract, develop and retain the talent critical to the worldwide electronics industry’s continued innovation and growth. The holistic program is designed to improve the industry’s image and provide educational programs for all age groups across the education continuum.

“SEMI has made workforce development and talent advocacy a top priority and dedicated significant resources and expertise to tackle the issue,” said Ajit Manocha, SEMI president and CEO. “As the global industry association anchoring the $2 trillion global electronics industry and representing the end-to-end semiconductor supply chain, SEMI is uniquely positioned to address this problem. We look forward to forming partnerships in leading the way on behalf of our members to build the workforce of the future.”

SEMI Works leverages the SEMI association’s proven track record developing and delivering education and workforce development initiatives as well as its rich history of building public-private partnerships. Under the program, SEMI will establish scalable and sustainable education programs extending from grade-schoolers to adults, offering experiential learning and training programs linked to the skill sets the industry needs most.

“Attracting, training and retaining talent is a major priority for our industry, and we applaud SEMI for taking a lead in workforce development,” said Dan Durn, senior vice president and CFO of Applied Materials, Inc. “SEMI is in a great position to mobilize the right resources and drive the success of this important initiative.”

Leading SEMI Works is Mike Russo, vice president of Global Industry Advocacy at SEMI. Russo brings to bear his more than two decades of talent development experience working with the public and private sectors.

“The global electronics industry’s shortage of high-skilled workers will only become more severe as technology advances,” Russo said. “We need a highly skilled workforce throughout the supply chain to develop new technologies and bring these advances to market. SEMI Works™ will be anchored by both detailed competency models continually updated to support the industry’s rapidly evolving workforce needs and certified education and training aligned to these competencies. This systematic approach will enable us to develop the talent vital to the industry’s prosperity.”

With SEMI Works, SEMI is building on its growing suite of workforce initiatives and involving a consortium of member companies along with its strategic alliances. The program will expand to include public and private sector partners. Organizations interested in contributing to SEMI Works should visit the SEMI Works webpage for program manager contact details.

The advancement of the IC industry hinges on the ability of IC manufacturers to continue offering more performance and functionality for the money.  As mainstream CMOS processes reach their theoretical, practical, and economic limits, lowering the cost of ICs (on a per-function or per-performance basis) is more critical and challenging than ever. The 500-page, 2019 edition of IC Insights’ McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry (released in January 2019) shows that there is more variety than ever among the logic-oriented process technologies that companies offer.  Figure 1 lists several of the leading advanced logic technologies that companies are presently using. Derivative versions of each process generation between major nodes have become regular occurrences.

Figure 1

Intel — Its ninth-generation processors unveiled in late 2018 have the code-name “Coffee Lake-S” or, sometimes called “Coffee Lake Refresh.” Intel says these processors are a new generation of products, but they seem to be more of an enhancement of the eighth-generation products.  Details are scarce, but these processors appear to be manufactured on an enhanced version of the 14nm++ process, or what might be considered a 14nm+++ process.

Mass production using its 10nm process will ramp in 2019 with the new “Sunny Cove” family of processors that it unveiled in December 2018.  It appears that the Sunny Cove architecture has essentially taken the place of the 10nm Cannon Lake architecture that was supposed to be released in 2019.  In 2020, a 10nm+ derivative process is expected to go into mass production.

TSMC — TSMC’s 10nm finFET process entered volume production in late 2016 but it has moved quickly from 10nm to 7nm.  TSMC believes the 7nm generation will be a long-lived node like 28nm and 16nm.

TSMC’s 5nm process is under development and scheduled to enter risk production in the first half of 2019, with volume production coming in 2020.  The process will use EUV, but it will not be the first of TSMC’s processes to take advantage of EUV technology.  The first will be an improved version of the company’s 7nm technology.  The N7+ process will employ EUV only on critical layers (four layers), while the N5 process will use EUV extensively (up to 14 layers).  N7+ is scheduled to enter volume production in the second quarter of 2019.

Samsung — In early 2018, Samsung started mass production of a second-generation 10nm process called 10LPP (low power plus). Later in 2018, Samsung introduced a third-generation 10nm process called 10LPU (low power ultimate) that provided another performance increase.  Samsung uses triple patterning lithography at 10nm.  Unlike TSMC, Samsung believes its 10nm family of processes (including 8nm derivatives) will have a long lifecycle.

Samsung’s 7nm technology went into risk production in October 2018.  The company skipped offering a 7nm process with immersion lithography and decided instead to move directly to a EUV-based 7nm process.  The company is using EUV for 8-10 layers at 7nm.

GlobalFoundries — GF views and markets its 22nm FD-SOI process as being complementary to its 14nm finFET technology.  The company says the 22FDX platform delivers performance very close to that of finFET, but with manufacturing costs the same as 28nm technology.

In August 2018, GlobalFoundries made a major shift in strategy by announcing it would halt 7nm development because of the enormous expense in ramping production at that technology node and because there were too few foundry customers planning to use the next-generation process.  As a result, the company shifted its R&D efforts to further enhance its 14nm and 12nm finFET processes and its fully depleted SOI technologies.

For five decades, there have been amazing improvements in the productivity and performance of integrated circuit technology.  While the industry has surmounted many obstacles put in front of it, it seems the barriers keep getting bigger.  Despite this, IC designers and manufacturers are developing solutions that seem more revolutionary than evolutionary to increase chip functionality.

Graphene Flagship researchers solved one of the challenges of making graphene nano-electronics effective: to carve out graphene to nanoscale dimensions without ruining its electrical properties. This allowed them to achieve electrical currents orders of magnitude higher than previously achieved for similar structures. The work shows that the quantum transport properties needed for future electronics can survive scaling down to nanometric dimensions.

Lithographically carved nanographene yields outstanding electrical properties. Credit: Carl Otto Moesgaard

Since its inception, scientists have tried to exploit graphene to produce nano-sized electronics. However, since graphene is only an atom thick, all atoms are exposed to the outside world, and even small amounts of defects and impurities impede its properties. Now, Graphene Flagship researchers at DTU, Denmark solved this problem by protecting graphene with insulating layers of hexagonal boron nitride, another two-dimensional material with insulating properties.

Peter Bøggild, researcher at Graphene Flagship partner DTU and coauthor of the paper, explains that although ‘graphene is a fantastic material that could play a crucial role in making new nano-sized electronics, it is still extremely difficult to control its electrical properties.’ Since 2010, scientists at DTU have tried to tailor the electrical properties of graphene, by making a very fine pattern of holes, so that channels through which an electric power can flow freely are formed. ‘Creating nanostructured graphene turned out to be amazingly difficult, since even small errors wash out all the properties we designed it to have,’ comments Bøggild.

Now, researchers from Graphene Flagship partner DTU made a leap forward. Bjarke Jessen and Lene Gammelgaard encapsulated graphene with another 2D material, hexagonal boron nitride, which is very similar to graphene, but electrically insulating. Then, using nanolithography, they carefully drilled nanoscopic holes in graphene through the protective layer of boron nitride. The holes have a diameter of approximately 20 nanometers, and are separated from each other with just 12 nanometers. This great precision makes possible to send an electrical current through the graphene that is 100-1000 times higher than typical numbers for lithographically carved nanographene.

‘When you make patterns in a material like graphene, you do so in order to change its properties. However, what we have seen throughout the years is that when we shape graphene on this fine scale, it does not behave like graphene anymore – there is too much disorder,’ explains Bøggild. ‘Many scientists have abandoned nanolithography in graphene on this scale, but now we have figured out how it can be done – you could say that the curse is lifted,’ he adds.

‘We have shown that we can control graphene’s band structure and that deterministic design of nanoelectronics is realistic. Looking solely at electronics, this means that we can make insulators, transistors, conductors and perhaps even superconductors, as our nanolithography can preserve the subtle inter-layer physics that was recently shown to lead to superconductivity in double-layer graphene. However, it goes way beyond that. When we control the band structure, we have access to all of graphene’s properties. In other words, we could sit in front of the computer and dream up other applications – and then go to the laboratory and make them happen,’ says Bøggild. ‘There are plenty of practical challenges, but the fact that we can tailor electronic properties of graphene is a big step towards creating new electronics with extremely small dimensions,’ he concludes.

Daniel Neumaier, Graphene Flagship Division Leader for Electronics and Photonics Integration says: ‘Controlling the electronic properties of graphene by nano-pattering offers an additional degree of freedom for the design of electronic and photonic devices, which was so far not accessible. The researchers from Graphene Flagship partner DTU and their co-workers now discovered a unique way for nano-patterning of graphene without seeing the limitations of patterning introduced defects. This was the key enabling step for using the nano-patterning induced electronic properties of graphene in real device and we are expecting significant advances especially for nano-electronics and photonics based on these results.’

Andrea C. Ferrari, Science and Technology Officer of the Graphene Flagship and Chair of its Management Panel added how ‘patterning of graphene to create nano-electronic devices was one of the first approaches attempted to exploit this unique material into devices. However, after an initial flurry of publications, the amount of damage produced was so much that this line of research was almost entirely abandoned. The work presented here shows how the long term nature of the Flagship allows scientists to pursue and solve even apparently intractable problems. This will rejuvenate the interest in graphene nanoelectronics, and could lead to a variety of useful devices, previously hampered by defects.’

GLOBALFOUNDRIES today announced that the company’s mobile-optimized 8SW RF SOI technology platform has delivered more than a billion dollars of client design win revenue since its launch in September 2017. With yields and performance exceeding client expectations, 8SW is enabling designers to develop solutions that offer extremely fast downloads, higher quality connections and reliable data connectivity for today’s 4G/LTE Advanced operating frequencies and future sub-6 GHz 5G mobile and wireless communication applications.

As the industry’s first 300mm RF SOI foundry solution, 8SW delivers significant performance, integration and area advantages, with best-in-class low-noise amplifier (LNA) and switch performance which all together improve integration solutions in the front-end module (FEM). The optimized RF FEM platform is tailored to accommodate aggressive LTE and sub-6 GHz standards for FEM applications, including 5G IoT, mobile device and wireless communications.

“At Qorvo, we continuously expand upon our industry-leading RF portfolio to support all pre-5G and 5G architectures, as such we require the best available technologies to enable us to deliver top-notch solutions with the broadest range of connectivity in sub-6 GHz and mmWave 5G,” said Todd Gillenwater, Qorvo CTO. “GF’s 8SW technology delivers a mix of performance, integration and area advantages in FEM switches and LNAs, giving us a great platform for our world-class products.”

“As new high-speed standards, including 4G LTE and 5G, continue to grow in complexity, innovation in RF Front End radio design must continue to deliver performance commensurate with growing network, data and application demands,” said Bami Bastani, senior vice president of business units at GF. “GF continuously builds on our extensive RF SOI capabilities that are providing our clients a competitive market advantage with first time design success, optimal performance, and the shortest time to market.”

According to Mobile Experts, the mobile RF front-end market is estimated to reach $22 billion in 2022, with a CAGR of 8.3 percent. With more than 40 billion RF SOI chips shipped thru 2018, GF is uniquely positioned to deliver an expanding RF portfolio for a broad range of high-growth applications such as automotive, 5G connectivity and the Internet of Things (IoT).

“Radio complexity promises to increase for both sub-6 GHz and mmWave, driving tight integration of multiple RF functions,” said Joe Madden, Principal Analyst at Mobile Experts. “The market needs RF solutions with high efficiency and linearity performance, but also using scalable processes on large wafers. GF has established an RF SOI process that will enable longer-term market expansion.”

GF combines legacy RF expertise and the industry’s most differentiated RF technology platform spanning advanced and established technology nodes, to help clients develop 5G connectivity solutions for next-generation products.

GF will present its 5G-ready RF solutions with industry experts at MWC Barcelona on February 25 at the NEXTech Labs Theater, in the Fira Gran Via Convention Center, in Barcelona Spain. For more information, go to globalfoundries.com.