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To scale down a transistor below a 5nm node is one of the vital concerns for VLSI industry as there are various challenges due to the shrinking of components. Several researches are going on worldwide to overcome the challenges of future technology nodes. Among them, this article reviews the potential transistor structures and materials like Carbon Nano-tube FET, Gate-All-Around FET, and Compound Semiconductors as solutions to overcome the problems of scaling the existing silicon FinFET transistor below 5nm node.

By Pavan H Vora, Akash Verma, Dhaval Parikh

The ‘Semiconductor era’ started in 1960 with the invention of the integrated circuit. In an integrated circuit, all the active-passive components and their interconnection are integrated on a single silicon wafer, offering numerous advantages in terms of portability, functionality, power, and performance. The VLSI industry is following Moore’s law for many decades, which says, “the number of transistors on a chip becomes double approximately every two years”. To get the benefits of a scaled-down transistor, VLSI industry is continuously improving transistor structure and material, manufacturing techniques, and tools for designing IC. Various techniques, which have been adopted for transistors so far, include high-K dielectric, metal gate, strained silicon, double patterning, controlling channel from more than one side, silicon on insulator and many more techniques. Some of these techniques are discussed in ‘A Review Paper on CMOS, SOI and FinFET Technology’[1].

Nowadays, the demand of the internet of things, autonomous vehicles, machine learning, artificial intelligence, and internet traffic is growing exponentially, which acts as a driving force for scaling down transistor below the existing 7nm node for higher performance. However, there are several challenges of scaling down a transistor size.

Issues with Sub-Micron Technology:

Every time we scale down a transistor size, a new technology node is generated. We have seen transistor sizes such as 28nm, 16nm, etc. Scaling down a transistor enables faster switching, higher density, low power consumption, lower cost per transistor, and numerous other gains. The CMOS (complementary metal-oxide-semiconductor) transistor base IC technology performs well up to 28nm node. However, the short channel effects become uncontrollable if we shrink down CMOS transistor below 28 nm. Below this node, a horizontal electric field generated by drain-source supply tries to govern the channel. As a result, the gate is unable to control leakage paths, which are far from the gate.

16nm/7nm Transistor Technology: FinFet and FD-SOI:

The VLSI industry has adopted FinFET and SOI transistor for 16nm and 7nm nodes, as both the structures are able to prevent the leakage issue at these nodes. The main objective of both the structures is to maximize gate-to-channel capacitance and minimize drain-to-channel capacitance[1]. In both transistor structures, the channel thickness scaling is introduced as the new scaling parameter. As the channel thickness is reduced, there are no paths, which are far from the gate area. Thus, gates have a good control over the channel, which eliminates short channel effects.

In Silicon-on-Insulator (SOI) transistor, a buried oxide layer is used, which isolates the body from the substrate shown in Figure 1(a).Owing to the BOX layer, drain-source parasitic junction capacitances are reduced, which results in faster switching. The main challenge with the SOI transistor is that it is difficult to manufacture a thin silicon layer on the wafer.

Figure 1: a) FD-SOI Structure b) FinFET Structure and Channel

FinFET, which is also called as tri-gate controls channel is shown from three sides in Figure 1(b).  There is a thin vertical Si-body, which looks like a back fin of fish wrapped by the gate structure. A width of the channel is almost two times Fin height. Thus, to get higher driving strength, a multi-Fin structure is used. One of the gains with FinFET is higher driving current. The main challenge with FinFET is the complex manufacturing process.

Challenges with Technology Node below 5nm: What Next?

Reducing the body thickness results into lower mobility as surface roughness scattering increases. Since FinFET is a 3-D structure, it is less efficient in terms of thermal dissipation. Also, if we scale down the FinFET transistor size further, say below 7nm, the leakage issue becomes dominant again. Consequently, many other problems come into consideration like self-heating, threshold flattening, etc. These concerns lead to research on other possible transistor structures and replacing existing materials with new effective materials.

According to the ITRS roadmap (International Technology Roadmap for Semiconductors), the next technology nodes are 5nm, 3nm, 2.5nm, and 1.5nm. Many different types of research and studies are going on in VLSI industry and academia for potential solutions to deal with these future technology nodes. Here we discuss some promising solutions like carbon nanotube FET, GAA transistor structure, and compound semiconductor for future technology nodes.

Figure 2: Transistor Technology Roadmap

CNTFET – Carbon Nano Tube FET:

CNT (Carbon Nanotube) showcases a new class of semiconductor material that consists of a single sheet of carbon atoms rolled up to form a tubular structure. CNTFET is a field-effect transistor (FET) that uses semiconducting CNT as a channel material between the two metal electrodes, which behave as source and drain contacts. Here we will discuss carbon nanotube material and how it is beneficial to FET at a lower technology node.

  • What is a Carbon Nanotube?

CNT is a tubular shaped material, made of carbon, having diameters measurable on the nanometer scale. They have a long and hollow structure and are formed from sheets of carbon that are one atom thick. It is called “Graphene”. Carbon nanotubes have varied structures, differing in length, thickness, helicity, and the number of layers. Majorly, they are classified as Single Walled Carbon Nanotube (SWCNT) and Multi-Walled Carbon Nanotube (MWCNT). As shown in Figure 3(a), one can see that SWCNTs are made up of a single layer of graphene, whereas MWCNTs are made up of multiple layers of graphene.

Figure 3: a) Single Walled and Multi Walled CNTs b) Chirality Vector Representation

  • Properties of Carbon Nanotube:

The carbon nanotube delivers excellent properties in areas of thermal and physical stability as discussed below:

  1. Both Metallic and Semiconductor Behavior

The CNT can exhibit metallic and semiconductor behavior. This change in behavior depends on the direction in which the graphene sheet is rolled. It is termed as chirality vector. This vector is denoted by a pair of integer (n, m) as shown in Figure 3(b). The CNT behaves as metallic if ‘n’ equals to ‘m’ or the difference of ‘n’ and ‘m’ is the integral multiple of three or else it behaves as a semiconductor [2].

  1. Incredible Mobility

SWCNTs have a great potential for application in electronics because of their capacity to behave as either metal or as a semiconductor, symmetric conduction and their capacity to carry large currents. Electrons and holes have a high current density along the length of a CNT due to the low scattering rates along the CNT axis. CNTs can carry current around 10 A/nm2, while standard metal wires have a current carrying capacity that is only around 10 nA/nm2[3].

  1. Excellent Heat Dissipation

Thermal management is an important parameter for the electronic devices’ performance. Carbon nanotubes (CNTs) are well-known nanomaterials for excellent heat dissipation. Moreover, they have a lesser effect of the rise in temperature on the I-V characteristics as compared to silicon [4].

CNT in Transistor Applications: CNFET

The bandgap of carbon nanotubes can be changed by its chirality and diameter and thus, the carbon nanotube can be made to behave like a semiconductor. Semiconducting CNTs can be a favorable candidate for nanoscale transistor devices for channel material as it offers numerous advantages over traditional silicon-MOSFETs. Carbon nanotubes conduct heat similar to the diamond or sapphire. Also, they switch more reliably and use much less power than silicon-based devices [5].

In addition, the CNFETS have four times higher trans-conductance than its counterpart. CNT can be integrated with a High-K material, which is offering good gate control over the channel. The carrier velocity of CNFET is twice as compared to MOSFET, due to increased mobility. A carrier mobility of N-type and P-type CNFET is similar in offering advantages in terms of same transistor size. In CMOS, PMOS (P-type metal-oxide-semiconductor) transistor size is approximately 2.5 times more than NMOS (N-type metal-oxide-semiconductor) transistor as mobility values are different.

The Fabrication process of CNTFET is a very challenging task as it requires precision and accuracy in the methodologies.Here we discuss the Top-gated CNTFET fabrication methodology.

The first step in this technique starts from the placement of carbon nanotubes onto the silicon oxide substrate. Then the individual tubes are isolated. Source and drain contacts are defined and patterned using advanced lithography. The contact resistance is then reduced by refining the connection between the contacts and CNT. The deposition of a thin top-gate dielectric is performed on the nanotube via evaporation technique. Lastly, to complete the process, the gate contact is deposited on the gate dielectric [6].

Figure 4: Concept of Carbon-Nanotube FET

Challenges of CNTFET:

There are lots of challenges in the roadmap of commercial CNFET technology.  Majority of them have been resolved to a certain level, but a few of them are yet to be overcome. Here we will discuss some of the major challenges of CNTFET.

  1. Contact Resistance

For any advanced transistor technology, the increase in contact resistance due to the low size of transistors becomes a major performance problem. The performance of the transistor degrades as the resistance of contacts increases significantly due to the scaling down of transistors. Until now, decreasing the size of the contacts on a device caused a huge drop in execution — a challenge facing both silicon and carbon nanotube transistor technologies [7].

  1. Synthesis of Nanotube

Another challenge with CNT is to change its chirality such that it behaves like a semiconductor. The synthesized tubes have a mixture of both metals and semiconductors. But, since only the semiconducting ones are useful for qualifying to be a transistor, engineering methodologies need to be invented to get a significantly better result at separating metal tubes from semiconducting tubes.

  1. To develop a non-lithographic process to place billions of these nanotubes onto the specific location of the chip poses a challenging task.

Currently, many engineering teams are carrying out research about CNTFET devices and their logic applications, both in the industries and in the universities. In the year 2015, researchers from one of the leading semiconductor companies succeeded in combining metal contacts with nanotubes using “close-bonded contact scheme”. They achieved this by putting a metal contact at the ends of the tube and making them react with the carbon to form different compounds. This technique helped them to shrink contacts below 10 nanometers without compromising the performance [8].

Gate-All-Around FET: GAAFET

One of the futuristic potential transistor structures is Gate-all-around FET. The Gate-all-around FETs are extended versions of FinFET. In GAAFET, the gate material surrounds the channel region from the four directions. In a simple structure, a silicon nanowire as a channel is wrapped by the gate structure. A vertically stacked multiple horizontal nanowires structure is proven excellent for boosting current per given area. This concept of multiple vertically stacked gate-all-around silicon nanowire is shown in Figure 5.

Figure 5: Vertically Stacked Nanowires GAAFET

Apart from silicon material, some other materials like InGaAs, germanium nanowires can also be utilized for better mobility.

There are many hurdles for GAAFET in terms of complex gate manufacturing, nanowires, and contacts. One of the challenging processes is fabricating nanowires from the silicon layer as it requires a new approach for the etching process.

There are many research labs and institute working for Gate-all-around FET for lower nodes. Recently, Leuven based R&D firm claimed that they achieved excellent electrostatic control over a channel with GAAFET at sub 10nm diameter nanowire. Last year, one of the leading semiconductor companies unveiled a 5nm chip, which contains 30 billion transistors on a 50mm2chip using stacked nanowire GAAFET technology. It claimed to achieve 40% improvement in performance compared to 10nm node or 70% improvement in power consumption at the same performance.

Compound Semiconductors:

Another promising way to scale down a transistor node is the selection of novel material that exhibits higher carrier mobility. A compound semiconductor with ingredients from columns III and V are having higher mobility compared to silicon. Some compound semiconductor examples are Indium Gallium Arsenide (InGaAs), Gallium Arsenide (GaAs), and Indium Arsenide (InAs). According to various studies, integration of compound semiconductor with FinFET and GAAFET showing excellent performance at lower nodes.

The main concerns with compound semiconductor are large lattice mismatch between silicon and III-V semiconductor, resulting in defects of the transistor channel. One of the firms developed a FinFET containing V-shaped trenches into the silicon substrate. These trenches filled with indium gallium arsenide and forming the fin of the transistor. The bottom of the trench is filled with indium phosphide to reduce the leakage current. With this trench structure, it has been observed that defects terminate at the trench walls, enabling lower defects in the channel.

Conclusion:

From the 22nm node to 7nm node, FinFETs have been proven successful and it may be scaled down to one more node. Beyond that, there are various challenges like self-heating, mobility degradation, threshold flattening, etc. We have discussed how carbon nanotube’s excellent properties of motilities, heat dissipation, high current carrying capability offer promising solutions for replacing existing silicon technology. As the stack of horizontal nanowire opened a “fourth gate”, Gate-all-around transistor structure is also a good candidate for replacing vertical Fin structure of FinFET for achieving good electrostatic property. It is not clear what comes next in the technology roadmap. However, in the futuristic transistor technology, there must be changes of existing material, structure, EUV (Extreme ultraviolet) lithography process, and packaging to sustain Moore’s law.

References:

[1]  Pavan Vora, Ronak Lad, “A Review Paper on CMOS, SOI and FinFET Technology”, www.design-reuse.com/articles/

[2]  P.A Gowri Sankar, K. Udhaya Kumar, “Investigating The Effect of Chirality On Coaxial Carbon Nanotube Field Effect Transistor”, 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET)

[3] Rashmita Sahoo, S.K Sahoo, “Design of an efficient CNTFET using optimum number of CNT in channel region for logic gate implementation”, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

[4] Yijian Ouyang and Jing Guo, “Heat dissipation in carbon nanotube transistors”, Appl. Phys. Lett. 89, 183122 (2006)

[5] Philip G. Collins & Phaedon Avouris, “Nanotubes for Electronics”, Scientific American 283, 62 – 69 (2000)

[6] Wind, S. J.; Appenzeller, J.; Martel, R.; Derycke, V.; Avouris, Ph. (2002). “Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes”, Applied Physics Letters. 80 (20): 3817. Bibcode:2002ApPhL..80.3817W.

[7] Aaron D. Franklin, Wilfried Haensch, “Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors”, 72nd Device Research Conference

[8] IBM, “IBM Research Breakthrough Paves Way for Post-Silicon Future with Carbon Nanotube Electronics”, https://www-03.ibm.com/press/us/en/pressrelease/47767.wss

About Authors:

Pavan Vora

Pavan Vora is working as an ASIC Physical Design Engineer at eInfochips, an Arrow company. He has more than 3 years of experience in ASIC designs for cutting technology nodes such as 12nm, 16nm FinFET, and 28nm. Pavan has expertise in ASIC P&R, LEC, LVS, Static Timing Analysis, Signal EM, DRC, and IR drop and has been awarded a Gold Medal in Master of Engineering in VLSI System Design.

Akash Verma

Akash Verma is working as an ASIC Trainee Engineer at eInfochips, an Arrow company. He has completed his bachelors in Electronics & Communication from the GIT, Gandhinagar. He is currently working on networking ASIC chip at 7nm FinFET technology, in which his accountabilities include block level APR, Static Timing Analysis and Physical Verification. His interest lies in Analog Mixed Signal designs and EDA tool’s algorithmic methodologies.

Dhaval Parikh

Dhaval Parikh is working as a Technical Manager at eInfochips, an Arrow company. He has more than 11 years of industry experience and has worked in various ASIC designs of IP’s & SoC’s, from 180nm to cutting technology node 7nm. He has been responsible for all the aspects of physical design and verification along with executing multiple projects simultaneously.

About eInfochips:

eInfochips, an Arrow company, is a global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company’s service offerings include digital transformation and connected IoT solutions across various cloud platforms, including AWS and Azure.

Along with Arrow’s $27B in revenues, 19,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients through Arrow Connect.

According to data compiled by Inkwood Research, the global semiconductor market is projected to grow at a CAGR of 7.67% during the forecast period from 2017 to 2024. Data reflects that the market is driven by rising demand for consumer electronics, the growing automotive semiconductor market, the emerging internet of things (IoT) market and investments into New Product Development and R&D. Consumer electronics are primarily fueling the market due to demand for products such as tablets, smartphones, laptops and wearable devices. As semiconductor technology begins to advance, new segments are swiftly being integrated into the market, such as Machine Learning. Squire Mining Ltd. (OTC: SQRMF), Intel Corporation (NASDAQ: INTC), Texas Instruments Incorporated (NASDAQ: TXN), NXP Semiconductors N.V. (NASDAQ: NXPI), Skyworks Solutions, Inc. (NASDAQ: SWKS)

According to data by MarketsandMarkets, the global machine learning sector is expected to grow from USD 1.41 Billion in 2017 to USD 8.81 Billion in 2022 while registering a CAGR of 44.1% during the forecast period. The segment is rapidly growing due to many businesses adopting machine learning to gather intelligence for security and consumer interaction benefits, which can help eliminate human errors. However, machine learning is also being integrated into modern day technology, such as the automotive industry, to build autonomous vehicles. In a report by Forbes, Daniel Newman Principal Analyst and Founding Partner of Futurum Research, explained, “When dealing with a technology as advanced as machine learning, there simply isn’t an industry that would not benefit. I mean how could a business not take advantage of a technology that would make them more successful? In the next year, there will be multiple new uses for machine learning in all of these industries available for the taking and I’m not just talking about in marketing and sales.”

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Yesterday, the Company announced breaking news that, “to report on its prototype ASIC chip testing event held in Seoul, South Korea. With executives and board members from Squire, Future Farm, CoinGeek, Gaonchips and Samsung Electronics in attendance, Peter Kim, President of Squire’s subsidiary AraCore Technology Corp. (“Aracore”), and his team of front-end microchip engineers and programmers, unveiled and tested a working prototype mining system comprised of a newly engineered FPGA (field programmable gate array) ASIC microchip that will be converted into AraCore’s first ASIC chip utilizing 10 nanometer technology for mining Bitcoin Cash, Bitcoin and other associated cryptocurrencies. The test results confirm Aracore’s original design specifications indicating that the ASIC chip, once mass manufactured by Samsung Electronics, will be capable of delivering a projected hash rate of 18 to 22 terahash per second (TH/s) with an energy consumption of between 700 and 800 watts.

Taras Kulyk, Chief Executive Officer of CoinGeek Mining and Hardware, said ‘The CoinGeek team is very pleased with the progress of our strategic partners; Squire Mining and Aracore. With this next generation technology, CoinGeek will continue to pull the blockchain industry out of the proverbial basement and into the boardroom.’

Stefan Matthews, Chairman of nChain, one of the industry leaders in blockchain research and development, and a director of Squire Mining added, ‘The early results indicate that this ASIC microchip has the potential to be the next generation leader in providing hash power for enterprise mining of Bitcoin Cash and other associated crypto currencies. It has also demonstrated the potential to rapidly process consensus protocols across the blockchain faster whilst utilizing less energy than anything currently in this sector.’

Hash rate speed and microchip efficiency are the two most important measuring criteria in the crypto-mining industry to enable end-users to maximize profitability and ROI in their day to day mining operations.

Simon Moore, Executive Chairman and CEO of Squire Mining, stated, ‘Aracore’s time and investment to date have been validated by the impressive results of this new microchip. Once completed, we believe the speed and efficiency of our ASIC microchip combined with our respective mining systems powered by this Samsung manufactured microchip together have the potential to substantially increase the profitability of enterprise mining facilities around the globe. We look forward to releasing our mining system to the market in the first half of next year through our exclusive distribution partners CoinGeek, and competing for a significant piece of this multi-billion-dollar enterprise mining market.’

In its September Update to The 2018 McClean Report, IC Insights discloses that over the past two years, DRAM manufacturers have been operating their memory fabs at nearly full capacity, which has resulted in steadily increasing DRAM prices and sizable profits for suppliers along the way.  Figure 1 shows that the DRAM average selling price (ASP) reached $6.79 in August 2018, a 165% increase from two years earlier in August of 2016. Although the DRAM ASP growth rate has slowed this year compared to last, it has remained on a solid upward trajectory through the first eight months of 2018.

Figure 1

The DRAM market is known for being very cyclical and after experiencing strong gains for two years, historical precedence now strongly suggests that the DRAM ASP (and market) will soon begin trending downward.  One indicator suggesting that the DRAM ASP is on the verge of decline is back-to-back years of huge increases in DRAM capital spending to expand or add new fab capacity (Figure 2). DRAM capital spending jumped 81% to $16.3 billion in 2017 and is expected to climb another 40% to $22.9 billion this year. Capex spending at these levels would normally lead to an overwhelming flood of new capacity and a subsequent rapid decline in prices.

Figure 2

However, what is slightly different this time around is that big productivity gains normally associated with significant spending upgrades are much less at the sub-20nm process node now being used by the top DRAM suppliers as compared to the gains seen in previous generations.

At its Analyst Day event held earlier this year, Micron presented figures showing that manufacturing DRAM at the sub-20nm node required a 35% increase in the number of mask levels, a 110% increase in the number of non-lithography steps per critical mask level, and 80% more cleanroom space per wafer out since more equipment—each piece with a larger footprint than its previous generation—is required to fabricate ≤20nm devices. Bit volume increases that previously averaged around 50% following the transition to a smaller technology node, are a fraction of that amount at the ≤20nm node.  The net result is suppliers must invest much more money for a smaller increase in bit volume output.  So, the recent uptick in capital spending, while extraordinary, may not result in a similar amount of excess capacity, as has been the case in the past.

As seen in Figure 2, the DRAM ASP is forecast to rise 38% in 2018 to $6.65, but IC Insights forecasts that DRAM market growth will cool as additional capacity is brought online and supply constraints begin to ease. (It is worth mentioning that Samsung and SK Hynix in 3Q18 reportedly deferred some of their expansion plans in light of expected softening in customer demand.)

Of course, a wildcard in the DRAM market is the role and impact that the startup Chinese companies will have over the next few years.  It is estimated that China accounts for approximately 40% of the DRAM market and approximately 35% of the flash memory market.

At least two Chinese IC suppliers, Innotron and JHICC, are set to participate in this year’s DRAM market. Although China’s capacity and manufacturing processes will not initially rival those from Samsung, SK Hynix, or Micron, it will be interesting to see how well the country’s startup companies perform and whether they will exist to serve China’s national interests only or if they will expand to serve global needs.

 

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, to day announced worldwide sales of semiconductors reached $40.16 billion for the month of August 2018, an increase of 14.9 percent compared to the August 2017 total of $34.96 billion. Global sales in August 2018 were 1.7 percent higher than the July 2018 total of $39.49 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales continued to bound upward in August, easily outperforming sales from last August and narrowly surpassing last month’s total,” said John Neuffer, president and CEO, Semiconductor Industry Association. “While year-to-year growth has moderated somewhat in recent months, sales remain strong across every major semiconductor product category and regional market, with the China and Americas markets standing out with the largest year-year growth.”

Regionally, sales increased compared to August 2017 in China (27.3 percent), the Americas (15.0 percent), Europe (9.5 percent), Japan (8.4 percent), and Asia Pacific/All Other (4.7 percent). Sales were up compared to last month in China (2.1 percent), the Americas (3.6 percent), and Asia Pacific/All Other (1.3 percent), and decreased slightly inJapan (-0.1 percent), and Europe (-1.4 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

By Jay Chittooran

Last week, SEMI joined a coalition of business groups in calling for Ambassador Robert Lighthizer, U.S. Trade Representative, to enact an exclusion process for the most recent tranche of tariffs on $200 billion in goods imported from China.

While an exclusion process was provided for in the previous tariff lists, which cover about $50 billion in goods, the administration has said that no similar process will be provided on the most recent tariffs on $200 billion (List 3), which took effect Monday. SEMI members will face millions of dollars in additional duties as a result of these tariffs. This action will also curb growth, stifle innovation, and introduce significant uncertainty in the semiconductor industry.

Americans for Free Trade is a diverse coalition, which includes hundreds of companies across the United States, to illustrate the impacts of tariffs on American businesses, consumers and manufacturers. SEMI is a member of this coalition. The full text of the letter can be found here.

Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Originally published on the SEMI blog.

Applied Energy Systems (AES), provider of high and ultra high purity gas systems, services, and solutions – including design, manufacturing, testing, installation, and expert field services – has announced the acquisition of Advanced Research Manufacturing (ARM), Inc., a specialty provider of gas purification systems based in Colorado Springs, CO. ARM, Inc. has been manufacturing high and ultra high purity gas purifiers and gas handling equipment for 20 years and boasts a worldwide installed base of point-of-use, micro-bulk and bulk gas purifiers. AES is a long-time leader in the manufacturing of high and ultra high purity gas and liquid delivery systems, and ARM’s portfolio of solutions will now be offered through AES to supplement and further expand its gas delivery equipment offerings and bring new benefits to customers seeking quality gas handling solutions.

“ARM brings getter, catalyst, and absorber purification technology to Applied Energy Systems that will complement our existing product offerings, allowing AES to provide a more complete and unique solution at a very competitive price,” said Steve Buerkel, President of Applied Energy Systems.

ARM, Inc.’s ultra high purity gas purifiers and associated gas handling equipment are used across the industrial, semiconductor, energy, medical, and pharmaceutical markets both in the U.S. and internationally – the same verticals where AES has a proven track record of enabling safe, precise gas delivery. “There is already a great deal of synergy between the AES and ARM teams in terms of our knowledge of gas handling requirements for innovative processes and applications,” said Jim Murphy, General Manager of AES.  “ARM’s products are a natural extension of our equipment offerings, and together we’ll offer customers our collective expertise to benefit their projects – whether they require gas purification or gas delivery solutions, or both.”

Brian Warrick, ARM, Inc.’s Director of Technology, added: “With AES’ and ARM’s combined resources, the research of new technologies and subsequent development of new products can occur at a more rapid pace. This will enable us to efficiently add to ARM’s existing portfolio of offerings that include purifiers as well as field engineering support.”

“We are extremely pleased to become a part of AES, and look forward to growing our market share in the purification of high and ultra high purity gas,” said Dan Spohn, Director of Global Sales and Market Development at ARM.

By Jaegwan Shim

Korea is on track to top all other regions in fab investment, spending $63 billion between 2017 and 2020, with powerhouses Samsung Electronics Co. and SK Hynix leading the way, according to latest World Fab Forecast Report by SEMI. Samsung Electronics increased fab investments $770 million to $12 billion this year, and SK Hynix upped its spending a significant $2.8 billion to $7.25 billion in 2018.

Korea’s investment companies anticipate continued growth for both companies in the second half of 2018.

Under this halo of extraordinary investment, nearly 380 SEMI Korea members and industry analysts gathered for 2018 SEMI Korea Members Day on September 22 to share insights on semiconductor market trends and new technologies that could help members bolster their competitiveness. Following are key takeaways from the event.

Korea semiconductor market to grow 16% in 2018

That’s according to IDC Korea VP Kim Soo-kyung, who noted that data center, memory and Internet of Things (IoT) are becoming key growth drivers for the semiconductor industry. He encouraged semiconductor companies to closely track development of automotive technology and the industry semiconductor market, both key growth areas.

SEMI Korea president H.D. Cho opens SEMI Korea Members Day 2018

Continuing fab investment will lead to oversupply, but display will shine

Market entry by Chinese companies will also spur the oversupply, said Jeong Won-Seok, an analyst at HI Investment Corp. He noted that the oversupply will force Korea into stiffer competition with other regions. However, with OLED used for a wide variety of devices and the display industry seeing rapid growth, the sector will remain ripe for growth among Korean companies.

Interconnecting various applications is a big semiconductor industry trend

The need for these interconnections will stand out in the mobility and high-performance computing (HPC) markets, said Kim Jin-Young, director at Amkor Technology Korea, who addressed trends in packaging technology. He also emphasized interconnection cost efficiency as key to maximizing competitiveness.

Smart Manufacturing is driving mass customization

As semiconductor industry growth continues, production methods are shifting from ‘mass production’ to ‘mass customization,’ increasing the importance of Smart Manufacturing in driving greater production efficiency, noted BISTel VP Jeon Kyeong-Sik. Building a Smart Manufacturing platform to support large-scale production of specialized database and artificial intelligence (AI) chips will boost production efficiency, reduce costs and improve risk management. Virtual simulation will be a key enabling technology.

SEMI analyst Clark Tseng presenting at SEMI Korea Members Day 2018

Surge in data volume and technology advances to drive long-term semiconductor industry growth

These key industry drivers will continue to power fab investment growth, with spending focused on 3D NAND, DRAM, and foundry, said Clark Tseng, a SEMI analyst. China alone will see eye-watering growth with the region’s investments in domestic companies surging 46% from 2018 to 2019 and fab investment by Chinese domestic companies outpacing spending by foreign companies in China, Tseng predicted.

SEMI membership rises with industry growth

Culminating the event, SEMI Korea president H.D. Cho said, “With the growth of the semiconductor market, the number of SEMI members is gradually increasing, and we will help member companies grow with various activities such as Korea Members Day.”

Jaegwan Shim is a marketing specialist at SEMI Korea. 

Originally published on the SEMI blog.

Imagination Technologies and GLOBALFOUNDRIES (GF) announced today at its annual GTC 2018 conference, a joint collaboration to provide ultra-low-power baseband and radio frequency (RF) solutions for Bluetooth Low Energy® (BLE) and IEEE 802.15.4 technology, using Imagination’s Ensigma connectivity IP on GF’s 22nm FD-SOI (22FDX®) platform. In addition, Imagination has joined GF’s FDXcelerator™ Partner Program.

The combination of 22FDX technology and Imagination’s Ensigma IP provides a power and cost efficient solution that customers can easily integrate into their System on Chip (SoC) designs. The collaboration will enable mutual customers to create innovative and differentiated connected devices for the Internet of Things (IoT) using Imagination’s silicon-proven, ultra-low power Ensigma connectivity engines in GF’s ultra-efficient 22FDX process.

David McBrien, executive vice president of sales and marketing, Imagination, says: “By working with partners such as GF, we continuously enhance our IP for the latest processes. 22FDX is an appealing option for customers designing cost-sensitive devices. The collaboration has made our Ensigma connectivity IP even more power and area efficient. The availability of silicon-proven baseband and RF enables customers to rapidly introduce single-chip wireless devices requiring only a single external antenna.”

“Imagination’s IP and BLE solutions complement GF’s 22FDX FD-SOI capabilities, enabling clients to leverage low-power, low-cost designs for IoT and connected applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “We are pleased to welcome Imagination as a partner in our FDXcelerator program to further broaden IP and design service choices and flexibility that will best match client requirements.”

Ensigma IP for 22FDX provides a complete IP solution comprising analogue RF/AFE as a hard macro complete with a fully synthesizable baseband IP for applications such as wearable computing, health care, and home control. The solution for ultra-low power Bluetooth Low Energy and IEEE 802.15.4 is currently in development with lead customers, with silicon available in early Q4 2018.

As a part of GF’s FDXcelerator Program, Imagination will join the rapidly-growing number of industry leaders committed to provide a broad set of resources, including EDA tools, IP, silicon platforms, reference designs, design services and packaging and test solutions specific to 22FDX technology. The program’s open framework enables members to minimize development time and cost while simultaneously leveraging the inherent power and performance advantages of FDX technology.

Mini diaphragm gauges offer a new alternative to Bourdon tubes.

BY BRIAN SULLIVAN, Valin Corporation, San Jose, CA

Fabs and OEMs in the semiconductor industry face a number of difficult challenges today, specifically in the etch and deposition/thin film processes. These incredibly specialized processes require extremely clean gases and vaporized chemical sources. The fabs and their process tools utilize gas delivery systems to provide these ultra-pure materials from their bulk sources to their process tools and systems. The increased use of highly aggressive and reactive gases in these processes has caused one very specific problem. These aggressive gases are picking up moisture (through leaks, flawed component installations, improper purging, poor PM practices, etc.) and then attacking and corroding the bourdon tubes located within the pressure gauges in the impacted lines. In a few instances, leaks have been created through these stressed system components.

Millions of dollars are spent inside the fabs and by OEMs to have a highly electropolished finish on the internal wetted surfaces of the many components that comprise their gas delivery systems. The gauges themselves have not been found to be the originating source of the leaks. Instead, the leaks form elsewhere, and the moisture laden and now highly corrosive gas immediately attacks the least corrosion resistant components found within the delivery line. Unfortunately, the bourdon tubes found in most “ultra-high purity (UHP) gauges” today are a principal target. When this type of event occurs, it doesn’t take long for the exposed gauges to fail.

The root of this problem lies in the fact that a standard pressure gauge’s main functioning component is typically an un-passivated, or only marginally passivated, bourdon tube. This tube is open to pressure on one end and welded closed at the other, a design invented by Eugene Bourdon more than 165 years ago. This is the principal weakness and ultimately leaves these gauges subject to corrosion.

As pressure enters this thin, hollow, C-shaped bourdon tube, it causes the tube to flex outward from its relaxed, round shape, stretching it up and away from its original form and position. The tip of the bourdon tube is connected to linkage that moves a pointer around the internal dial (or face) of the gauge, indicating the pressure the gauge is currently measuring. Of course, flexing components made of stainless steel – particularly if they aren’t fully electropolished like the tubing, fittings, valves, regulators, and other components in the delivery system’s line – become vulnerable to chemical attack through the micro fissures formed by the flexures they experience. Each time a bourdon tube flexes, it can suffer the creation of micro fissures. Over time these can then grow into macro fissures, and then ultimately create internal cracks or complete breaks in the bourdon tube’s integrity. Throughout the life of a typical pressure/vacuum gauge in a dynamic system, going through gas source changes, pressure spikes, cycle purge sequences, and other events, the flexing bourdon tube will be subjected to the formation of countless micro fissures. If they are then exposed to a corrosive gas that has become aggressive through the introduction of moisture, it should be no surprise that the bourdon tubes will be aggressively assailed and damaged in the process.

It is well known throughout the industry that aggressive corrosive gases transported through the gas lines increase the likelihood of both internal particle generation and outbound leaks from any vulnerable component. Of course, the presence of any entrained moisture compounds the probability greatly. Any time a minimal quantity of atmospheric moisture makes its way into these corrosive gas lines, it will convert the corrosive gasses into corrosive acids. The bourdon tube acts as a dead leg in the system and is an ideal place for the corrosive gas to enter but does not allow it to get back out. Once the gas forms an acid, the acid will corrode any susceptible surface and generate an exit path by eating its way through the material. Many of the most vulnerable areas for this activity in a gas delivery system are the micro fissures found inside of bourdon tubes.

Although the process connection of a pressure gauge (typically a face seal fitting for semiconductor applications) will be fully passivated and electropolished and is clearly identified in the literature as such. The surface finish and Ra Max or Ra Average values of the bourdon tube itself is usually not provided. Gauge manufacturers measure their gauge connection’s wetted surfaces, but when they are asked about the bourdon tube, there is usually not a clear answer. The surface finish and passivation level of the bourdon tube inside the gauge is not disclosed in most cases. The reason for this is simple. Gauge manufacturers do not make a bourdon tube of electropolished and fully passivated stainless steel because the electropolishing process would damage the bourdon tube due to its thin, spring-like design. A bourdon tube must be able to flex to properly function and to do that it has to be made from thin metal.

Originally the industry used these “standard” bourdon tube gauges in non-critical applications because, compared to their more expensive transducer cousins, they were inexpensive, simple to use, and easy to obtain. However, as the industry has continued to evolve, and the processes used in the OEMs systems have required more aggressive and reactive gases, the use of these gauges has continued. Today, if decision makers want the best running and safest fabs their money can buy, they have to make a change.

The solution: mini diaphragm gauges

Engineers have been searching for a solution to the burden this issue presents to the fabs, and fortunately, a solution has been found and has proven itself to be both long lasting and resilient.

Mini diaphragm gauges for both pressure and compound applications are now available that eliminate the bourdon tube completely. These mini diaphragm gauges employ a diaphragm made of Inconel®, which is highly flexible and extremely corrosion resistant. In an accelerated corrosion study, it exceeded the lifespan of a standard “UHP gauge” using a bourdon tube by a factor of twenty. This means that a gauge that would have lasted only six months in a corrosive application can now last up to ten years.

This Inconel® diaphragm will not suffer the effects of corrosion that its weaker, stainless steel bourdon tube counterpart does. It also removes the dead leg of the bourdon tube itself within the gauge. And all the wetted surfaces of these mini diaphragm pressure gauges are made of either fully electropolished 316L Stainless Steel (Ra <0.25 μm) or Inconel® 718. They also comply with SEMATECH and SEMI Standards.

In the mini diaphragm gauge, the Inconel® diaphragm is welded directly to the solid, stainless steel body which is machined out of a piece of 316L SS bar stock. This seals the wetted surfaces away from the atmosphere and the linkage used to actuate the gauge’s pointer.

Standard (bourdon tube) gauges are made with two separate assemblies. The outer case that holds the dial and outer face is usually made from a very thin sheet of stainless steel and formed into a cylindrical cup-like shape. Its whole function is to hold and protect the dial, the window, the gauge’s bourdon tube assembly and the associated linkage inside of it. The bourdon tube assembly is made of the process connection socket, welded to the bourdon tube, and welded to a tube end-piece. Those are then connected to the linkage and movement pieces that connect to the pointer. Additionally, there are usually a pair of screws that hold the housing onto the gauge’s internal assembly and a couple more that fix the gauge’s dial in place.

The mini diaphragm gauges are made in a manner similar to that of a UHP valve or regulator where the process connection and the case (body) are machined from one solid piece of 316L stainless steel. The Inconel® diaphragm is then welded in place, sealing the wetted surfaces away from the atmosphere, the linkage used to actuate the gauge’s pointer, the face of the gauge, and its outer window. Additionally, the linkage inside the mini diaphragm gauge is not the simplistic linkage of a regular gauge. It is more like a swiss watch in its complexity.

The mini diaphragm gauges are currently only available in 1” and 1.3” dial sizes (hence the “mini” in the name) with ¼” face seal connections. As aggressive gases in gas delivery systems are typically run in ¼” inch lines, there is not a need for larger gauges for these applications, meaning a mini diaphragm gauge should suffice. Another benefit is these can also be used in surface mount applications common to the industry today. If there is a need for a gauge to be installed into a 1.125” or 1.5” surface mount application, this is a perfect fit.

Moving away from using a flexible un-passivated stainless steel internal component to a highly corrosion resistant diaphragm is the exact same technology path taken years ago when diaphragm valves overtook bellows valves for use in reactive and corrosive process gas applications and in nearly all UHP systems. It is a simple, fully-established, and well-proven solution for safer and cleaner gas delivery systems.

Having gauges follow this technology path is one that many OEMs and fabs are just beginning to move toward. This is especially true in the applications and processes where a costlier pressure transducer is not required.

BRIAN SULLIVAN is the Director of Sales – Technology for Valin Corporation, San Jose, CA.

By Jay Chittooran

Last week, more than a dozen senior semiconductor executives traveled to Washington, DC for the first-ever Fall Washington Forum. The SEMI Washington Forum, a venue for SEMI members to educate lawmakers about the industry, focused on action against China, both in the form of tariffs and export controls.

Our industry is global, and companies rely heavily on trade. In 2017, more than 90 percent of equipment made in the United States was exported. Because of this dynamic, the United States holds a nearly $9 billion trade surplus in this industry. SEMI is supportive of trade policies that open foreign markets.

In the meetings, the executives expressed deep concern that the tariffs would inflict deep damage to the U.S. economy, including to SEMI members. Estimates suggest that the Sec. 301 tariffs (and the Chinese retaliatory tariffs) will cost semiconductor companies more than $700 million annually, dramatically increasing the cost of doing business. These tariffs also threaten U.S. technological leadership. The United States has led innovation for decades. However, by pursuing policies that limit market access opportunities, company-led R&D and innovation will slow, which, in turn, will curb further export potential.

SEMI companies also stressed that because of the blunt application of these tariffs, this action will actually hurt U.S. companies as much as it hurts their Chinese competitors. Indeed, about 40 percent of imports in our sector from China are from U.S. or other non-Chinese companies. Further, the semiconductor industry relies on a vast network of supply chains, which have been built and qualified over the course of years. A fundamental revamp of supply chains is simply not feasible. This would be expensive, time-consuming, and resource-intensive.

With a growing number of policy issues that are central to and could have significant impact for semiconductor companies, SEMI hosted its first ever Fall Washington Forum for members of its North American Advisory Board (NAAB). SEMI also invited several other industry executives. In total, 14 senior industry executives, including representatives from equipment manufacturers, component suppliers, and materials providers, attended the Fall Forum.

During the two days of meetings, SEMI met with several senior Administration officials to better the policies being enacted and considered as well as encourage all parties to not impose barriers to commerce, which would severely impact the semiconductor industry. SEMI also met with Members of Congress and their staffs on this issue.

All told, attendees at the Fall Forum had more than 15 meetings with policymakers, reflecting the great impact of public policy on SEMI members companies. At a time when the stakes for the industry could not be higher, direct engagement with lawmakers is critical. The Washington Forum offers an incredible opportunity for members to better understand the impact of key public policy issues and gain firsthand experience in influencing policy and helping lawmakers better understand the industry.

If you are interested in learning more about the SEMI Washington Forum or SEMI’s public policy program, please contact Jay Chittooran by email at [email protected].