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Leti, a research institute at CEA Tech, and CMP, a service organization that provides prototyping and low-volume production of ICs and MEMS, today announced the integrated-circuit industry’s first multi-project-wafer (MPW) process for fabricating emerging non-volatile memory OxRAM devices on a 200mm foundry base-wafer platform.

Available on Leti’s 200mm CMOS line, the MPW service provides a comprehensive, very low-cost way to explore techniques designed to achieve miniaturized, high-density components. Including Leti’s Memory Advanced Demonstrator (MAD) future mask set with disruptive OxRAM (oxide-based resistive RAM) technology, Leti’s integrated silicon memory platform is developed for backend memories and non-volatility associated with embedded designs. The new technology platform will be based on HfO2/Ti (titanium-doped hafnium oxide) active layers.

Emerging OxRAM non-volatile memory is one of the promising technologies to be implemented for classical embedded memory applications on advanced nodes like micro-controllers or secure products, as well as for AI accelerators and neuromorphic computing.

Leti’s MAD platform is dedicated to advanced non-volatile memories, bringing both versatility and robustness for material and interface assessment, and allowing in-depth exploration of memory performance from technology and design perspectives.

The full platform’s highlights:

  • 200mm STMicroelectronics HCMOS9A base wafers in 130nm node
  • All routing is made on ST base wafers from M1 to M4 (included)
  • Leti’s OxRAM memory module is fabricated on top
  • One level of interconnect (i.e. M5) plus pads are fabricated in Leti’s cleanroom.

“Leti has developed during the past 20 years deep expertise in non-volatile memory (NVM) devices covering flash evolutive solutions and disruptive technologies,” said Etienne Nowak, head of the Leti’s Advanced Memory Lab. “This MPW capability, combined with our Memory Advanced Demonstrator platform, is based on a broad tool box that enables customized research with our partners, and provides a benchmark between different NVM solutions.”

The MPW service with integrated silicon OxRAM addresses all the key steps of advanced memory development. These include material engineering and analysis, developing critical memory modules, evaluation of memory cells coupled with electrical tests, modeling and innovative design techniques to comply with circuit design opportunities and constraints. This technology offer comes with a design kit, including layout, verification and simulation capabilities. Libraries are provided with a comprehensive list of active and passive electro-optical components. The design kit environment is compatible with all offers through CMP.

Providing access to a non-volatile memory process from Leti is a major achievement in development work at CMP. Since 2003, the organization has participated in national and European projects for developing access to NVM technologies (Mag-SPICE, Calomag, Cilomag, Spin, and Dipmem). With this new offer in place, the CMP users’ community can have the benefits and advantages of using this process through this close collaboration between CMP and Leti.

“CMP has a long experience providing smaller organizations with access to advanced manufacturing technologies, and there is very strong interest in the CMP community in designing and prototyping ICs using this process,” said Jean-Christophe Crébier, director of CMP. “It is an opportunity for many universities, start-ups and SMEs in France, Europe,North America and Asia to take advantage of this new technology and MPW service.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced Dr. John L. Hennessy, chairman of Alphabet Inc., former president of Stanford University, and pioneer in electrical engineering, has been named the 2018 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the semiconductor industry in technology or public policy. Hennessy will accept the award at the SIA Annual Award Dinner on Thursday, Nov. 29, 2018 in San Jose.

“Throughout his outstanding and influential career spanning more than four decades, John Hennessy has helped move the semiconductor industry forward, leading efforts to advance semiconductor technology and train future generations of electrical engineers,” said John Neuffer, president and CEO, Semiconductor Industry Association. “John literally wrote the book on computer architecture design and has spearheaded semiconductor research that has helped make our industry what it is today. On behalf of the SIA board of directors, it is an honor to announce John’s selection as the 2018 Robert N. Noyce Award recipient in recognition of his exceptional accomplishments.”

Hennessy joined Stanford University’s faculty in 1977 as an assistant professor of electrical engineering and rose through the academic ranks to become Stanford’s 10th president, serving in that role from 2000 until his retirement in 2016. In February 2018, Dr. Hennessy was appointed chairman of Alphabet Inc., parent company of Google.

In 1981, Hennessy drew together researchers to focus on a computer architecture known as RISC (Reduced Instruction Set Computer), a technology that has revolutionized the computer industry by increasing performance while reducing costs. Dr. Hennessy helped transfer this technology to industry. In 1984, he cofounded MIPS Computer Systems, which designed microprocessors. In more recent years, his research focused on the architecture of high-performance computers.

Hennessy has lectured and published widely and is the co-author of two internationally used

undergraduate and graduate textbooks on computer architecture design. He earned his bachelor’s degree in electrical engineering from Villanova University and his master’s and doctoral degrees in computer science from the State University of New York at Stony Brook.

“It is a true privilege to be selected for this award, joining a distinguished list of pioneers and icons who have previously received it,” said Hennessy. “Throughout my career, I have been fortunate to work with countless outstanding colleagues, mentors, and friends who have been instrumental in my work every step of the way. It is with them in mind that I gratefully accept this award, and I look forward to continuing to work alongside them to advance the forward march of innovation.”

The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel.

In its recently released Mid-Year Update to The McClean Report 2018, IC Insights forecasts that the 2018-2022 global GDP and IC market correlation coefficient will reach 0.95, up from 0.88 in the 2010-2017 time period.  IC Insights depicts the increasingly close correlation between worldwide GDP growth and IC market growth through 2017, as well as its forecast through 2022, in Figure 1.

As shown, over the 2010-2017 timeframe, the correlation coefficient between worldwide GDP lgrowth and IC market growth was 0.88, a strong figure given that a perfect correlation is 1.0.  In the three decades previous to this timeperiod, the correlation coefficient ranged from a relatively weak 0.63 in the early 2000s to a negative correlation (i.e., essentially no correlation) of -0.10 in the 1990s.

IC Insights believes that the increasing number of mergers and acquisitions, leading to fewer major IC manufacturers and suppliers, is one of major changes in the supply base that illustrate the maturing of the industry that is helping foster a closer correlation between worldwide GDP growth and IC market growth. Other factors include the strong movement to the fab-lite business model and a declining capex as a percent of sales ratio, all trends that are indicative of dramatic changes to the semiconductor industry that are likely to lead to less volatile market cycles over the long term.

In 2017, IC industry growth was greatly influenced by the “Capacity/Capital Spending Cycle Model” as the DRAM and NAND flash markets surged and served to drive total IC industry growth of 25%.  It would initially appear that the strong correlation coefficient between worldwide GDP growth and total IC market growth that had been evident from 2010 through 2016 had disappeared in 2017.  However, IC Insights does not believe that is the case.

When excluding the DRAM and NAND flash segments from the IC market in 2017, the remainder of the IC market displayed an 11% increase, which closely correlates to what would be expected given a worldwide GDP increase from 2.4% in 2016 to 3.1% in 2017.  Moreover, the three-point decline in the total IC market growth rate forecast for 2018, when excluding DRAM and NAND flash (from 11% in 2017 to 8% in 2018), is expected to mirror the slight decline expected for worldwide GDP growth this year as compared to last year.  Thus, excluding the amazing surge for the DRAM and NAND flash markets in 2017 and 2018, IC Insights believes that the trend toward an increasingly close correlation between total IC market growth and worldwide GDP growth is still largely intact.

Figure 1

 

By Jay Chittooran, Public Policy Manager, SEMI 

Two months after opposing $34 billion in U.S. trade tariffs on behalf of the U.S. semiconductor manufacturing industry, Jonathan Davis, global vice president of industry advocacy at SEMI, this week spoke out against an additional $16 billion duties on Chinese goods. Testifying before the same U.S. interagency panel mulling the merits of the tariffs, Davis called for the removal of 29 tariff lines covering items critical to semiconductor manufacturing including machines and spare parts used to make, wafers, flat panel displays and masks.

In his testimony to the panel, Davis stressed that while SEMI supports stronger protections against the theft of valuable intellectual property (IP), tariffs do little to address U.S. concerns over IP loss. Over the past month, SEMI has also submitted written comments and opposed the tariffs in public testimony. The panel includes representatives from the U.S. Trade Representative (USTR), Departments of Treasury, Commerce, State and Defense, and the Council of Economic Advisers.

Also testifying, Joe Pon, corporate vice president at Applied Materials, explained that the proposed tariffs will harm small and midsized companies and other U.S. business interests. Describing the tariffs as a tax on exports of high-value U.S. goods, Pon said the duties give non-U.S. firms an unfair competitive advantage.

In a parallel push to Davis’s testimony, SEMI, with more than 10 representatives from six member companies, met with 16 congressional offices this week to underscore the damage the tariffs would wreak on the U.S. semiconductor industry. The fallout would include higher operating costs, fewer exports and slower innovation. The tariffs would also curb industry growth and put thousands of high-paying, high-skill jobs at risk. SEMI pressed congressional leaders to reject the tariffs and support a push for congress to re-assert itself on trade policy.

Tariffs to cost U.S. SEMI members more than $500 million

SEMI estimates that the second list of proposed tariffs, covering about $16 billion in Chinese goods, will cost its 400 U.S. members more than $500 million annually in additional duties.

The tariffs on $34 billion in Chinese goods, which took effect July 6, impact products such as test and inspection equipment as well as spare parts that enter the U.S. from China. That round of tariffs will cost SEMI member companies and estimated tens of millions of dollars annually.

SEMI public policy team asks members to review tariff list

Looking ahead, SEMI encourages members to review the newly released $200 billion tariff list, determine any impact to their businesses and share their findings with SEMI’s public policy team.

The U.S. Trade Representative (USTR) has published the exclusion process for products subject to the China 301 tariffs. If your company’s products are subject to tariffs, you can request an exclusion.

In evaluating product exclusion requests, the USTR will consider whether a product is available from a source outside of China, whether the additional duties would cause severe economic harm to the requestor or other U.S. interests, and whether the product is strategically important or related to Chinese industrial programs (such as “Made in China 2025”).

The deadline for submitting product exclusion requests to USTR is October 9, 2018. Approved exclusions will be effective for one year upon approval and retroactive to July 6, 2018.

More information including the process for submitting the product exclusion request can be found here.

Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

The silicon-on-insulator market is expected to reach USD 1,832.5 million by 2023 from USD 686.0 million by 2018, at a CAGR of 21.7%, According to the new market research report “Silicon on Insulator (SOI) Market by Wafer Size (200 mm and less than 200 mm, 300 mm), Wafer type (RF-SOI, FD-SOI, PD-SOI, Power SOI, Emerging-SOI), Application (Consumer Electronics, Automotive, Datacom, Industrial), Technology – Global Forecast to 2023”, published by MarketsandMarkets™ . The increasing use of SOI wafers in advanced devices such as smartphones, tablets, earphones/headphones, and wearables is expected to boost the market for consumer electronics application. Moreover, while manufacturing thin wafers, the use of SOI technology prevents the wastage of silicon, which reduces the cost of semiconductor devices. Hence, the effective use of silicon during the manufacture of thin SOI wafers is a major factor driving the growth of the SOI market.

SOI market for 300-mm wafers size to grow at a higher CAGR during forecast period

The market for 300-mm wafer size is expected to grow at the highest CAGR during 2018-2023. Wafer and foundry players expanding their capacity for producing 300-mm wafers is one of the driving factors for the growth of the SOI market. For instance, Soitec expanded its manufacturing capacity for the production of 300-mm SOI wafers.

Consumer electronics application expected to hold the largest share of the SOI market during the forecast period

Among the SOI applications, the market for consumer electronics is expected to hold the largest share during 2018-2023. The growth of this market is attributed to the increasing demand for SOI products in smartphones and other consumer electronics devices. For instance, RF SOI wafers are commonly used in smart devices as these wafers enable device integration, cost-effectiveness, and high performance. Also, the growing adoption of FD SOI for consumer or IoT devices is expected to drive the growth of the market.

SOI market in APAC expected to grow at the highest CAGR during the forecast period

SOI market in APAC is expected to grow at the highest CAGR during 2018-2023. APAC is witnessing an increase in the use of SOI products owing to the presence of a large number of consumer electronic companies, smartphone manufacturers, and advanced ICT technology providers, and wafer and foundry players in APAC.

Major players operating in this market are Soitec (France), Shin-Etsu Chemical (Japan), GlobalWafers (Taiwan), SUMCO (Japan), Simgui (China), GlobalFoundries (US), STMicroelectronics N.V. (Switzerland), TowerJazz (Isreal), NXP Semiconductor N.V. (Netherlands), and Murata Manufacturing (Japan).

Know more about the Silicon on Insulator (SOI) Market:

https://www.marketsandmarkets.com/Market-Reports/global-silicon-on-insulator-market-158.html

Semiconductor Research Corporation (SRC), today announced the release of $26 million in added research funding for its New Science Team (NST) Joint University Microelectronics Program (JUMP). JUMP will fund 24 additional research projects spanning 14 unique U.S. universities. The new projects will be integrated into JUMP’s six existing research centers. NST will continue to distribute funds over its five-year plan, and industrial sponsors are welcome to join to further accentuate those plans.

The awards have been given to 27 faculty and will enhance the program’s expertise in technical areas such as atomic layer deposition (ALD), novel ferroelectric and spintronic materials and devices, 3D and heterogeneous integration, thermal management solutions, architectures for machine learning and statistical computing, memory abstractions, reconfigurable RF frontends, and mmWave to THz arrays and systems for communications and sensing.

“The goal of the NST project is not only to extend the viability of Moore’s Law economics through 2030, but to also change the research paradigm to one of co-optimization across the design hierarchy stack through multi-disciplinary teams,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “Our strategic partnerships with industry, academia, and government agencies foster the environment needed to realize the next wave of semiconductor technology innovations.”

“A new wave of fundamental research is required to unlock the ultimate potential of autonomous vehicles, smart cities, and Artificial Intelligence (AI),” said Dr. Michael Mayberry, Senior Vice President and Chief Technology Officer of Intel and the elected Chairman of the NST Governing Council. “Such advances will be fueled by novel and far-reaching improvements in the materials, devices, circuits, architectures, and systems used for computing and communications.”

The JUMP program, a consortium consisting of 11 industrial participants and the Defense Advanced Research Projects Agency (DARPA), is one of two complementary research programs for the NST project—a 5-year, greater than $300 million SRC initiative launched this January. JUMP and its six thematic centers will advance a new wave of fundamental research focused on the high-performance, energy-efficient microelectronics for communications, computing, and storage needs for 2025 and beyond.

Semiconductor revenues are expected to increase 12.8% in 2018 as a result of continued strong memory prices. Units are expected to grow 7.2%. The forecast is based on moderate smartphone sales with a possible return to lower memory prices in the second half of the year. This, among other market issues, will push 2018 wafer demand to over 115 million units in 300mm equivalents according to Semico Research’s newest report, Semico Wafer Demand Update Q2 2018 (MA111-18).

“Semiconductor manufacturers are rolling out new products targeted at artificial intelligence applications. Products require both the most advanced technologies for AI training functions as well as potentially high-volume products for edge devices,” says Joanne Itow, Manager Manufacturing Research for Semico. “On the other side of the technology spectrum, mature processes for sensors and analog products such as biometric sensors, RF and power management continue to be in high demand aided by growth in Internet of Things (IoT) applications along with more ‘smart devices’ that are beginning to build in algorithms that are the precursor to full-fledged AI devices.”

Key findings include:

  • 2018 NAND revenues are expected to increase 18.9%.
  • MCU revenues are expected to exceed $17 billion in 2018.
  • Total Communication MOS Logic wafer demand is expected to increase 4.0% in 2018.
  • Sensor units are expected to grow 20.4% in 2018.

North America-based manufacturers of semiconductor equipment posted $2.49 billion in billings worldwide in June 2018 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 8.0 percent lower than the final May 2018 level of $2.70 billion, and is 8.1 percent higher than the June 2017 billings level of $2.30 billion.

“Global billings of North American equipment manufacturers declined for the current month by 8 percent from the historic high but is still 8 percent higher than billings for the same period last year,” said Ajit Manocha, president and CEO of SEMI. “Billings remain robust.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
January 2018
$2,370.1
27.5%
February 2018
$2,417.8
22.5%
March 2018
$2,431.8
16.9%
April 2018
$2,689.9
25.9%
May 2018 (final)
$2,702.3
19.0%
June 2018 (prelim)
$2,485.7
8.1%

Source: SEMI (www.semi.org), July 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

Imec, a research and innovation hub in nanoelectronics, energy and digital technology, within the partnership of EnergyVille, today announced a record result for its 4-terminal Perovskite/silicon tandem photovoltaic cell. With a power conversion efficiency of 27.1 percent, the new imec tandem cell beats the most efficient standalone silicon solar cell. Further careful engineering of the Perovskite material will bring efficiencies over 30% in reach.

Perovskite microcrystals are a promising material system to make high-performance thin-film solar cells. They can be processed into thin, light, semitransparent modules that can achieve a high power conversion efficiency, are inexpensive to produce, and have a high absorption efficiency for sunlight. Because they can be made semitransparent, perovskite solar cells and modules can also be used on top of silicon solar cells. When the Perovskite is carefully engineered, the absorbance in the Perovskite minimizes the thermal losses that occur in the silicon cell. As a result, a Perovskite-silicon tandem solar cell can potentially reach power conversion efficiencies above 30 percent.

Imec’s new record tandem cell uses a 0.13 cm² spin-coated Perovskite cell developed within our Solliance cooperation stacked on top of a 4 cm² industrial interdigitated back-contact (IBC) silicon cell in a 4-terminal configuration, which is known to have a higher annual energy yield compared to a 2-terminal configuration. Additionally, scaling up the tandem device by using a 4 cm2 perovskite module on a 4 cm2 IBC silicon cell, a tandem efficiency of 25.3% was achieved, surpassing the stand-alone efficiency of the silicon cell.

Manoj Jaysankar, doctoral researcher at imec/EnergyVille, adds: “We have been working on this tandem technology for two years now, and the biggest difference with previous versions is in the engineering and processing of the Perovskite absorber, tuning its bandgap to optimize the efficiency for tandem configuration with silicon.”

“Adding Perovskite on top of industrial silicon PV may prove to be the most cost-effective approach to further improve the efficiency of photovoltaics,” concludes Tom Aernouts, group leader for thin-film photovoltaics at imec/EnergyVille. “Therefore, we invite all companies in the PV value chain that are looking into higher efficiencies, to partner with us and explore this promising path.”

After a quiet period due to the saturation of the mobile handset industry, the GaAs wafer market wakes up.  The technical choice made by Apple creates a real and vast enthusiasm for GaAs solutions. 3D sensing in mobile phone as well as LiDAR’s applications are giving a new breath for GaAs substrates suppliers.

Under its new technology & market report “GaAs Wafer & Epiwafer Market: RF, Photonics, LED and PV applications”, Yole Développement (Yole) announces a 15% CAGR between 2017 and 2023 (in volume), with an impressive 37%, especially for photonics applications (1).

GaAs analysis from Yole proposes a comprehensive overview of the GaAs wafer and epi wafer industry. This report outlines Yole’s understanding of the industrial landscape, its evolution as well as the technical challenges. The analysts are offering a relevant technical description of GaAs wafer and epiwafer growth. Market size and forecasts are also delivered in four big applicative markets: RF, Photonics, LED, and PV. Photonics applications are driving the GaAs wafer and epiwafer market into a new era. Yole’s analysts invite you to discover the latest GaAs technology and market trends.

Figure 1

 As one of the most mature compound semiconductors, GaAs has been ubiquitous as the building block of power amplifiers in every mobile handset. In 2018, GaAs RF business represents more than 50% of the GaAs wafer market. However, market growth has slowed down in the past couple years due to the handset market’s gradual saturation and shrinking die size. “At Yole, we expect GaAs to remain the mainstream technology for sub-6 GHz instead of CMOS, owing to GaAs’ high power and linearity performance as required by carrier aggregation and MIMO technology,” explains Dr. Hong Ling, Technology and Market Analyst at Yole.

Since 2017, GaAs wafer has been particularly notable in photonics applications. When Apple introduced its new iPhone X with a 3D sensing function using GaAs-based lasers, it paved the way for a significant boost in the GaAs photonics market. GaAs wafers market segment for photonics applications should reach US$150 million by 2023.

“GaAs-based ROY and infrared LED applications have also caught our attention”, asserts Dr. Ezgi Dogmus, Technology & Market Analyst at Yole. “We estimate, 2017-2023 CAGR achieves 21% (in units) for the total GaAs LED market, surpassing more than half of GaAs wafer volume by 2023.”

In terms of the wafer and epiwafer businesses, each application requires a different size and quality when determining wafer and epiwafer prices. As a new entrant, photonics applications will impose new specification requirements compared to the well-established RF and LED wafer and epiwafers, creating significant ASP diversity.

From a value chain point of view, the GaAs photonics market’s remarkable growth potential will offer plenty of opportunities for wafer, epiwafer, and MOCVD equipment suppliers, as well as for investors.
GaAs wafer supply: Sumitomo Electric, Freiberger Compound Materials, and AXT, involved in GaAs wafer supply, lead the market with about 95% of market share collectively. And since new laser applications have very high specification requirements for GaAs wafer that are constantly evolving, Yole analysts’ expect the top players to maintain their technical advantage for at least another 3 – 5 years.

Regarding GaAs epiwafer production, Yole’s analysts identified different business models. The GaAs LED market is principally vertically integrated, with very well-established IDMs like Osram, San’an, Epistar, and Changelight. In parallel, GaAs RF businesses outsource significantly from well-established epihouses.

Within the GaAs photonics market, the epi business is still applications-dependent. GaAs datacom market segment is mostly epi-integrated, with dominant IDMs like Finisar, Avago, and II-VI. For 3D sensing in smartphones, epi outsourcing is significant.

In 2017, Apple’s supplier Lumentum used IQE as its VCSEL epi supplier. This resulted in an almost 10x increase in IQE’s stock price. Other leading GaAs epihouses are in qualification or ramping up. Yole expects the photonic epiwafer market to behave similar to the GaAs RF epiwafer market.