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By Pete Singer

Increasingly complicated 3D structures such finFETs and 3D NAND require very high aspect ratio etches. This, in turn, calls for higher gas flow rates to improve selectivity and profile control. Higher gas flow rates also mean higher etch rates, which help throughput, and  higher rates of removal for etch byproducts.

“Gas flow rates are now approaching the limit of the turbopump,” said Dawn Stephenson, Business Development Manager – Chamber Solutions at Edwards Vacuum. “No longer is it only the process pressure that’s defining the size of the turbopump, it’s now also about how much gas you can put through the turbopump.”

Turbopumps operate by spinning rotors at very high rates of speed (Figure 1). These rotors propel gases and process byproducts down and out of the pump. The rotors are magnetically levitated (maglev) to reduce friction and increase rotor speed.

Figure 1. Spinning rotors propel gases and process byproducts out of the pump.

The challenge starts with processes that have high gas flow rates, over a thousand sccm, and lower chamber pressures, below 100 mTorr.  Such processes include chamber clean steps where high flows of oxygen-containing gases are used to remove and flush the process byproducts from inside the chamber, through Silicon via (TSV) in which SF6is widely used at high gas flowrates for deep silicon reactive ion etch (RIE) and more recently, gaseous chemical oxide removal (COR) which typically uses HF and NH3to remove oxide hard masks.

However, the challenge is intensified with the more general trend to higher aspect ratio etch across all technologies.

Stephenson said the maximum amount of gas you can put through a maglev turbo is determined by two things: the motor power and the rotor temperature. Both of these are affected adversely by the molecular weight of the gas. “The heavier the molecule, the lower the limit. For motor power, if the gas flow rate is increased, the load on the rotor is increased, and then you need more power. Eventually you reach a gas flow at which you exceed the amount of power you have to keep the rotor spinning and it will slow down,” she said.

The rotor temperature is an even bigger limiting factor. “As gas flow rates increase, the number of molecules hitting the rotor are increased. The amount of energy transferred into the rotors is also increased which elevates the temperature of the rotor. Because the rotor is suspended in a vacuum and because it’s levitated, it’s not very easy to remove that heat from the rotor because its primary thermal transfer is through radiation,” she explained.

Pumping heavier gases, particularly ones that have poor thermal conductivity, cause the rotor temperature to rise, leading to what is known as “rotor creep.”Rotor creep is material growth due to high temperature and centrifugal force (stress).  Rotor creep deformation over time narrows clearances between rotor and stator and can eventually lead to contact and catastrophic failure (Figure 2).

Figure 2. Edwards pumps have the highest benchmark for rotor creep life temperature in the industry, due to the use of a premium aluminum alloy as the base material for its mag-lev rotors, combined with a low stress design.

Where it gets even worse are in applications where the turbopump is externally heated to reduce byproduct deposition inside the pump. Such a heated pump will have a higher baseline rotor temperature and significantly lower allowable gas flowrates than an unheated one. This becomes a challenge particularly for the heated turbopumps on semiconductor etch and flat panel display processes using typical reactant gases such as HBr and SF6.  “Those are very heavy gases with low thermal conductivity and the maximum limit of the turbopump is actually quite low,” Stephenson said.

The good news is that Edwards has been diligently working to overcome these challenges. “What we have done to maximize the amount of gas you can put into our turbopumps is to  ensure our rotors can withstand the highest possible temperature design limit for a 10 year creep lifetime.   We use a premium alloy for the base rotor material and then beyond that we have done a lot of work with our proprietary modeling techniques to design a very low stress rotor because the creep is due to two factors: the temperature and the centrifugal stress. Because of those two things combined, we’re able to achieve the highest benchmark for rotor creep life temperature in the industry,” she said.

Furthermore, the company has worked on thermal optimization of the turbopump platform. “That means putting in thermal isolation where needed to try to help keep the rotor and motor cool. At the same time, we also need to keep the gas path hot to stop byproducts from depositing. We have also released a high emissivity rotor coating that helps keep the rotor cool,” Stephenson said. A corrosion resistant, black ceramic rotor coating is used to maximize heat radiation, which helps keep the rotor cool and gives more headroom on gas flowrate before the creep life temperature is reached.

Edwards has also developed a unique real-time rotor temperature sensor: Direct, dynamic rotor temperature reporting eliminates over-conservative estimated max gas flow limits and allows pump operation at real maximum gas flow in real duty cycle while maintaining safety and lifetime reliability.

In summary, enabling higher flows at lower process pressures is becoming a critical capability for advanced Etch applications, and Edwards have addressed this need with several innovations, including optimized rotor design to minimize creep, high emissivity coating, and real time temperature monitoring.

By Dave Lammers

The semiconductor industry is collecting massive amounts of data from fab equipment and other sources. But is the trend toward using that data in a Smart Manufacturing or Industry 4.0 approach happening fast enough in what Mike Plisinski, CEO of Rudolph Technologies, calls a “very conservative” chip manufacturing sector?

“There are a lot of buzzwords being thrown around now, and much of it has existed for a long time with APC, FDC, and other existing capabilities. What was inhibiting the industry in the past was the ability to align this huge volume of data,” Plisinskisaid.

While the industry became successful at adding sensors to tools and collecting data, the ability to track that data and make use of it in predictive maintenance or other analytics thus far “has had minimal success,” he said. With fab processes and manufacturing supply chains getting more complex, customers are trying to figure out how to move beyond implementing statistical process control (SPC) on data streams.

What is the next step? Plisinski said now that individual processes are well understood, the next phase is data alignment across the fab’s systems. As control of leading-edge processes becomes more challenging, customers realize that the interactions between the process steps must be understood more deeply.

“Understanding these interactions requires aligning these digital threads and data streams. When a customer understands that when a chamber changes temperature by point one degrees Celsius, it impacts the critical dimensions of the lithography process by X, Y, and Z. Understanding those interactions has been a significant challenge and is an area that we have focused on from a variety of angles over the last five years,” Plisinski said.

Rudolph engineers have worked to integrate multiple data threads (see Figure), aligning various forms of data into one database for analysis by Rudolph’s Yield Management System (YMS). “For a number of years we’ve been able to align data. The limitation was in the database: the data storage, the speed of retrieval and analysis were limitations. Recently new types of databases have come out, so that instead of relational, columnar-type databases, the new databases have been perfect for factory data analysis, for streaming data. That’s been a huge enabler for the industry,” he said.

Rudolph engineers have worked to integrate multiple data threads into one database.

Leveraging AI’s capabilities

A decade ago, Rudolph launched an early neural-network based system designed to help customers optimize yields. The software analyzed data from across a fab to learn from variations in the data.

“The problem back then was that neural networks of this kind used non-linear math that was too new for our conservative industry, an industry accustomed to first principle analytics. As artificial intelligence has been used in other industries, AI is becoming more accepted worldwide, and our industry is also looking at ways to leverage some of the capabilities of artificial intelligence,” he said.

Collecting and making use of data with a fab is “no small feat,” Plisinskisaid, but that leads to sharing and aligning data across the value chain: the wafer fab, packaging and assembly, and others.

“To gain increased insights from the data streams or digital threads, to bring these threads all together and make sense of all of it. It is what I call weaving a fabric of knowledge: taking individual data threads, bringing them together, and weaving a much clearer picture of what’s going on.”

Security concerns run deep

One of the biggest challenges is how to securely transfer data between the different factories that make up the supply chain. “Even if they are owned by one entity, transferring that large volume of data, even if it’s over a private dedicated network, is a big challenge. If you start to pick and choose to summarize the data, you are losing some of the benefit. Finding that balance is important.”

The semiconductor industry is gaining insights from companies analyzing, for instance, streaming video. The network infrastructures, compression algorithms, transfers of information from mobile wireless devices, and other technologies are making it easier to connect semiconductor fabs.

“Security is perhaps the biggest challenge. It’s a mental challenge as much as a technical one, and by that I mean there is more than reluctance, there’s a fundamental disdain for letting the data out of a factory, for even letting data into the factory,” he said.

Within fabs, there is a tug of war between equipment vendors which want to own the data and provide value-add services, and customers who argue that since they own the tools they own the data. The contentious debate grows more intense when vendors talk about taking data out of the fab. “That’s one of the challenges that the industry has to work on — the concerns around security and competitive information getting leaked out.” Developing a front-end process is “a multibillion dollar bet, and if that data leaks out it can be devastating to market-share leadership,” Plisinski said.

Early adopter stories

The challenge facing Rudolph and other companies is to convince their customers of the value of sharing data; that “the benefits will outweigh their concerns. Thus far, the proof of the benefit has been somewhat limited.”

“At least from a Rudolph perspective, we’ve had some early adopters that have seen some significant benefits. And I think as those stories get out there and as we start to highlight what some of these early adopters have seen, others at the executive level in these companies will start to question their teams about some of their assumptions and concerns. Eventually I think we’ll find a way forward. But right now that’s a significant challenge,”Plisinski said.

It is a classic chicken-and-egg problem, making it harder to get beyond theories to case-study benefits. “What helped us is that some of the early adopters had complete control of their entire value chain. They were fully integrated. And so we were able to get over the concerns about data sharing and focus on the technical challenges of transferring all that data and centralizing it in one place for analytical purposes. From there we got to see the benefits and document them in a way that we could share with others, while protecting IP.”

Aggregating data, buying databases and analytical software, building algorithms – all cost money, in most cases adding up to millions of dollars. But if yields improve by .25 or half a percent, the payback comes in six to eight months, he said.

“It’s a very conservative industry, an applied science type of industry. Trying to prove the value of software — a kind of black magic exercise — has always been difficult. But as the industry’s problems have become so complex, it is requiring these sophisticated software solutions.”

“We will have examples of successful case studies in our booth during SEMICON West. Anyone wanting further information is invited to stop by and talk to our experts,” adds Plisinski.

The development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

BY KIM YESS, Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Fan-out (FO) packaging is one of the most talked- about advanced packaging solutions for heterogeneous integration. Although it has been available for nearly a decade for the chips used in mobile devices, its popularity has spiked in the past two years, thanks to Apple’s adoption of TSMC’s integrated fan-out package-on-package (InFO PoP) for its A10 and A11 processors, and the Apple Watch. As a result, FO has quickly progressed to the mainstream, with outsourced semiconductor and test service providers (OSATs), foundries and integrated device manufacturers (IDMs) vying for market share.

What’s driving FO innovation?

According to Yole Développement, smartphone appli- cation processors are the main beneficiaries of high- density fan-out (HDFO)’s excellent performance and thin profile. As a result, as shown in FIGURE 1, the HDFO market was worth $500 million in 2017 and was predicted to exceed $1 billion if other players, namely Qualcomm, Samsung and Huawei switch to HDFO [1].

Jan Vardaman, TechSearch International, said Apple selected InFO PoP for its A10 processor because of power noise reduction and signal integrity improvement, in addition to being thin enough to enable a low-profile PoP solution as small as 15 x 15 mm.

In addition to HDFO, the market is growing for conventional FO, driven by new applications such as audio CODECs, power management ICs, radar modules and RF[2].

The automotive electronics market—particularly advanced driver assistance systems (ADAS) and autonomous vehicles—is also being explored as a viable application for FO because of the flexibility and fast time to market it provides, as well as the ability to adapt to new sensor system protocols.

Exploring new processes

In this race to provide the most reliable, highest-density solution, many manufacturing approaches have emerged. FO is not only becoming more versatile, it is also reaching high enough densities to offer a cost-effective alternative to 2.5D interposers. As the demand for FO increases, packaging processes are being explored in both the wafer and panel formats. This is driving a need for new and better-performing materials that address more stringent specifications to meet, for example, finer line and space requirements, as well as the improved elongation needed for advanced high-density FO.

Thanks to recent innovations in packaging materials, three new process approaches have been developed to bridge these gaps. One approach involves new carrier- assist release-layer materials for creation of the redistribution layer (RDL)-first/chip-last buildup processes. Another important development is an alternative to lithography dielectric patterning that uses laser-ablated dielectric materials. Lastly, an alternative to the molding process in the chip-first approach that uses a laminated die stencil and gap-fill materials is under development.

Carrier-assist release layer for chip-last FO

Low-density FO is built using a chip-first approach, which involves first placing the chips on a substrate wafer followed by over-mold to create a reconstituted wafer, with subsequent RDL and solder-ball placement. On the other hand, HDFO processes like TSMC’s InFO technology use a chip-last approach. Also known as RDL-first, this approach (with target features of ≤2 μm l/s) begins with a layer-by-layer buildup of the RDL on a carrier wafer, followed by die placement and over-mold.

Currently, manufacturers turn to permanent bonding, followed by backgrinding to remove the carrier wafer. This is because conventional temporary bond/debond materials cannot withstand the downstream RDL processes that subject the build-up layers to high temperatures and vacuum conditions, as well as harsh chemical environments. However, backgrinding is a destructive process, creating debris that can cause damage to the device itself.

The new approach uses neither a temporary nor a permanent bonding process. Instead, it utilizes a release layer on the carrier substrate to allow separation of the FO wafer from the carrier at the end of the process flow.

The challenge with this new method is designing a material that withstands high- temperature process steps as well as strong mechanical stresses without delaminating or distorting the reconstituted wafer. Additionally, the material must be adaptable to the new FO panel-level processes (FOPLP) along with existing round wafers, as the industry innovates in that direction.

Manufacturers are investigating the use of copper foil lamination, as an alternative to physical vapor deposition of the seed layer. The copper laminating process requires a material that is flexible enough to sufficiently laminate layers on top of the substrate, and that can be cured using UV radiation or heat to yield a structurally stable base that meets the thermomechanical and chemical resis- tance requirements of the build-up process.

Additionally, it must be releasable by ultraviolet(UV) laser ablation or other UV exposure. To meet these needs, a new class of so-called “triangle” polymeric materials has been conceived that have advantages over standard-application release layers because they are multi functional. Specifically, these “triangle” materials can be laminated, cured and debonded, adding flexibility to the carrier-assisted process (FIGURE 2).

Dielectric RDL patterning

Traditional RDL patterning uses a complicated, 24-step photolithography process that employs photosensitive dielectric materials and masks to create trace patterns, followed by Cu plating to route the signal from the chip out of the package to the solder balls. This process, developed with round wafers in mind, uses spin-coated dielectrics. Unfortunately, these lithography processes are too costly to utilize in innovative package designs that must meet the stringent requirements for most markets [3].

As the industry moves to HDFO and begins to investigate panel-level processes to reduce cost and improve yield, alternative patterning approaches are being developed that can achieve resolutions down to 5 μm with an ultimate goal of 2 μm l/s. Laser ablation is one alter- native to photolithography for creating finer-featured RDL patterns while achieving all these goals.

The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet processing. In addition, with excimer laser patterning technology, the industry gains a much wider choice of dielectric materials (photopatternable and non-photopatternable) to help achieve further reductions in manufacturing costs as well as enhancements in chip or package performance [4].

By using excimer laser ablation, many process steps and costly materials can be eliminated from the manufacturing flow, including resist coating, baking, developing and resist stripping and etching using harsh chemicals [5].

FIGURE 3 demonstrates the considerable cost savings of laser ablation over photolithography. Activity-based cost modeling was used to carry out the cost comparison between the two processes. With activity-based cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is calculated. The cost of each activity is determined by analyzing the following attributes: time, amount of labor and cost of material required (consumable and permanent), tooling cost, all capital costs, and yield loss associated with the activity.

Laser-ablated patterning is a room-temperature process that works by using a dielectric material to build up RDL fixtures, and excimer and solid-state lasers to ablate the material and direct-write a pattern. Laser ablation allows for depth and side-wall angle control, making it possible to create feature sizes <5 μm. It also reduces chemical waste streams. Additionally, fewer steps, fast removal rates and high throughput lead to a lower-cost solution in comparison with traditional photolithography (Fig. 3).

Photosensitive dielectric materials often fall short of meeting the required mechanical and thermal properties, and therefore need a variety of process “work-arounds” that add to the cost of ownership. Alter- natively, non-photopatternable dielectric materials can be designed using a vast selection of chemical platforms, which improves the possibility of meeting the thermal and mechanical property requirements.

As with all new approaches, laser ablation is not without some challenges. Post-laser-ablation cleaning and debris removal, along with surface roughness as a result of the ablation step, need to be addressed. Additionally, the laser system needs to achieve a high ablation rate for high throughput. While the process costs of laser ablation are lower than photolithography, there is still a significant equipment capacity investment required to add laser tools to the manufacturing line. This may delay overcoming the most critical challenge: convincing the industry to embrace laser ablation patterning over conventional approaches.

Development of the dielectric material is ongoing to further push the resolution of laser-ablated materials. In addition to spin and spray coating, other deposition methods being investigated include slot-die coating, ink-jet printing, Vermeer coating, spray coating and laminate film.

Laminated polymeric die-stencil fill concept

Chip-first is the standard approach for conventional FO packages, including embedded wafer level ball grid arrays (eWLBs), redistributed chip packages (RCPs), M-Series and others. It calls for placing die into the mold compound before the RDL processing steps. One of the challenges of this approach that impacts final yield is the die shift that can occur during the RDL processes. Additionally, in multi-die FOWLP configurations that combine disparate technologies to essen- tially form a system-in-package (SiP), the dies may be of different sizes and heights. Additionally, the mismatch in coefficient of thermal expansion (CTE) between all of the materials involved leads to severe warpage of the reconstituted wafer.

A new carrier-based approach developed to combat this problem replaces the over-mold structure around the dies with a laminated die stencil (FIGURE 4). A release layer is first applied to a carrier, followed by a curable adhesive backing layer. Next, the die stencil film is laminated to the curable adhesive backing layer. The dies are then placed in the stencil openings and attached to the adhesive backing layer during thermal curing. The gaps between the dies and stencil are then filled with a flexible yet curable polymeric material, yielding a stable reconstituted substrate. This is followed by construction of the RDLs while still supported on the carrier. Finally, the reconsti- tuted substrate is released from the carrier.

The stencil can be fabricated as a sheet from a variety of high-temperature-stable thermoplastics including, for example, carbon-fiber-filled polyetheretherketone (PEEK), which has an in-plane CTE of <10 ppm/K.

The pre-formed cavities can be configured for different die sizes and types to fabricate SiP components. The curable adhesive backing layer is comparatively soft and tacky before it is cured. This property allows the die-stencil film to be laminated to the structure at low temperatures.

This process not only addresses the die shift issue that plagues the chip-first approach, it also enables varying levels of die thickness. When placed in the stencil, the polymeric material allows the dies to sink and adjusts itself within the stencil. Once the dies are set, the material is cured, which locks them in place. Additionally, the process offers high-temperature stability, better CTE matching for warpage control, and high throughput.

Summary and conclusion

Fan-out packaging is on track to be a game-changing advanced packaging technology that will enable heterogeneous integration architectures. Applications have already expanded beyond smartphones, with HDFO targeting emerging applications.

Substrate handling and RDL strategies will be increasingly important, if not critical, for both conventional and HDFO technologies. To this end, the development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

The gamut of application needs for wafer support includes simple thinning processes during the backside processing of ultrathin, 300-mm silicon wafers, as well as reconstituted substrates for RDL fabrication. In addition to new materials, novel manufacturing approaches are also needed to further optimize the FO process flow.

KIM YESS is Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Acknowledgements

The author would like to thank Amy Lujan, SavanSys, for her contribution to this article regarding activity- based cost modeling.

References

1. Yole Developpement, “Fan-out Packaging Confirms its Success Story,” 3D InCites, September 14, 2017.
2. P. Garrou, “ITLE 356 SEMI Taiwan Part 1: Fan-out Packaging Players, Applications, and Market Growth,” Solid State Technology, October 2017.
3. H.Hichri,M.Arendt,andM.Gingerella,“Novel Process of RDL Formation for Advanced Packaging by Excimer Laser Ablation,” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1733-1739. doi: 10.1109/ECTC.2016.225
4. H. Hichri, Ibid.
5. R. Zoberbier, M. Souter, “Laser Ablation, Emerging Patterning Technology for Advanced Packaging,” SUSS MicroTec Lithography GmbH, January 2010

Optimized stepping, based on parallel analysis of die placement errors and prediction of overlay errors, can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The productivity benefits of optimized stepping are demonstrated using a test reticle with known die placement errors.

KEITH BEST, Director of Lithography Applications Engineering, Rudolph Technologies, Inc., Wilmington, Mass.

Fan out wafer and panel level packaging (FOWLP/ FOPLP) processes place individual known good die on reconstituted wafer (round) or panel (rectangular) substrates, providing more space between die than the original wafer. The additional space is used to expand (fanout) the die’s I/O connections in order to create a pad array large enough to accommodate solder balls that will connect the die to the end-use substrate.The processes used to create these redistribution layers (RDL) are similar to wafer fabrication processes, using patterns defined by photolithography, with feature sizes typically ranging from a few micrometers to tens of micrometers. The placement and reconstitution molding processes introduce significant die placement errors that must be corrected in the photolithography process to ensure accurate overlay registration among the multiple vias and distribution layers that are built up to form the RDL. The errors can be measured on the lithography tool, but this significantly impacts throughput as the measurement process for each die may take as much or more time than the exposure itself.

Current best-practice methods employ an external metrology system to measure the displacement of each die. This metrology data is converted into a stepper correction file that is sent to the lithography stepper tool, eliminating the need to measure displacement on the stepper and more than doubling stepper throughput. An important enhancement to this method, optimized stepping, varies the number of die per exposure based on a predictive yield analysis of the displacement measurements, potentially multiplying throughput 20X or more. Results obtained using a test reticle that includes intentionally displaced die pads, vias, and RDL features typical of an FOWLP/FOPLP process confirm the validity of the approach.

Introduction

Die placements on reconstituted wafer or panel substrates include translational and rotational placement errors. The pick and place process itself introduces initial error. Additional error is created in the mold process and by instability of the mold compound through repeated processing cycles. As a result, the position of the die must be measured before each exposure in the lithog- raphy system to ensure sufficient registration with the underlying layer.

Displacement errors can be measured in the lithography tool, but the measurements are slow, typically taking as much time as the exposure. Moving the measurement to a separate system and feeding corrections to the stepper can double throughput.

Optimized stepping adds predictive yield analysis to the external measurement and correction procedures and increases the number of die included in the exposure field up to a user-specified yield threshold. FIGURE 1 illustrates the exposure/measurement loop. The measurement and analysis are repeated after each layer is exposed, calculating a new set of corrections. In addition to corrections, the software engine analyzes the displacement errors to predict yield (based on a user desig- nated limit for acceptable registration error) for multiple die exposure fields of varying sizes. The method requires tight integration of the stepper and measurement system with the controlling software.

With RDL features currently reaching sizes as small as 2μm, die placement measurements and pattern overlay registration requirements are also continuing to tighten. The speed of the measurement/correction/prediction calculation for each wafer/panel is also an important consideration. It must be faster than the exposure time to avoid becoming the throughput limiting step. Note that this requirement refers to the total exposure for multiple die per field which can be much less than the time needed to expose each die individually. The metrology system used in this work (Firefly system, Rudolph Technologies) can meet these challenges and measure placement errors for >5,000 die on a 510mm x 515mm panel in less than 10 minutes.

The stepper must be able to accept externally generated corrections for translation, rotation, and magnification.

It must also have a large exposure field and the ability to automatically select different images from the reticle (masking blades), changing the size of the field for each exposure. The stepper used in this work was the JetStep system from Rudolph Technologies.

The third critical piece of the optimized stepping loop is the software engine (Discover software, Rudolph Technol- ogies) which calculates displacement corrections and predicts yield for various multi-die exposure configura- tions. It also enables statistical process control (SPC) and controls genealogy.

Balancing yield and throughput

Optimized stepping uses a reticle that includes multiple exposure fields each comprising die arrays of different sizes. In FIGURE 2 the arrays range from a single die to an 8 X 8 array of 64 die. On a wafer containing random displacement errors, the smallest overlay error will be achieved by aligning the exposure pattern for each die individually. However, this accuracy comes at a high cost of reduced throughput. Optimized stepping analyzes the measured displacement errors and calculates the number of die that will meet a designated overlay error limit for various field sizes. It then selects the combination of fields that maximizes throughput. In operation, the stepper automatically selects the correct reticle image and adjusts the field size to expose the selected array.

The yield prediction algorithm (FIGURE 3) uses a recursive splitting procedure that initially predicts yield for the largest available field. If the prediction does not meet user-defined yield requirements, it splits the field and re-evaluates the prediction, repeating this cycle for decreasing field sizes until all exposures yield satisfactory results. The user designates an aggressiveness factor (larger values mean more aggressive splits) and specifies yield requirements in an exposure shot pyramid that determines the number of failures allowed for each available field size.

Results

Optimized stepping was evaluated using a test reticle with multiple field sizes containing die that included pads, vias and RDL structures typical of FOWLP/FOPLP. The patterns included predefined offsets in some of the structures for feed forward measurement testing. Application of the corrections calculated from the die placement error measurements yielded overlay errors of < +/-3μm (FIGURE 4).

Productivity vs. yield

FIGURE 5 illustrates the potential benefits of optimized stepping applied to a panel process. In the example the panel contains approximately 4,500 die. A conventional serial process, with placement errors measured on the stepper, takes a little over six hours, including three hours for measurement and three hours for exposure. Making the measurements outside the stepper in parallel with the exposure halves the cycle time per panel to three hours, and the exposure time becomes the throughput limiting step. The third case is optimized for productivity, using larger field sizes and more relaxed yield requirements. It reduces cycle time to less than 10 minutes. The final case balances throughput against more stringent yield require- ments and results slightly higher cycle times that are still nearly an order of magnitude shorter than the conventional serial process of the first case.

Conclusion

Optimized stepping can increase lithography throughput by more than an order of magnitude and deliver commensurate reductions in cost of ownership. The method also provides a means to balance productivity (throughput) against yield, adding an extra dimension of flexibility for optimizing profitability. Optimized stepping requires a stepper that can use externally calculated corrections and automatically change field size and reticle position. The metrology system must have sufficient accuracy and speed (faster than the accelerated exposure time). The control software must be able to predict yields based on measured displacement errors and control the stepper. Using a test reticle with known displacement errors, we have verified the accuracy of the metrology system and correction procedures and demonstrated the productivity benefits of optimized stepping.

KEITH BEST is Director of Lithography Applications Engineering, Rudolph Technologies, Inc., Wilmington, Mass.

Smart technologies take center stage tomorrow as SEMICON West, the flagship U.S. event for connecting the electronics manufacturing supply chain, opens for three days of insights into leading technologies and applications that will power future industry expansion. Building on this year’s record-breaking industry growth, SEMICON West – July 10-12, 2018, at the Moscone Center in San Francisco – spotlights how cognitive learning technologies and other disruptors will transform industries and lives.

Themed BEYOND SMART and presented by SEMI, SEMICON West 2018 features top technologists and industry leaders highlighting the significance of artificial intelligence (AI) and the latest technologies and trends in smart transportation, smart manufacturing, smart medtech, smart data, big data, blockchain and the Internet of Things (IoT).

Seven keynotes and more than 250 subject matter experts will offer insights into critical opportunities and issues across the global microelectronics supply chain. The event also features new Smart Pavilions to showcase interactive technologies for immersive, virtual experiences.

Smart transportation and smart manufacturing pavilions: Applying AI to accelerate capabilities

Automotive leads all new applications in semiconductor growth and is a major demand driver for technologies inrelated segments such as MEMS and sensors. The SEMICON West Smart Transportation and Smart Manufacturing pavilions showcase AI breakthroughs that are enabling more intelligent transportation performance and manufacturing processes, increasing yields and profits, and spurring innovation across the industry.

Smart workforce pavilion: Connecting next-generation talent with the microelectronics industry

SEMICON West also tackles the vital industry issue of how to attract new talent with the skills to deliver future innovations. Reliant on a highly skilled workforce, the industry today faces thousands of job openings, fierce competition for workers and the need to strengthen its talent pipeline. Educational and engaging, the Smart Workforce Pavilion connects the microelectronics industry with college students and entry-level professionals.

In the Workforce Pavilion “Meet the Experts” Theater, recruiters from top companies are available for on-the-spot interviews, while career coaches offer mentoring, tips on cover letter and resume writing, job-search guidance, and more. SEMI will also host High Tech U (HTU) in conjunction with the SEMICON West Smart Workforce Pavilion. The highly interactive program supported by Advantest, Edwards, KLA-Tencor and TEL exposes high school students to STEM education pathways and useful insights about careers in the industry.

Releasing its Mid-Year Forecast at the annual SEMICON West exposition, SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide sales of new semiconductor manufacturing equipment are projected to increase 10.8 percent to $62.7 billion in 2018, exceeding the historic high of $56.6 billion set last year. Another record-breaking year for the equipment market is expected in 2019, with 7.7 percent forecast growth to $67.6 billion.

The SEMI Mid-Year Forecast predicts wafer processing equipment will rise 11.7 percent in 2018 to $50.8 billion. The other front-end segment, consisting of fab facilities equipment, wafer manufacturing, and mask/reticle equipment, is expected to jump 12.3 percent to $2.8 billion this year. The assembly and packaging equipment segment is projected to grow 8.0 percent to $4.2 billion in 2018, while semiconductor test equipment is forecast to increase 3.5 percent to $4.9 billion this year.

In 2018, South Korea will remain the largest equipment market for the second year in a row. China will rise in the rankings to claim the second spot for the first time, dislodging Taiwan, which will fall to the third position. All regions tracked except Taiwan will experience growth. China will lead in growth with 43.5 percent, followed by Rest of World (primarily Southeast Asia) at 19.3 percent, Japan at 32.1 percent, Europe at 11.6 percent, North America at 3.8 percent and South Korea at 0.1 percent.

SEMI forecasts that, in 2019, equipment sales in China will surge 46.6 percent to $17.3 billion. In 2019, China, South Korea, and Taiwan are forecast to remain the top three markets, with China rising to the top. South Korea is forecast to become the second largest market at $16.3 billion, while Taiwan is expected to reach $12.3 billion in equipment sales.

The following results are in terms of market size in billions of U.S. dollars:

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers an early perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (SEMS), a detailed report of semiconductor equipment bookings and billings for seven regions and over 22 market segments; and the SEMI Mid-year Forecast, which provides an outlook for the semiconductor equipment market. For more information or to subscribe, please contact SEMI customer service at 1.877.746.7788 (toll free in the U.S.). For more information online, visit: http://info.semi.org/semi-equipment-market-data-subscription

By Paula Doe

Chip testing is becoming smarter and more complex, creating growing requirements to stream data in real time and ensure it is ready to use for analysis, regardless of the vendor source.

Adaptive testing using machine learning to predict die performance in a downstream test can reduce the number of cycles by as much as 40 per cent without compromising test performance, notes Dan Sebban, VP of data analysis, OptimalPlus, who’ll speak on machine learning challenges at SEMICON West’s Test Vision 2020 program. “As devices and their test requirements grow in complexity, the motivation for automating adaptive test greatly increases,” he states, adding that characteristics such as die location on the wafer, defects on neighboring die, condition of the tester, and test values near the specification limits can help predict which die are likely to be good.

“The big issue we see is that while everyone likes the idea of machine learning, it remains a black box model, with little visibility into why it makes the decisions it does,” adds Sebban. In addition, a suitable infrastructure to run, deploy and assess a machine learning model in real time is required. “There is still some hesitation to adopt machine learning. It’s a big change of mindset. While building the confidence to use machine learning will take time and experience, using the technology to automate big data analysis with the relevant infrastructure may be our best alternative to reduce test cost.”

Systems test and parts-per-billion quality become the rule

Systems test will continue to become more prominent and more complex as chips and packages shrink, affirms Stacy Ajouri, Texas Instruments system integration engineer and Test Vision 2020 event chair. “Even IC makers now need to start doing more systems test.” And as more ICs are used in automotive applications, the distinction between consumer and automotive requirements is blurring, driving demand in other markets for higher precision test with parts-per-billion defectivity requirements.

“Intelligent test gets increasingly challenging as devices become more complex and as testing moves from distinguishing good from bad devices to figuring out how to repair and trim marginal devices to make them good,” adds Derek Floyd, Advantest director of business development, this year’s program chair.

“We’re highlighting efforts to create the infrastructure the industry needs to manage big data for machine learning with test platforms from different vendors,” says Ajouri, citing work on new standards for streaming data from the testers and labeling critical steps in consistent language to simplify the use of data from different platforms in real time. “I have 10 platforms from multiple vendors, and I need them to mean exactly the same thing by ‘lot’ so I don’t have to sort it out before I can use the data,” she says.

Are devices becoming too complicated to test at the required price point?

Can testing be economical with up to a million die per wafer, 50 data points per die, a requirement for parts-per-billion accuracy, and the need to identify parts that test good now but that might fail in the future? Organizers of the event invite chipmakers and test suppliers to debate the issue. “The speed of innovation in the semiconductor industry challenges test to keep pace,” notes Floyd. “The product we’re testing is always ahead of the product we have to test it with.”

The two-day event features sessions on automotive test; big data and machine learning for adaptive test; handling and interface issues such as over-the-air testing;  and a general session covering memory and RF test.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $38.7 billion for the month of May 2018, an increase of 21.0 percent compared to the May 2017 total of $32.0 billion. Global sales in May were 3 percent higher than the April 2018 total of $37.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has posted consistent growth of greater than 20 percent for 14 consecutive months, and May 2018 marked the industry’s highest-ever monthly sales,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas led the way once again, with sales increasing by more than 30 percent compared to last year, and sales were up across all major semiconductor product categories on both a year-to-year and month-to-month basis.”

Year-to-year sales increased solidly across all regions: the Americas (31.6 percent), China (28.5 percent), Europe (18.7 percent), Japan (14.7 percent), and Asia Pacific/All Other (8.7 percent). Month-to-month sales increased more modestly across all regions: China (6.3 percent), Japan (2.6 percent), Asia Pacific/All Other (1.2 percent), the Americas (1.1 percent), and Europe (1.0 percent).

The SiC power market is now on the road, asserts Yole Développement (Yole). Therefore, since 2017, the market research and strategy consulting company identified more than 20 strategic announcements, showing the dynamism of this market and attractiveness of the technology. Rohm, Bombardier, Cree, SDK, STMicroelectronics, Infineon Technologies, Littelfuse, Ascatron and more are part of the powerful ecosystem, presenting innovative products and revealing key partnerships and/or M&A .

Today, SiC transistors are clearly being adopted, penetrating smoothly into different applications. Yole’s analysts forecast a US$1.4 billion SiC power semiconductor market by 2023. According to the Power & Wireless team at Yole, this market is showing a 29% CAGR between 2017 and 2023.
Power SiC report, 2018 edition presents Yole’s deep understanding of SiC penetration in different applications including xEV, xEV charging infrastructure, PFC/power supply, PV, UPS, motor drives, wind and rail. In addition, it highlights the state-of-the-art SiC-based devices, modules, and power stacks. Yole’s analysts also describe the SiC power industrial landscape from materials to systems, and analyze of SiC power market dynamics. This report proposes a detailed quantification of the SiC power device market until 2023, in value and volume.

SiC adoption is accelerating: is the supply chain ready? Yole’s analysts reveal today their vision of the SiC industry.

SiC market is still being driven by diodes used in PFC and PV applications. However Yole expects that in five years from now the main SiC device market driver will be transistors, with an impressive 50% CAGR for 2017-2023.

This adoption is partially thanks to the improvement of the transistor performance and reliability compared to the first generation of products, which gives confidence to customers for implementation.

Another key trend revealed by Yole’s analysts is the SiC adoption by automotive players, over the next 5-10 years. “Its implementation rate differs depending on where SiC is being used,” comments Dr. Hong Lin, Technology and Market Analyst, Compound Semiconductors at Yole. “That could be in the main inverter, in OBC or in the DC/DC converter. By 2018, more than 20 automotive companies are already using SiC SBDs or SiC MOSFET transistors for OBC, which will lead to 44% CAGR through to 2023.”

Yole expects SiC adoption in the main inverter by some pioneers, with an inspiring 108% market CAGR for 2017-2023. This will be possible because nearly all carmakers have projects to implement SiC in the main inverter in coming years. In particular, Chinese automotive players are strongly considering the adoption of SiC.

The recent SiC module developed by STMicroelectronics for Tesla and its Model 3 is a good example of this early adoption. The SiC-based inverter, analyzed by System Plus Consulting, Yole’s sister company is composed of 24 1-in-1 power modules. Each module contains two SiC MOSFETs with an innovative die attach solution and connected directly on the terminals with copper clips and thermally dissipated by copper baseplates. The thermal dissipation of the modules is performed thanks to a specifically designed pin-fin heatsink.

“SiC MOSFET is manufactured with the latest STMicroelectronics technology design,” explains Dr. Elena Barbarini, Head of Department Devices at System Plus Consulting. “This technical choice allows reduction of conduction losses and switching losses”. STMicroelectronics is strongly involved in the development of SiC-based modules for the automotive industry. During its recent Capital Markets Day, the leading player details its activities in this field (Source: Automotive & Discrete Group presentation – May 2018). STMicroelectronics is also commited in the development of innovative packaging solutions. . System Plus Consulting proposes today a complete teardown analysis including a detailed estimation of the production cost of the module and its package.

PV has also caught the attention of Yole’s analysts during recent months. China claimed almost the half of the world’s installations in the last year. However due to new governmental regulations, Yole sees a slow down of the PV market in short term and has lowered its expectation of SiC penetration for the segment.

In general, system manufacturers are interested in implementing cost effective systems which are reliable, without any technology choice, either silicon or SiC. “Today, even if it’s certified that SiC performs better than silicon, system manufacturers still get questions about long term reliability and the total cost of the SiC inverter”, comments Ana Villamor, Technology & Market Analyst, Power Electronics & Compound Semiconductors at Yole.

Yole and System Plus Consulting teams will attend SEMICON Europa 2018 (Munich, Germany – November 13-16). During the leading trade show, Dr. Milan Rosina, Senior Technology & Market Analyst, Power Electronics & Batteries at Yole proposes a dedicated WBG presentation on November 15 at 2:30 PM.

SiC and GaN devices have demonstrated their large potential for power electronic applications. During the presentation “GaN and SiC power device: market overview” taken place during the Power Electronics Session, Dr. Rosina proposes an overview of the market, technology and the industrial supply chain. More information available on i-micronews.com, Conferences & Trade Shows section.

By Paula Doe, SEMI

The fast-maturing infrastructure that is enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI checked in with some leading players on the changes they see coming in the next several years for this article series. The trade group is expanding its programming on smart manufacturing to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.

“The ramp of EUV, and the smaller geometries and smaller process margins, will drive an exponential increase in the amount of metrology data to manage,” says Neal Callan, ASML vice president, Silicon Valley. Callan notes that moving to multibeam e-beam inspection will increase data volume from megabytes per second to gigabytes per second and from thousands of data points to millions of data points. “The process is so tight and the margin so small that stochastic variation, or noise, becomes more dominant – at least it’s noise until we can learn to understand and control it. And understanding and controlling this variation will be key to delivering 5nm patterning,” he says.

Single-beam e-beam inspection is already driving large increases in data as engineers extend the slow technology to broad, high-speed defect metrology applications by more intelligently instructing the system where to look for problems. Callan says ASML is now using the scanner data on wafer focus, alignment and leveling. The company is also using the computational lithography model from the design to identify the smallest process windows in the pattern that are most likely to see problems. The model then quantifies the number and significance of those instances.

“The collection of all this diverse data means that tools will need to be plug-and-play so all tool data is instantly available to all systems and software,” says Doug Suerich, PEER Group product evangelist. “We need tools that can be discovered automatically by the network so it can start slurping up data immediately. The adoption of the Interface A (EDA) standard is accelerating and fabs are starting to ask for it. The proliferation of sensors also needs to self-discover. If you are going to add thousands of new sensors into a facility, you can’t afford a time-consuming integration process.”

“We are now seeing that engineers are greedy for more data – if they can get the data, it’s becoming a need-to-have,” adds Tom Ho, BISTel America president. “Getting more data from more sensors, from the sensors on the tool that are not being fully utilized, and from untapped data sources like vibration is another big coming opportunity.”

Process complexity drives demand for feed forward between silos with computational models

ASML co-optimizes its scanner process with etch and reticle process steps. Source: ASML

In addition to the drive for trace-back of data, the increasing complexity of interrelated processes is also driving demand for feed-forward of data. “Feed-forward is becoming more important,” notes Ho. He points to the example of 3D NAND features, now getting so deep that identifying the layer being measured is a challenge unless the signal at the step before can be recognized.

“We need partnerships with our peers to understand how to take advantage of the sensors they use, integrate them with our data, and then feed-forward corrections to the other systems,” concurs Callan. “To drive the best CD uniformity and overlay, we need to co-optimize litho and etch,” agrees Henk Niesing, ASML director of product management. He notes that the company is working with etcher makers to measure the overlay and CD, decompose the finger prints, and then use models to steer automated control that best adjusts both the scanner and the etcher. ASML is also working with Zeiss on co-optimization between the scanner and the reticle to make even higher-order corrections by locally modifying the reticle.

These higher-order corrections, applied on each exposed field, drive the need for even more data, and at higher speed but without higher cost, notes Jan Mulkens, ASML senior fellow. These corrections increase demand for computational metrology, which combines various metrology sources with physics and deep learning models trained on real data to predict and control process results in real time. “We’re working on computational metrology to ideally use all the knobs we have in the fab,” he says.

So far this effort has largely involved linking data between two companies. More consistent data formats would enable data exchange to be extended to more companies. “The software versions also need to be managed for upgrades so they still match after one party updates the system on its tool,“ notes Niesing.

Speakers on these issues of smart manufacturing and data handling at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research & Photonics, ASML, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital,  Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Seimens, Stanford University, TEL, TIBCO Software. See semiconwest.org