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Surface preparation technology provides pristine and stable hydrogen passivated semiconductor surfaces

December 6, 2017

A new technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

BY ROBERT PAGLIARO, RP Innovative Engineering Solutions, LLC, Mesa, AZ

As semiconductor based electronic devices have become smaller, faster, smarter, 3-dimensional, and multi-functional the methods and materials required to fabricate them demand novel approaches to be developed and implemented in the device manufacturing facilities. Amongst the most challenging requirements are the need to lower the thermal budgets of the front end thermal processes and to minimize the semiconductor material consumption that comes with the conventional oxidizing (hydrogen peroxide and ozone based chemistries) wet cleaning processes chemistries such as APM, HPM, SPM and SOM.

A novel wet surface preparation method that removes existing surface contamination and native oxide from semiconductor surfaces and then passivates them with a pristine and stable hydrogen passivated surface has been developed and commercialized by APET Co, Ltd. in a system called the TeraDox. This patented technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

The TeraDox system is an enhanced version of the APET FRD (HF etching, Rinse and Dry). The name TeraDox implies the ability to provide a process chemistry with < 1 ppb impurities, particularly dissolved oxygen, which allows for producing pristine and stable H-passivated semiconductor surfaces. Dilute HF and HCl (dHF and dHCl) are the etching chemistries used for removing the native and chemical oxides from Si, SiGe and Ge surfaces. The TeraDox system has a single vessel wet processor and a wafer transfer/drying hood that allows for a segue between the load, chemical fill, etch, insitu-rinse, dry and unload steps of the process sequence, while keeping the process chemistry and the wafers in a continuous ambient of ultra- pure N2. This equipment and process design eliminate the exposure of the wafers to air and minimizes gas perme- ation throughout the entire oxide removal and H-passiv- ation process sequence. These are all critical elements to achieving the best surface quality results. While there are a variety of important parameters towards achieving a pristine and stable H-passivated surface one of the most enabling ingredients to the APET TeraDox process and equipment IP is the PPT level degassing capability for the UPW and aqueous chemicals used in the H-passivation process. The unique UPW and chemical degassing apparatus require an optimized hardware configuration with membrane contactors and facilities used for the vacuum + UHP N2 sweep gas to achieve a DO degassing efficiency > 99.999%. This ultra-high degassing efficiency allows for a Dissolved Oxygen (DO) concen- tration capability of < 100 ppt.

It has been well proven and documented by multiple world-renowned surface scientists [1,2,3] since the late 1980s that the level of dissolved oxygen (DO), as well as other dissolved impurities (such as CO2, TOC, silica and N2), has a direct impact on the efficiency of H-passivation and the native oxide (initial and changing thickness vs. queue time) that follows the removal of native and chemical oxides from semicon- ductor surfaces. Queue time (Q-time) is the amount of time that the H-passivated wafer are exposed to air before being placed in an inert environment for the subsequent process step (epi, poly silicon, metal, ion implantation etc.). It can be seen in FIGURE 1 how native oxide regrowth occurs after HF treatment in air and UPW vs. exposure time [1].

A similar DO vs. surface oxide and carbon relationship is also verified using encapsulated SIMS. This method uses dynamic SIMS to measure the amount of O, C that are trapped at the epi layer/silicon wafer interface. This has been a widely used characterization method to assess a pre-low temperature epi surface prepa- ration process’ hydrogen surface passivation quality since the early 90s. The typical epi cap is ~80-150nm and is deposited using a 650°C SiH4 source deposition process. The objective is to be able to minimize the thermal budget of the pre-deposition bake step which is required to remove any surface oxides and organics to allow perfect epitaxial deposition with no contami- nants or defects at the interface.

FIGURE 2 demonstrates how the encapsulated SIMS interface O (areal oxide density, AOD) using a 650°C SiH4 no bake Si deposition process is strongly dependent on the DO concentration. Three samples are depicted with different surface preparation conditions, a reference wafer with no surface preparation, a wafer dHF wet processedwith the UPW DO ~ 1ppb, and a wafer dHF wet processed with the DO ~0.1 ppb.

It can be seen in FIGURE 3 how applying a 700C/80T/60s bake before a 650C Si deposition process with the UPW DO at 0.1ppb yields non-detectable O and C. This SIMS data info is relatively old (2010) but is still good for reference. The current APET TeraDox wet process capability can provide non-detectable O and C without a bake before the 650°C Si deposition process.

As mentioned earlier, undesirable native oxide thickness increases with queue time on H-passivated Si, SiGe and Ge surfaces. So, it is important to minimize the Q-time between the H-passivation process and the subsequent process step, but the quality and stability of the H-passivation does need to accommodate practical queue times in a manufacturing environment. The H-passivation from the APET TeraDox process has proven to be stable enough for up to at least 8-hour Q-times for most low temperature process applications, which makes it suitable for most semiconductor device manufacturing facilities.

Aside from the low surface oxygen benefit from having ultra-low DO in this process there are other very important benefits to this as well. Having ultra-low DO prevents water marks, microroughness (faceting), bacterial contamination and material consumption. If there is no DO in the UPW or the etching chemistry then there is no competing mechanism to simultaneously oxidize and etch the semiconductor material during the oxide etch and insitu-rinse steps. If the surface is being oxidized/etched then orientation selective faceting will occur. Faceting leads to gener- ation a mix of mono-, di- and tri- hydride terminations on the different orientations of the semiconductor surface. An example is silicon (100), which if it is kept atomically smooth after the oxide is removed by HF, the surface will be dominated by di-hydride terminations. If the surface is faceted it will contain lower energy mono-hydride terminations. Higher energy hydride bonds lead to better surface stability while the lower energy hydride bonds make the surface less stable and will re-oxidize faster with Q-time.

So in general, the pristineness and the atomic smoothness of the semiconductor surface are what dictates the quality and stability of the H-passivating surface preparation process.

While the TeraDox process performance has continued to improve with the new innovations, the capabilities have surpassed the detection limits of conven- tional measurement methods like encapsulated SIMS characterization. Encapsulated SIMS also has a lot of drawbacks and limitations which make it an impractical process monitoring method in manufacturing facil- ities. The need to have a more sensitive measurement method that can measure “as processed” surfaces in a fast, real time and non-destructive manner had become an urgent requirement.

There are a variety of very good electrical and optical measurement methods that have been in use for many years, but most of them do not provide surface specific information directly. Surface parameters such as surface recombination velocity and lifetime (SRV and Ts) can be calculated relatively accurately using multiple step procedures by measurement methods such as uPCD, QSS-PC, PL and SPV. SRV (surface recombination velocity) and Ts (surface recombination lifetime) are extremely sensitive to surface contamination such as C, O metals and dopants as well as micro- roughness. This diverse sensitivity make it ideal for assessing surface preparation methods.

Until recently, only one measurement technique has been found that can measure the SRV and Teff (effective lifetime) of the surface directly and quickly on as processed H-passivated wafers. While doing a lot of research for the ideal measurement method to pair with the APET TeraDox H-passivation process, it was discovered that an enhanced version of the CADIPT department at the University of Toronto’s PCR-LIC technology, called Quantitative Lock-in Carrierog- raphy and Imaging (Q-LIC), could have the unique and enabling capabilities needed for this application. After completing an array of screening and optimization testing over the course of 8 months, the results have validated Q-LIC as an ideal measurement method for “as processed” H-passivated surfaces. In FIGURE 4, the plot demonstrates the SRV vs Q-time for four different wet cleans and an unprocessed control. The data shows strong evidence of the differentiation between different H-passivation methods (process and equipment), the level of DO in the wet process chemistry, and the dynamically changing surface state over time.

FIGURE 4. Q-LIC SRV measurements vs Q-time for four different HF last wet processes.

APET currently has five patents, related to this technology, integrated on the commercially available TeraDox wet process equipment, four of which include the use of vacuum/N2 sweep degassing with membrane contactors for both the UPW and chemical degassing.

The UPW degassing is done in a separate stand-alone module (called the APET Dox unit) that treats up to 60 lpm of UPW before going to the main unit. All Dox units are guaranteed to have DO < 1 ppb, but all of the units in use to date achieve < 200 ppt. The most recently installed Dox unit system has a base DO level of ~30-40 ppt. Aside from the importance of PPT level degassing of the UPW much attention has also been given towards the design and materials used in the entire TeraDox system to prevent gas permeation into the UPW supply and the process chemistry to achieve optimum H-passivation. The most recent TeraDox related patent that was issued to APET was for chemical degassing. The degassing of the HF and HCl are typically overlooked in this application. Typically, HF comes in ~48% and HCl in ~37% concentrations with the balance of these supplied mixtures is in DO saturated water. So even diluted etching chemistries of up to 400 (UPW) :1 (chemical) ratios will typically still produce a composite DO of > 3ppb in the process vessel, even if the UPW supply is degassed to 0 ppt. Having the unique chemical degassing capability to < 1ppb DO significant improves the overall performance of the H-passivation process. The chemical degassing apparatus is integrated into the HF and HCl chemical delivery lines inside the TeraDox system’s main unit.

In summary, APET has developed and commercialized a unique and enabling wet surface preparation technology, the TeraDox process and equipment, that can produce pristine and stable hydrogen passivated semiconductor surfaces. While there are several critical factors and innovations that enable the TeraDox’s unique process performance capabilities, the fully integrated “dry in/dry out” system design and the unique PPT level degassing of the process chemistries are the most facili- tating features on the TeraDox system.

Acknowledgement

A special thanks to Dr. Andreas Mandelis and his staff at the University of Toronto for their support in optimizing their Q-LIC system to provide data for this paper as well as demonstrating a suitable measurement method for the “as processed” H-passivation application.

References

1. M. Morita et al, J. Appl. Phys. 88 (3), 1 (1990)
2. A. Philipossian, J. Electrochem. Soc. 139 No. 10, 2956 (1992)
3. F. H. Li, M. K. Balazs, and S. Anderson, J. Electrochem. Soc. 152,
G669 (2005)

Solutions for controlling resin bleed out

December 5, 2017

The hows and whys of resin bleed-out (RBO) are discussed, as well as the impact it makes and how to control it.

BY RONGWEI ZHANG, ABRAM CASTRO and YONG LIN, Semiconductor Packaging, Texas Instruments Inc., Dallas, TX

Die attach pastes, which consist of resin, curing agent, catalyst, filler and additives, have been extensively used to attach die onto lead frames in various electronic packages such as small outline integrated circuit (SOIC), thin-shrink small outline package (TSSOP), quad flat package (QFP) and quad-flat no-lead (QFN). One of the issues commonly encountered during package assembly is resin bleed-out (RBO), or epoxy bleed out (EBO). RBO is the separation of some formulation ingredients in the paste from the bulk paste (see FIGURE 1). Depending on die attach paste formulations and lead frame surface chemistry and morphology, bleeding ingredients can be solvents, reactive diluents, low-molecular-weight resins, catalysts, and additives like adhesion promoter. Resin bleed out tends to occur on high energy surfaces such as metal lead frames without any organic coating. In particular, if plasma cleaning is utilized to remove the contaminants prior to assembly, the bleeding issue may become more pronounced due to the increase in surface energy. Bleed-out can occur once die attach pastes are dispensed on to lead frames or during thermal curing. As microelectronics continue to move towards smaller form factor, higher reliability and higher performance, control of RBO becomes increasingly critical for packages where there is a very little clearance between die and die pad edge, or between one die and another in multi-chip modules (MCMs).

How resin bleed-out occurs

When die attach paste is dispensed onto a solid surface like lead frame surface, the paste will typically wet the surface partially. The adhesive force between die attach paste and lead frame surface causes the paste to spread while the cohesive force within the bulk paste will hold the ingredients together and avoid contact with a lead frame surface. The adhesive and cohesive forces are the intermolecular forces such as hydrogen bonding and Van der Waals forces. So the degree of wetting will depend on the balance between adhesive force and cohesive force. Bleed-out occurs when the adhesive force of some formulation ingredients to the substrate is stronger than the cohesive force within the paste. The driving force for bleed out is to minimize the surface energy of the substrate by wetting.

Impact of resin bleed-out

Resin bleed-out can cause several issues if it is not well controlled.

• If the formulation ingredients bleed from the periphery of the die attach pastes and covers the wire bonding area, then issues like non-stick on pad (NSOP) and weak wire bond can occur. It can also be an issue if bleeding occurs from the die attach fillet along die edge to the die top, contaminating the bond pad on die top surface [1].

• Resin bleed-out may affect the adhesion of mold compound to die pad or mold compound to die top surface, both of which can lead to delamination. In particular, die top delamination is strictly not allowed in wire-bonded packages because it can cause the ball bond to be mechanically lifted, thereby leading to electrical failures during temperature cycling [2].

• As the formulation ingredients bleed out of the bulk paste, the composition of die attach paste under die may change accordingly. This can impact the adhesion of die attach to lead frame adversely, leading to an adhesive failure [3].

Influence of surface roughness

There are many factors that can cause resin bleed-out, such as low surface tension of die attach pastes, high surface energy of metal lead frames, surface contami- nation, surface porosity and surface roughness. Here we will focus on the impact of surface roughness, which is critical to achieve high package reliability. Two die attach pastes were dispensed onto three lead frames with different surface roughness. The surface roughness of these three lead frames was characterized by Atomic Force Microscopy (AFM) using the roughness average (Ra) and the roughness ratio (r) (FIGURE 2). The roughness average (Ra) represents the arithmetic average of the deviations from the center plane. The roughness ratio is the ratio between the actual 3-D surface area calculated by AFM and the flat surface. The 3D morphologies of lead frames are shown in FIGURE 3. It was found that (a) there is a good correlation between the roughness ratio and resin bleed-out. As the surface roughness ratio increases, the bleeding becomes increasingly worse; (b) LF1 and LF2 have almost same Ra, but the bleeding performance of DA3 and DA4 are different. This indicates that the roughness average is not a good index for RBO; (c) DA4 is more resistant to bleed out than DA3.

The relationship between surface roughness and the wettability has been described by Young equation (Equ. 1) and Wenzel equation (Equ. 2).

cos0y=(YS-YSL)/YL (1)0
cosöm=rcos0y (2)

Where Ys, YL, YSL are surface tensions of the solid, liquid and interfacial tension between die attach paste and lead frame, respectively; 0y is the Young contact angle, 0m is the measured contact angle, and r is the roughness ratio. As the surface roughness increases, the better the wetting, and the worse the bleed-out if the contact angle is < 90o [4]. This is the case for die attach paste on a metal surface without anti-EBO coating.

Approaches to control resin bleed out

There are several approaches to control or eliminate resin bleed-out. These approaches include modifying formulation by selecting appropriate anti-EBO, using die attach film (DAF)/B-stage epoxy, controlling surface roughness, creating mechanical barrier, and lowering the surface energy of lead frames by surface coating.

• Modifying formulations. Generally, anti-bleeding agents are added to die attach pastes to reduce or eliminate RBO. Different anti-bleeding agents may have different working mechanisms. Some anti- bleeding agents are added to enhance the cohesiveness of the pastes while others are added to form a thin layer with a surface energy lower than the pastes themselves on a lead frame surface [5]. Therefore, tailoring die attach adhesives with appropriate anti-bleeding agents is critical to prevent RBO on different types of lead frames, while maintaining high adhesion to metal lead frames to achieve high reliability.

• Die Attach Film/B-stage Epoxy. The simplest and most effective way to eliminate RBO is to use die attach films or B-stage materials. However, there are limitations associated with this approach. These can include high material cost and capital investment, difficulty to achieve high adhesion and thus high reliability, and limited thermal performance of these materials.

• Mechanical barriers. In some cases, grooves on lead frames are designed in between die attach area and wire bond area to reduce resin bleed-out, as shown in FIGURE 4. This is a simple and cost-effective process. However, this approach may not work well if the bleeding is severe. Similarly, some low surface energy insulating film around a chip can be printed to confine the un-cure pastes to the space defined by the printed pattern [5].

• Vacuum baking. Vacuum baking of ceramic substrates with gold or other metal surfaces has been reported to reduce bleed-out. Several mechanisms were proposed: (a) through removal of polar surface contaminant, which promotes bleed-out of lighter organic resin by dipole attraction or chemical reaction [6]; (b) through reducing the surface energy of the plating surface by the formation of Ni2O3 [7]; (c) through producing a coating of hydrocarbon by oil back streaming toreduce the surface energy [8]. The method is not recommended either due to lack of controllability or due to the detrimental effect on wire bonding quality [7]. A more controlled method to reduce or eliminate RBO is to treat the surface with known chemicals and controlled processes, as discussed below.

• Low surface energy coating. Roughened lead frames have been utilized to enhance package reliability, particularly to meet Automotive Grade 0 requirements or beyond, as they increase surface contact area and enhance mechanical interlocking. As shown in Fig. 2, a small increase in roughness can result in a severe bleed-out. Therefore, increasing surface roughness will promote bleed-out if there is no anti-EBO on the surface. According to Young’s equation, decreasing surface energy will increase the contact angle, i.e. decreasing the wetting of the surface. Therefore, in roughened lead frame manufacturing, a solution of low surface energy material is used to treat roughened lead frames to lower their surface energy to reduce or eliminate RBO. Alternatively, a thin layer of film can be deposited onto the assembly surface by gas plasma technology to modify the surface energy [9]. FIGURE 5 shows water contact angles of lead frames with or without anti-EBO treatment. The anti-EBO coating will increase the contact angle on standard lead frame as explained by Young’s equation. Compared with standard lead frames, roughened lead frames have an increasing roughness and the anti-EBO coating on roughened lead frames further increases contact angle significantly. This can be explained by Wenzel equation, which demonstrates that adding surface roughness will increase surface hydrophobicity if the surface is chemically hydrophobic. In addition, Fig. 5 shows the resin bleed-out performances of a die attach paste (DA2) on these three types of lead frames. Bleed out was observed on the standard lead frame without anti-EBO, but there was no bleeding on both standard and roughened lead frame with anti-EBO coating. The low surface energy anti-EBO coating eliminates resin bleed out.

Summary

This article provides an understanding of how bleeding occurs, the impact of bleeding, and methods to control bleeding. Bleeding is the result of the interaction between die attach pastes and metal lead frames. In particular, we studied the influence of surface roughness on RBO of different die attach materials, and found that there is a good correlation between the roughness ratio and bleed-out performance. Reducing the surface roughness will reduce or eliminate RBO. It is noteworthy that there is a line between reducing roughness to achieve no RBO and increasing roughness to ensure excellent delamination performance for lead frames without Anti-EBO. In terms of die attach pastes, the most effective way to control RBO seems to be the surface coating with anti-RBO without affecting other performances like delamination, or combining this method with others to provide an even better solution.

References

1. B. Neff, J. Huneke, M. Nguyen, P. Liu, T. Herrington, S. K. Gupta, “No bleed die attach adhesives”, IEEE International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005, pp. 1-3.
2. R. W. Zhang, Y. Lin, A. Castro, “Solving delamination in lead frame- based packages”, Chip scale review, 2015, pp. 44-48.
3. S. Kanagavel, D. Hart, “Optimization of die attach to surface-enhanced lead frames for MSL-1 performance of QFN packages”, Chip scale review, 2017, pp. 35-38.
4. J.-C. Hsiung, R.A. Pearson, T.B. Lloyd, “A surface energy approach for analyzing die attach adhesive resin bleed,” J. of Adhesion Science and Technology, 2003, 17, No. 1, pp. 1-13.
5. H. Schonhorn, L. H. Sharpe, “Liquids with reduced spreading tendency”, US Patent 4,483,898.
6. J. Ireland, “Epoxy bleedout in ceramic chip carriers”, Int. J Hybrid Microelectron., 1982, 5, pp. 1-4.
7. M. R. Marks, J. A. Thompson, R. Gopalakrishnan, “An experimental study of die attach polymer bleedout in ceramic packages”, Thin Solid Film, 1994, 252, pp. 54-60.
8. N. Tan, K. H. H. Lim, B. Chin, A. J. Bourdillon, “Engineering surface in ceramic pin grid array packaging to inhibit epoxy bleeding”, The Hewlett-Packard Journal, 1998, pp. 81-89.
9. M. Burmeister, “Elimination of epoxy resin bleed through thin film plasma deposition”, Proceeding of the 36th international IMAPS conference, Boston, MA, 2003, pp. 780-785.

Reveal previously invisible defects and contaminants in advanced packaging applications

December 5, 2017

A new illumination technology compares favorably to conventional bright field illumination.

BY GURVINDER SINGH, Director, Product Management, Rudolph Technologies, Inc., Wilmington, MA

A new optical technique can reveal defects and contaminants that escape conventional inspection technologies in many advanced packaging applications. As wafer level packaging (WLP), and especially fan-out wafer and panel level packaging (FOWLP/FOPLP), gains broader accep- tance, certain classes of defects that are characteristic of these processes present significant challenges to standard optical inspection tools. A new optical technology demonstrates increased sensitivity to transparent defects, such as residual dielectric films and photoresist, which are only marginally visible with conventional tools. At the same time, it is less sensitive to nuisance defects, such as those caused by the varying contrast and texture of grains in metal films, that should correctly be ignored.

Challenges in advanced packaging applications

Advanced packaging processes often involve the use of front-end-like technologies in back-end applications. Fan-out packaging is no exception, and, not surpris- ingly, it is following a similar development path, with increasing circuit complexity accompanied by shrinking circuit geometries. Redistribution layer (RDL) line widths, which were around 20μm in early implementations, will soon reach 2μm and are unlikely to stop there. Just as front-end processes placed increasing emphasis on enhanced process monitoring and control, advanced packaging processes will be forced to include more and better inspection and metrology capability at critical steps to maintain control and improve yields.

Advanced packaging processes, such as fan-out, face unique challenges that, for inspection systems, result in overcounting nuisance defects and undercounting yield-robbing critical defects. These advanced packaging techniques make extensive use of metal and organic polymers. Layers of metal are used to define conductive paths and organic polymer dielectric materials are used to provide insulation between conductors and planar surfaces between the layers. Dark field and bright field inspection results often include tens of thousands of nuisance defects. These occur because the inspection algorithms are designed to find random aberrations in highly repeatable patterns and the variable grain patterns of metal conductors appear as defects when are not. If not excluded, their large numbers can quickly overwhelm the real defects. Metal grain features can be as large as 50μm, much larger than RDL lines, which are currently as small as 2μm, and likely to reach 1μm in the near future.

Another class of defects that has proven difficult for conventional optical inspection techniques is caused by the presence of organic residues left after etching and descumming operations. They are hard to find because these materials tend to be transparent at visible wavelengths, yielding little signal in bright field and dark field inspection. They can be especially troublesome when they occur on contacts such as bumps and pillars. The new illumination method effectively eliminates nuisance noise from metal surface textures and enhances signal strength from organic defects.

Clearfind^TM technology

The results presented here were all acquired using a Firefly^TM inspection system (Rudolph Technologies) that incorpo- rates the new Clearfind (CF) illumination technology¹. The new method takes advantage of the fact that many organic polymers exhibit distinctive optical properties that are not present in metals, silicon or other common inorganic materials used in semiconductor manufacturing. These properties tend to be unique to organic molecules displaying a high degree of conjugation, such as polycyclic aromatic hydrocarbons, and in linear or branched chain organic polymers with multiple regularly interspersed pi-bonds. This phenomenon results in the generation of a readily detectable, high color-contrast signal when the feature is appropriately illuminated against a metallic or other inorganic surface. The emission tends to be anisotropic and therefore less sensitive to surface topography that could potentially direct most ordinary bright field or dark field reflected light away from the detector. This results in increased sensitivity to organic residues and reduced sensitivity to interference from surrounding features. The method has the additional advantage of being relatively insensitive to signal variations caused by metal grains. FIGURE 1 presents a simplified illustration comparing the new technology to traditional white light inspection.

The light source for the new technology is laser based, rather than the broadband source typically used in white light inspection systems. Thus, the light output is more stable in terms of both spectral range and output power. Autofocusing of the samples is accomplished using a patented high speed, near infrared-based laser triangulation system that maintains a constant distance between the imaging optics and the area being scanned. Images are acquired at high speed with a high-resolution camera. The result images compared in this article using bright field, dark field and CF technology were all acquired on the same inspection platform using different illumination techniques.

Through Silicon Via (TSV)

The sample is a 300mm silicon wafer with revealed TSV pillars². TSV nail diameter is about 8μm and the distance between TSVs is about 56μm. The TSVs are on the backside of the wafer and the front side of the wafer is attached to a carrier.

In FIGURE 2a, the top shows a bright field image of two TSVs. The TSV on the left, circled in red, is covered with unetched organic residue and the TSV on the right, circled in green, is completely exposed. In the bright field image both TSVs look good and the residue is not visible. The images at the bottom left of figure 2 were acquired with CF technology and show the same TSVs. The TSV on the left, circled in red, has a bright blob while the one on the right, circled in green, is completely dark. The organic residue remaining on the left TSV now emits a readily detectable signal.

FIGURE 2b shows the inspection result from the full TSV wafer. The dots on the wafer map represent defect locations. There is a heavy concentration of organic residue on TSVs on the right side of the wafer. Metal pads approximately 35μm in diameter will be placed on top of the TSVs. Any organic residue between the TSV and the pad can cause deplanarization, which may result in connectivity issues when the die is stacked together. In addition, organic residue can increase the resistance of the contact when the die is stacked. If the defects are found before the next process step the wafer can be reworked.

Under Bump Metal (UBM)

The sample is a 300mm wafer with RDL and under bump metallization (UBM). The UBM pads are about 50μm wide. In FIGURE 3a, the bright field image of two UBM pads shows the left pad is completely exposed and the right pad is covered with unetched organic film. However, the film is transparent and both pads look good in this image. Note the random metal texture visible in the bright field image, which adds noise and makes sensitive inspection for small defects more difficult. The image at lower left, acquired with CF technology, shows the same pads. The left pad, with no residue, appears black. The right pad, covered by residue, is significantly brighter. Also note that the metal texture seen in the bright field image with absent in CF illumination, permitting sensitive inspection for defects down to the pixel level.

FIGURE 3b shows a map of the full wafer where there is a heavy concentration of defects on UBM pads near the edge of the wafer. As in the TSV example, residue remaining on the UBM pads can cause increased resistance or loss of connectivity to a bump deposited on the pad. Bumps deposited on the residue are higher than normal bumps, leading to loss of coplanarity and connectivity issues. If the problem is found before starting the bump process, the wafer can be reworked and the residues removed.

Redistribution Layer (RDL)

The sample is a 300mm molding compound wafer for fan-out packaging. FIGURE 4a shows a bright field image that includes a UBM pad and several RDL lines. The middle image shows the same area viewed with the new illumination technology. In the bright field image, the metal of the UBM pad and the RDL lines is very similar to the underlying metal visible through an interposed transparent film. The texture and graininess of the metals add noise to the image, increasing the difficulty of detecting small defects. Inspection with bright field illumination resulted in high nuisance defect counts without finding real process issues on the wafer. In FIGURE 4b, the top surface metal features, RDL and UBM, stand out against the background of the transparent film, while the underlying metal features are barely visible. FIGURE 4c shows a full wafer map acquired using CF technology and reveals a rectangular pattern that corresponds to the reticle of the lithography tool. The rectangular pattern was not visible in the bright field wafer map.

FIGURE 5 shows additional RDL inspection results on the same wafer. CF technology revealed thinner lines toward the lower left corner of the reticle pattern. Ultimately, it was determined that these thinner lines were caused by a defect in the condenser lens of the lithography tool. The improved contrast between the first layer metal features in the underlying organic film, and the reduced noise, permitted more accurate and sensitive measurements using the new illumination technology. A bright field inspection of 20 wafers containing the same defect did not detect any thinner lines.

Photoresist

The sample is a 300mm patterned silicon wafer from a large memory manufacturer³. It contains die approximately 11.7mm x 7.6mm in size, and containing arrays of about 9,000 metal pillars, each pillar approximately 22μm in diameter. The customer was interested to know if the new illumination technology would find defects not found by bright field inspection. FIGURE 6a shows a wafer map overlaying bright field defects (blue triangles) and CF defects (green triangles). In both cases the defects appear to be randomly distributed and not clustered. As depicted by the bar chart in FIGURE 6b, bright field illumination found 2,279 defects compared to 289 defects found by CF technology. Most interestingly, only 32 of the defects found by CF technology were also found with bright field inspection. 257 defects would have been missed by bright field inspection. The bar chart (FIGURE 6c) shows the size distribution of defects discovered by both techniques. Bright field inspection found a very large number of small defects (less than 5μm) and more defects larger than 25μm. Defects found by the CF technology were between 5-25μm in size.

FIGURE 7 compares CF technology results (top) and bright field results (bottom). Each vertical pair shows a defect missed by bright field inspection and detected by CF technology. The enhanced brightness and circular shape of the defects detected by the new method strongly imply that they are associated with polymer residues. The enhanced brightness of the defects against the very black background is a unique and valuable feature of CF technology. Overall, these results demonstrate the value of supplementing bright field inspection with CF technology. All of the defects found by CF technology were of sufficient size to impact yield.

Conclusion

Results shown here demonstrate the benefits of imaging with the new CF illumination technology when compared to conventional bright field illumination. The new technology allows detection of transparent organic residues that are not visible with bright field illumination.

It was also shown to detect types and sizes of defects that were not detected by bright field inspection. Equally important, its ability to reduce noise caused by metal texture and graininess significantly improves its sensitivity to small defects on metal features and dramatically reduces the detection of nuisance defects.

References

1. Gurvinder Singh, et al, “Advanced packaging lithography and inspection solution for next generation FOWLP-FOPLP processing”, IEEE Xplore, October 2016.
2. Woo Young Han, et al, “Inspection challenges in wafer level packaging”, International Wafer Level Packaging Conference, October 2017
3. Jonathan Cohen, et al, “Photoresist residue detection in advanced packaging”, International Wafer Level Packaging Conference, October 2017

Broad 3Q 2017 growth – Both globally and in Europe

December 4, 2017

By Walt Custer, Custer Consulting

SEMICON Europa 2017 and productronica were co-located November 14 to 17 at Messe Munchen in Munich, Germany. Attendance was very good and the mood was upbeat.

The third quarter of this year has seen broad growth both globally and also for the European electronic supply chain.

Chart 1 shows 3Q’17/3Q’16 growth by electronic sector for the world. SEMI and PCB process equipment and semiconductors stand out but almost all key sectors expanded.

Chart 2 shows third quarter growth for Europe. SEMI equipment leads but the third quarter Eurozone expansion was broad based.

At productronica, Custer Consulting presented at the “Business Outlook for the Global Electronic Supply Chain” event (with emphasis on Europe). For a copy of Walt’s charts, please email [email protected].

Semiconductor industry continues upward trend toward record year

November 30, 2017

The semiconductor industry continued its upward trend in the third quarter of 2017, notching 12 percent sequential growth with strength across all application markets, according to IHS Markit (Nasdaq: INFO). Global revenue totaled $113.9 billion, up from $101.7 billion in the second quarter of 2017.

As memory prices remain high and the wireless market continues to see strong demand through the fourth quarter, 2017 is shaping up to be a record-breaking year for the semiconductor industry. IHS Markit projects that semiconductor revenue will reach a record-high $428.9 billion in 2017, representing a year-over-year growth rate of 21 percent.

Key growth drivers

All application end markets posted sequential growth over the prior quarter, with wireless communications and data processing categories leading the pack.

Revenue from wireless applications grew faster sequentially in the third quarter of 2017 than any of the other high-level application markets. Semiconductor revenue from wireless applications was a record high $34.8 billion in the third quarter, representing nearly 31 percent of the total semiconductor market. IHS Markit anticipates an even bigger fourth quarter for wireless applications, projecting $37.5 billion in revenue — and more than $131 billion for the full-year 2017.

As the wireless market evolves, this growth can be attributed to a number of factors. ”More complex and comprehensive smartphone systems on a chip are supporting applications such as augmented reality and computational photography,” said Brad Shaffer, senior analyst for wireless semiconductors and applications at IHS Markit. “Premium smartphones have increasing amounts of memory and storage. The radio frequency content in these smartphones has also grown considerably over the past few product generations, with many high-end smartphones now supporting gigabit LTE mobile broadband speeds.”

The memory markets proved once again to be the driving force and highest-growing segment for semiconductors in the third quarter of 2017. “The DRAM industry had another record quarter with $19.8 billion in revenue, exceeding the prior record by more than $3 billion,” said Mike Howard, director for DRAM memory and storage research at IHS Markit. “Prices and shipments were up during the quarter as strong demand for mobile and server DRAM continued to propel the market.”

The NAND industry had another record quarter as well, growing 12.9 percent in the third quarter of 2017, with total revenue reaching $14.2 billion. “Pricing was flat in the quarter, as seasonally strong demand driven by the mobile and solid-state drive segments was able to offset moderate shipment growth,” said Walter Coon, director for NAND flash technology research at IHS Markit. “The market is expected to soften exiting 2017 and into early next year, as the industry transition to 3D NAND technology continues to progress and the market enters a traditionally slower demand period.”

Manufacturer moves

Samsung officially passed Intel to become the number-one semiconductor supplier in the world in the third quarter of 2017, growing 14.9 percent sequentially. Intel now comes in at number two, with SK Hynix securing the third rank in terms of semiconductor revenue for the third quarter.

Among the top 20 semiconductor suppliers, Apple and Advanced Micro Devices (AMD) achieved the highest revenue growth quarter over quarter by 46.6 percent and 34.3 percent, respectively.

There was a good deal of market share movement within the top 10 suppliers throughout the third quarter as well. In terms of semiconductor revenue, Qualcomm surpassed Broadcom Limited to secure the number-five spot, while nVidia made its way into the top 10 ranking for the first time ever. At this time last year, the top five semiconductor companies controlled 40 percent market share of the entire industry. The top five gained 4.2 percent more market share this year over last year, while comprising three memory companies instead of the previous two.

More information on this topic can be found in the latest release of the Semiconductor Competitive Landscaping Tool (CLT) from the IHS Markit Semiconductor Competitive Landscape CLT Intelligence Service.

Soitec announces substrate breakthrough for 3D image sensing devices

November 30, 2017

Soitec, a designer and manufacturer of semiconductor materials for the electronics industry, today announced the latest generation of silicon-on-insulator (SOI) substrates in its Imager-SOI product line designed specifically for fabricating front-side imagers for near-infrared (NIR) applications including advanced 3D image sensors. The new SOI wafers from Soitec are now available in large volumes with high maturity to meet the needs of customers in the growing market for 3D cameras used in augmented reality (AR) and virtual reality (VR), facial-recognition security systems, advanced human/machine interfaces and other emerging applications.

“Our newest Imager-SOI substrates represent a major achievement for our company and a smart way to increase performance in NIR spectrum domain, accelerating new applications in the growing 3D imaging and sensing markets,” said Christophe Maleville, executive vice president of the Digital Electronics Business Unit at Soitec. “Innovative sensor design on SOI is achieved by leveraging our advanced know-how in ultrathin material layer transfer and our extensive manufacturing experience.”

The new SOI substrate makes it possible to simply extend the operating range of high resolution silicon based CMOS image sensors into the NIR spectrum. This optimized version of SOI substrate greatly improves the signal to noise ratio in the NIR spectrum.

The market for 3D imaging and sensing devices is forecast to grow at a CAGR of 37.7 percent over the next five years and reach US$9 billion in sales by 2022, according to Yole Développement. The market research and consulting firm predicts that 2018 will likely see a massive influx of products, with the first applications in mobile electronics and computing.*

Broadcom completes acquisition of Brocade Communications Systems

November 17, 2017

Broadcom Limited (NASDAQ: AVGO) (“Broadcom”), a semiconductor device supplier to the wired, wireless, enterprise storage, and industrial end markets, today announced that it has completed its acquisition of Brocade Communications Systems, Inc. (NASDAQ: BRCD).

Brocade’s common stock will now cease to be traded on NASDAQ. Brocade will operate as an indirect subsidiary of Broadcom and will be led by Jack Rondoni as General Manager. Previously, Rondoni served as Senior Vice President of Storage Networking at Brocade, having joined the company in 2006. Rondoni brings over 20 years of experience in storage, networking and technology.

“We are pleased to complete this transaction, which strengthens Broadcom’s position as a leading provider of enterprise storage and networking solutions and enables us to better serve our OEM customers,” said Hock Tan, President and Chief Executive Officer of Broadcom. “Broadcom has a track record of successfully integrating and growing companies we acquire, enabling us to offer customers a leading portfolio of best-in-class franchises across a diverse set of technologies. We intend to invest in and grow the Brocade business to further enhance its capabilities in mission-critical storage networking.”

Tan continued, “We are pleased to announce Jack’s appointment as General Manager, and would like to welcome the outstanding team of employees at Brocade to the Broadcom family. Together, we will continue to exceed the expectations of our customers.”

“We are very excited to join the Broadcom team and provide compelling benefits for customers and new opportunities for Brocade’s employees,” said Jack Rondoni, General Manager, Brocade business unit. “Broadcom provides us with the scale, resources and complementary capabilities to accelerate growth, execute on our strategic initiatives and extend our market leadership in storage area networking. We share a common culture of innovation and execution, and we look forward to the exciting new growth opportunities we will have as part of the Broadcom team.”

Flexible AMOLED panel supply capacity to exceed demand by 44% in 2018

November 16, 2017

With flexible active-matrix organic light-emitting diode (AMOLED) panel fabs building at a quicker pace than global demand, supply capacity of flexible AMOLED panels is forecast to be 44 percent higher than global demand in 2018, according to IHS Markit (Nasdaq: INFO).

The net area capacity of flexible AMOLED panels is expected to reach 4.4 million square meters in 2018, up 100 percent from 2017. However, demand for flexible AMOLED panels is increasing slower than suppliers’ expectation, at 69.9 percent to 2.4 million square meters in 2018, according to the AMOLED & Flexible Display Intelligence Service by IHS Markit.

“Panel makers had expected that flexible AMOLED panels would penetrate into the smartphone market fast,” said Jerry Kang, principal analyst of display research at IHS Markit. “But, this year, most smartphone brands have focused on LCD or rigid AMOLED wide-screens with an 18:9 or higher aspect ratio rather than curved screens using flexible AMOLED panels because the price of flexible AMOLED module is still much higher.”

According to the OLED Display Cost Model by IHS Markit, it costs 1.5 times more to produce flexible OLED panels in the Gen 6 production line than to make rigid OLED panels in the same Gen 6 line.

“The wide-screen smartphone is expected to maintain its competiveness against one with curved edge screen for a while,” Kang said.

Due to the high cost, smartphone brands use the flexible AMOLED panels for their highest-end product segment, making it more difficult for the second-tier flexible AMOLED panel suppliers to meet the product qualification. “This may result in seriously low fab utilization at the second-tier panel suppliers,” Kang said.

The AMOLED & Flexible Display Intelligence Service covers the latest trend and forecast of the AMOLED display industries (including shadow mask and PI substrates), technology and capacity analysis, and panel suppliers’ business strategies by region.

The OLED Display Cost Model provides more detailed cost analysis of OLED panels, including details of boards, arrays, luminescent materials, encapsulants, direct materials such as driver ICs. The report also covers overheads such as occupancy rate, selling, general and depreciation costs. In addition, this report analyzes OLED panels in a wide range of sizes and applications.

Will Samsung’s 2017 semi capex deliver knockout blow to competition?

November 15, 2017

IC Insights has revised its outlook for semiconductor industry capital spending and will present its new findings in the November Update to The McClean Report 2017, which will be released at the end of this month. IC Insights’ latest forecast now shows semiconductor industry capital spending climbing 35% this year to $90.8 billion.

After spending $11.3 billion in semiconductor capex last year, Samsung announced that its 2017 outlays for the semiconductor group are expected to more than double to $26 billion. Bill McClean, president of IC Insights stated, “In my 37 years of tracking the semiconductor industry, I have never seen such an aggressive ramp of semiconductor capital expenditures. The sheer magnitude of Samsung’s spending this year is unprecedented in the history of the semiconductor industry!”

Figure 1 shows Samsung’s capital spending outlays for its semiconductor group since 2010, the first year the company spent more than $10 billion in capex for the semiconductor segment. After spending $11.3 billion in 2016, the jump in capex expected for this year is simply amazing.

To illustrate how forceful its spending plans are, IC Insights anticipates that Samsung’s semiconductor capex of $8.6 billion in 4Q17 will represent 33% of the $26.2 billion in total semiconductor industry capital spending for this quarter. Meanwhile, the company is expected to account for about 16% of worldwide semiconductor sales in 4Q17.

IC Insights estimates that Samsung’s $26 billion in semiconductor outlays this year will be segmented as follows:

3D NAND flash: $14 billion (including an enormous ramp in capacity at its Pyeongtaek fab)

DRAM: $7 billion (for process migration and additional capacity to make up for capacity loss due to migration)

Foundry/Other: $5 billion (for ramping up 10nm process capacity)

IC Insights believes that Samsung’s massive spending outlays this year will have repercussions far into the future. One of the effects likely to occur is a period of overcapacity in the 3D NAND flash market. This overcapacity situation will not only be due to Samsung’s huge spending for 3D NAND flash, but also to its competitors in this market segment (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) responding to the company’s spending surge. At some point, Samsung’s competitors will need to ramp up their capacity or loose market share.

Samsung’s current spending spree is also expected to just about kill any hopes that Chinese companies may have of becoming significant players in the 3D NAND flash or DRAM markets. As our clients have been aware of for some time, IC Insights has been extremely skeptical about the ability of new Chinese startups to compete with Samsung, SK Hynix, and Micron with regards to 3D NAND and DRAM technology. This year’s level of spending by Samsung just about guarantees that without some type of joint venture with a large existing memory suppler, new Chinese memory startups stand little chance of competing on the same level as today’s leading suppliers.

Gigaphoton announces new roadmap for DUV light source

November 14, 2017

Gigaphoton Inc., a manufacturer of light sources used in semiconductor lithography, announced its intention to draw up a new roadmap with the aim of improving the availability of the equipment, and also to respond to the needs of the semiconductor chip manufacturers who are being confronted with increasingly high demands.

Gigaphoton recently drew up a roadmap titled “RAM Enhancement” to enhance the Reliability, Availability, and Maintainability of the Excimer laser, a DUV light source. The company has already started off on overcoming the “99.8%-availability” barrier by 2020, which is the threshold limit value in the industry.

The availability of lithography tools is a key parameter which has a major impact on manufacturing IC chips. In line with this, maximizing the availability requires “long-term stable operation” and “minimized maintenance time.” To achieve both of the above, Gigaphoton is now striving to extend module lifetime and improve on-site unit serviceability that the company’s field engineers provide to customers, aiming at maintenance with the minimum number of machine stops.

To achieve “long-term stable operation,” the company is now increasing each lifetime of major modules such as the chamber (AMP CH), the line narrow module (LNM), and the monitor module (MM) up to 120 Bpls. As for “minimized maintenance time,” new software which automatically calculates expected unit lifetime and the right time for maintenance is ready to be introduced.

With these efforts, the company are now in the course of reducing the required number of maintenance down to only once per year as well as the mean time between module replacement down to half the conventional hours, and also overcoming the barrier of 99.8%-availability on every customer site by 2020. (This is on the assumption that memory chip makers use 60Bpls/year.)

Katsumi Uranaka, President & CEO of Gigaphoton commented, “Along with the increasing demand for semiconductor chips in recent years, the availability of semiconductor manufacturing equipment is becoming increasingly important. The ‘RAM Enhancement’ roadmap which we are promoting was formulated in order to meet these customer needs. From now on as well, Gigaphoton will continue to provide the optimum solutions, while taking into consideration the demands of our customers and also the market trends. ”