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Leti demonstrates world’s first 300mm wafer-to-wafer direct hybrid bonding with 1-micron pitch

November 13, 2017

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and Leti, an institute of CEA Tech, today announced the world’s first successful 300-mm wafer-to-wafer direct hybrid bonding with pitch dimension connections as small as 1µm (micron). This breakthrough also achieved copper pads as small as 500nm.

The copper/oxide hybrid bonding process, a key enabler for 3D high-density IC applications, was demonstrated in Leti’s cleanrooms using EVG’s fully automated GEMINI FB XT fusion wafer bonding system. This result was obtained in the framework of the program IRT Nanoelec headed by Leti. EVG joined the institute’s 3D Integration Consortium in February 2016.

Wafer bonding an enabling process for 3D device stacking

Vertical stacking of semiconductor devices has become an increasingly viable approach to enabling continuous improvements in device density and performance. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected device on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices. The constant reduction in pitches that are needed to support component roadmaps is fueling tighter wafer-to-wafer bonding specifications with each new product generation.

Demonstration results

In the Leti demonstration, the top and bottom 300mm wafers were directly bonded in the GEMINI FB XT automated production fusion bonding system, which incorporates EVG’s proprietary SmartView NT face-to-face aligner and an alignment verification module to enable in-situ post-bond IR alignment measurement. The system achieved overlay alignment accuracy to within 195nm (3-sigma) overall, with mean alignment results well centered below 15nm. Post-bake acoustic microscopy scans of the full 300mm bonded wafer stack as well as specific dies confirmed a defect-free bonding interface for pitches ranging from 1µm to 4µm with optimum copper density.

Focused Ion Beam Scanning Electron Microscope (FIB-SEM) cross-section of 1-µm pitch copper pads on a pair of 300-mm wafers bonded with the GEMINI®FB XT automated production fusion bonding system from EV Group. Photo courtesy of Leti.

“To our knowledge, this is the first reported demonstration of sub-1.5µm pitch copper hybrid bonding feasibility,” said Frank Fournel, head of bonding process engineering at Leti. “This latest demonstration represents a real breakthrough and important step forward in enabling the achievement and eventual commercialization of high-density 3D chip stacking.”

This demonstration is summarized in a paper co-authored by Leti, titled “1 µm Pitch Direct Hybrid Bonding with with <300nm Wafer-to-wafer Overlay Accuracy,” which was presented at the 2017 IEEE S3S Conference.

“3D integration holds the promise for increased device density and bandwidth as well as lower power consumption for a variety of applications, from next-generation CMOS image sensors and MEMS to high-performance computing,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “As a leader in 3D integration research and development, Leti has been at the forefront in moving this critical technology toward industry adoption and commercialization. EVG shares that vision, and we are pleased to have played a role in supporting Leti’s latest achievement in 3D integration.”

Leveraging EVG’s high-throughput XT Frame platform and an equipment front-end module (EFEM), the GEMINI FB XT automated production fusion bonding system is optimized for ultra-high throughput and productivity. The SmartView NT aligner integrated into the system provides industry-leading wafer-to-wafer overlay alignment accuracy (sub-200nm, 3-sigma). In addition, the GEMINI FB XT can accommodate up to six pre- and post-processing modules for surface preparation, conditioning and metrology steps such as wafer cleaning, plasma activation alignment verification, debonding (allowing pre-bonded wafers to be separated automatically and re-processed if necessary) and thermo-compression bonding.

EVG will showcase the GEMINI FB XT at the SEMICON Europa exhibition being held November 14-17 at the Messe München in Munich, Germany. Attendees interested in learning more about the product, as well as EVG’s full suite of wafer bonding and lithography solutions, are invited to visit the company’s booth #B1-1424.

Transfer technique produces wearable gallium nitride gas sensors

November 10, 2017

A transfer technique based on thin sacrificial layers of boron nitride could allow high-performance gallium nitride gas sensors to be grown on sapphire substrates and then transferred to metallic or flexible polymer support materials. The technique could facilitate the production of low-cost wearable, mobile and disposable sensing devices for a wide range of environmental applications.

Transferring the gallium nitride sensors to metallic foils and flexible polymers doubles their sensitivity to nitrogen dioxide gas, and boosts response time by a factor of six. The simple production steps, based on metal organic vapor phase epitaxy (MOVPE), could also lower the cost of producing the sensors and other optoelectronic devices.

Sensors produced with the new process can detect ammonia at parts-per-billion levels and differentiate between nitrogen-containing gases. The gas sensor fabrication technique was reported November 9 in the journal Scientific Reports.

Abdallah Ougazzaden, director of Georgia Tech Lorraine in Metz, France and Chris Bishop, a researcher at Institut Lafayette, example a sample being processed in a lab at Georgia Tech Lorraine. (Credit: Rob Felt, Georgia Tech).

“Mechanically, we just peel the devices off the substrate, like peeling the layers of an onion,” explained Abdallah Ougazzaden, director of Georgia Tech Lorraine in Metz, France and a professor in Georgia Tech’s School of Electrical and Computer Engineering (ECE). “We can put the layer on another support that could be flexible, metallic or plastic. This technique really opens up a lot of opportunity for new functionality, new devices – and commercializing them.”

The researchers begin the process by growing monolayers of boron nitride on two-inch sapphire wafers using an MOVPE process at approximately 1,300 degrees Celsius. The boron nitride surface coating is only a few nanometers thick, and produces crystalline structures that have strong planar surface connections, but weak vertical connections.

Image shows wafer-scale processed AlGaN/GaN sensors being tested. (Credit: Georgia Tech Lorraine).

Aluminum gallium nitride (AlGaN/GaN) devices are then grown atop the monolayers at a temperature of about 1,100 degrees Celsius, also using an MOVPE process. Because of the boron nitride crystalline properties, the devices are attached to the substrate only by weak Van der Waals forces, which can be overcome mechanically. The devices can be transferred to other substrates without inducing cracks or other defects. The sapphire wafers can be reused for additional device growth.

“This approach for engineering GaN-based sensors is a key step in the pathway towards economically viable, flexible sensors with improved performances that could be integrated into wearable applications,” the authors wrote in their paper.

So far, the researchers have transferred the sensors to copper foil, aluminum foil and polymeric materials. In operation, the devices can differentiate between nitrogen oxide, nitrogen dioxide, and ammonia. Because the devices are approximately 100 by 100 microns, sensors for multiple gases can be produced on a single integrated device.

“Not only can we differentiate between these gases, but because the sensor is very small, we can detect them all at the same time with an array of sensors,” said Ougazzaden, who expects that the devices could be modified to also detect ozone, carbon dioxide and other gases.

The gallium nitride sensors could have a wide range of applications from industry to vehicle engines – and for wearable sensing devices. The devices are attractive because of their advantageous materials properties, which include high thermal and chemical stability.

“The devices are small and flexible, which will allow us to put them onto many different types of support,” said Ougazzaden, who also directs the International Joint Research Lab at Georgia Tech CNRS.

To assess the effects of transferring the devices to a different substrate, the researchers measured device performance on the original sapphire wafer and compared that to performance on the new metallic and polymer substrates. They were surprised to see a doubling of the sensor sensitivity and a six-fold increase in response time, changes beyond what could be expected by a simple thermal change in the devices.

“Not only can we have flexibility in the substrate, but we can also improve the performance of the devices just by moving them to a different support with appropriate properties,” he said. “Properties of the substrate alone makes the different in the performance.”

In future work, the researchers hope to boost the quality of the devices and demonstrate other sensing applications. “One of the challenges ahead is to improve the quality of the materials so we can extend this to other applications that are very sensitive to the substrates, such as high-performance electronics.”

The Georgia Tech researchers have previously used a similar technique to produce light-emitting diodes and ultraviolet detectors that were transferred to different substrates, and they believe the process could also be used to produce high-power electronics. For those applications, transferring the devices from sapphire to substrates with better thermal conductivity could provide a significant advantage in device operation.

Ougazzaden and his research team have been working on boron-based semiconductors since 2005. Their work has attracted visits from several industrial companies interested in exploring the technology, he said.

“I am very excited and lucky to work on such hot topic and top-notch technology at GT-Lorraine,” said Taha Ayari, a Ph.D. student in the Georgia Tech School of ECE and the paper’s first author.

In addition to Ougazzaden, the research team includes Georgia Tech Ph.D. students Taha Ayari, Matthew Jordan, Xin Li and Saiful Alam; Chris Bishop and Youssef ElGmili, researchers at Institut Lafayette; Suresh Sundaram, a researcher at Georgia Tech Lorraine; Gilles Patriarche, a researcher at the Centre de Nanosciences et de Nanotechnologies (C2N) at CNRS; Paul Voss, an associate professor in the Georgia Tech School of ECE; and Jean Paul Salvestrini, a professor at Georgia Tech Lorraine and adjunct professor in the Georgia Tech School of ECE.

The research was supported by ANR (Agence Nationale de Recherche), the National Agency of Research in France through the “GANEX” Project.

CITATION: Taha Ayari, et al., “Gas sensors boosted by two-dimensional h-BN enabled transfer on thin substrate foils: towards wearable and portable applications,” (Scientific Reports, 2017). http://dx.doi.org/10.1038/s41598-017-15065-6

Automotive electronic systems growth strongest through 2021

November 9, 2017

Automotive electronic system sales are forecast to rise by a compound annual growth rate (CAGR) of 5.4% from 2016 through 2021, which is the highest among six major end-use system categories (Figure 1), according to data presented in the 2018 edition of the IC Insights’ IC Market Drivers—A Study of Key System Applications Fueling Demand for Integrated Circuits that will be released later this year.

Demand is rising for electronic systems in new cars with increasing attention focused on self-driving (autonomous) vehicles, vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) communications, as well as on-board safety, convenience, and environmental features, and growing interest in electric vehicles. Automotive electronics is growing as technology becomes more widely available on mid-range and entry-level cars and as consumers purchase technology-based aftermarket products. For semiconductor suppliers, this is good news as analog ICs, MCUs, and a great number of sensors are required for many of these automotive systems.

The automotive segment is expected to account for an estimated 9.1% of the $1.49 trillion total worldwide electronic systems market in 2017 (Figure 2), a slight increase from 8.9% in 2015, and 9.0% in 2016. Automotive’s share of global electronic system production has increased only incrementally through the years, and is forecast to show only marginal gains as a percent of total electronic systems market through 2021, when automotive electronics are forecast to account for 9.8% of global electronic systems sales. Though many electronics systems are being added in new vehicles, IC Insights believes pricing pressures on both ICs and electronic systems will keep the automotive end-use application from accounting for much more than its current share of total electronic systems through the forecast period.

Other electronic system and IC market highlights from the 2018 IC Market Drivers Report include the following.

• The automotive segment is forecast to be the fastest growing electronic system market through 2021. This is good news for the total automotive IC market, which is forecast to surge 22% in 2017 and 16% in 2018.

• Industrial electronic systems are forecast to enjoy the second-fastest growth rate (4.6%) through 2021 as robotics, wearable health devices, and systems promoting the Internet of Things help drive growth in this segment. Analog ICs are forecast to hold 45% of the industrial IC market in 2017.

• The 2016-2021 communication systems CAGR is projected to be 4.2% as global sales of smartphones and other mobile devices reach saturation. Asia-Pacific is forecast to show the strongest regional growth of communication systems and account for 69% of the total communications IC market in 2017.

• The consumer electronic systems market is forecast to display a CAGR of 2.8% through 2021. The logic segment is forecast to be the largest consumer IC market throughout the forecast. In total, the consumer IC market is expected to register a 2.4% CAGR across the 2016-2021 time period.

• Flat or marginal demand for personal computing devices (desktops, notebooks, tablets) is expected to result in the computer systems market showing the weakest CAGR through 2021. The total computer IC market is forecast to increase 25% in 2017 driven by much higher average selling prices for computer DRAM and NAND flash memory.

Temperature impact on UHP pressure transducer performance

November 8, 2017

The temperature impact on the performance of UHP pressure transducers is discussed.

BY YANLI CHEN, Ph.D. and MATTHEW MILBURN, P.E., UCT, Hayward, CA

As the semiconductor industry develops new films that require heated delivery systems, all related components need to be characterized at elevated temperatures. Vacuum pressure measurement components, typically called manometers, have been used at elevated temperatures for many years. In fact, many of the vacuum measurement transducers are internally heated to a known temperature to stabilize the mechanical relationships between moving parts and the sensors used to measure the movement. This stabilization enables the precision and inaccuracy of the measurement to be greatly improved. For positive pressure UHP transducers, this elevated temperature characterization has not been done. Based on the testing performed at UCT, temperature related performance variations are very real and must be carefully considered before choosing a positive pressure transducer for elevated temperature use. Since the industry is driving toward higher delivery system operating temperatures, temperature effects will become more important.

The UHP pressure transducer is a widely-used component in the semiconductor industry and the performance is very important for process control and process monitoring. Selecting a proper UHP pressure transducer with good performance for the specific application is challenging, because different UHP pressure transducers manufacturers have different parameters listed in their data and specification sheets. Behind the data presented, it was found that different test procedures and data processing methods were used to determine and report performance characteristics. This reality creates a situation where, without standardized test method or reporting format, neither the specifier nor the end user can compare the performance of different brands of pressure transducers. To date, the industry has not recognized the full scope of the specification problem nor developed a standardized testing and reporting program. A new push toward standardization has become available with the publishing of SEMIF113 “Test Method For Pressure Transducers Used In Gas Delivery Systems” in November of 2016.

In order to have a better understanding about the performance of different UHP pressure transducer manufacturers’ products, UCT initialized a comprehensive performance evaluation project with a participation of three major UHP pressure transducer manufacturers (MFG A, MFG B and MFG C). The totality of the project covered a total of nine test categories, including warm up time test, input voltage sensitivity test, repeatability, linearity, hysteresis and inaccuracy test, reproducibility test, thermal coefficient test, drift test, accelerated lift cycle test, proof and burst test. The topic of this paper is the thermal coefficient test. Interested readers can find the other article “Comprehensive performance evaluation of UHP pressure transducers” published on the VOL. 59 NO. 4 of Solid State Technology (June 2016), which demonstrated the test method of repeatability, linearity, hysteresis and inaccuracy.

Ideally, a pressure transducer would sense pressure and remain unaffected by other environmental changes. In reality, however, the signal output of every pressure transducer is somewhat affected by variations in environment and fluid temperature. Temperature changes can cause the expansion and contraction of the sensor materials, fill fluids, housings, and electronics. Temperature changes also can affect the sensor’s resistors and electrical connections through the thermoelectric effects. Typically, a sensor’s behavior regarding changes in temperature is characterized by two temperature coefficients: temperature effect on zero (TC zero) and temperature effect on span (TC Span). TC zero is expressed as a percentage of full scale and indicates the greatest deviation of a pressure transducer at zero setpoint per equal temperature change (such as 10K or 50°C) during the operating temperature range. TC span is also expressed as a percentage of full scale and indicates the greatest deviation of a pressure transducer at 100%FS setpoint per equal temperature change (such as 10K or 50°C) during the operating temperature range. FIGURES 1, 2 and 3 list the TC zero and TC span of pressure transducer products of MFG A, MFG B and MFG C, respectively.

Comparing the three thermal coefficient specifications above for MFG A, MFG B and MFC C, it is not possible to conclude which manufacturer’s product is the best for thermal behavior. Therefore, a standard test method and data process for thermal effects evaluation is needed.

Test setup and procedure

Three major UHP pressure transducer manufacturer (MFG A, MFG B, and MFG C) participated in this comprehensive performance evaluation project by providing test samples. Table 1 shows the detailed information of all the devices under tests (DUTs). Twelve DUTs were installed in a test fixture designed by UCT for running simultaneous tests. The schematic of the test fixture is shown in FIGURE 4. The benefit of this design is to save significant time that would be otherwise used for assembly, disassembly, and testing, and eliminates the potential for setup errors if each transducer was tested separately in the battery of tests.

The test was conducted in a temperature controlled environmental chamber (see Figure 5). The following sequence of steps were taken:

• A leak integrity test
• Make the initial zero adjustment per the manufacturer’s instructions
• Adjust the temperature of the environmental chamber to 0°C and allow the temperature to stabilize for a minimum period of two hours.
• Adjust the pressure to 0% FS (-14.7 psig), and record the signal output of all the DUTs and the pressure reference device after the pressure stabilization.
• Adjust the pressure to 100% FS(235.3 psig),andrecord the signal output of all the DUTs and the pressure reference device after the pressure stabilization.
• Repeat the same procedure for the temperature setpoints of 20°C, 40°C and 60°C at the pressure setpoints of 0%FS and 100%FS.

Results and discussion

The TC zero (0%FS) and TC span (100%FS) values of all DUTs are listed in Table 2. For each manufacturer’s sample group, the highest value for the thermal coefficients at zero and span are highlighted in red; the lowest value for the thermal coefficients at zero and span are highlighted in green. To reiterate, the smaller the TC value, the better.

• For the DUTs from MFG A, the smallest TC zero is 0.0022%FS/°C and the smallest TC span is 0.0324%FS/°C.
• For the DUTs from MFG B, the smallest TC zero is 0.0012%FS/°C and the smallest TC span is 0.0099%FS/°C.
• For the DUTs from MFG C, the smallest TC zero is 0.0102%FS/°C and the smallest TC span is 0.0215%FS/°C.
• For the DUTs from MFG A, the largest TC zero is 0.0127%FS/°C and the largest TC span is 0.0564%FS/°C.
• For the DUTs from MFG B, the largest TC zero is 0.0042%FS/°C and the largest TC span is 0.0155%FS/°C.
• For the DUTs from MFG C, the largest TC zero is 0.0283%FS/°C and the largest TC span is 0.0354%FS/°C.

The extreme TC values for each manufacturer are summarized in Table 3. As shown in this table, the MFG B product has the lowest value (0.0042%FS/°C) and MFG C product has the highest value (0.0283%FS/°C) for the TC zero. For the TC span, the MFG B product still has the lowest value (0.0155%FS/°C), and the MFG A product has the highest value (0.0564%FS/°C).

To compare the results to the published specification from MFG A, the results needed to be converted and are listed in Table 4.

Comparing test results with the published specifications (FIGURE 1), the MFG A devices are meeting their thermal coefficient specification.

To compare the results to the published specification from MFG B, the results needed to be converted and are listed in Table 5.

Compared with the published specifications (FIGURE 2), the MFG B devices are meeting their thermal coefficient specification at zero. All the MFG B devices except DUT 6 meet the of the thermal coefficient specification at span. However, the TC span for DUT 6 is 0.15550%FS/10K, which is very close to the specification value (0.15%FS/10K).

To compare the results to the published specification from MFG C, the results needed to be converted and are listed in Table 6.

Compared to the published MFG C specifications (FIGURE 3), the MFG C devices are meeting their thermal coefficient specification.

The error change with the temperature increase of all the DUTs at 0%FS is shown graphically in FIGURE 6. Comparing the three plots, it can be seen that the DUTs from manufacturer C have the largest thermal variation across the temperature range of the test as well as device to device variation. The DUTs from manufacturer B have the smallest thermal variation across the temperature range of the test as well as device to device variation.

The error change with the temperature increase of all the DUTs at 100%FS is shown graphically in FIGURE 7. Comparing the three plots, it can be seen that the DUTs from manufacturer C have the largest thermal variation across the temperature range of the test as well as device to device variation. The DUTs from manufacturer B have the smallest fluctuation across the temperature range.

Conclusion

Based on this study, transducers marketed as comparable to each other display dramatically different performance levels within a relatively small temperature range which could lead to process reproducibility challenges. As the demand for higher temperature applications increases, these temperature performance variances will become more pronounced. These variations may prove to be very problematic with tool-to-tool process replication or when a transducer is replaced as a repair activity and the new transducer does not have the same performance characteristic as the old unit. The test results also demonstrate that the published specifications need to be standardized to improve direct comparison by end users. In addition, a uniform test procedure and data processing method needs to be adopted by the industry. The pressure measurement task force of SEMI North America Gases and Facilities Committee has developed and published a new pressure transducer measurement standard in November of 2016 based on this study.

Temperature-related shift not only contributes to the overall inaccuracy of a pressure transducer in a particular application, but they also factor into the economics of designing and manufacturing pressure transducers. This is due to the fact that temperature compensation is a complex, time-consuming, and expensive process that requires a significantly larger investment in production equipment and a deeper understanding of the influencing parameters.

References

1. Chemical Engineering Progress (CEP), June 2014 Gassmann, E. (2014, June) Pressure Sensor Fundamentals: Interpreting Accuracy and Error, 37-45
2. IEC 61298-3 Process measurement and control devices-General methods and procedures for evaluating performance-Part 3: Tests for the effects of influence quantities
3. SEMI C59-1104-0211R Specifications and Guidelines for Nitrogen
4. SEMI F1-0812 Specification for leak integrity of high-purity gas piping systems and components
5. SEMI F62-1111 Test method for determining mass flow controller performance characteristics from ambient and gas temperature effects
6. SEMI F113-1116 Test method for pressure transducers used in gas delivery systems

The intelligence that leads to artificial intelligence

November 8, 2017

By Ajit Manocha, president and CEO, SEMI

Artificial intelligence (AI) may be a hot topic today, but SEMI has helped to incubate Big Data and AI since its founding. Early in SEMI’s history, SEMI’s always intelligent members worked together to introduce International Standards that enabled different pieces of equipment to collect and later pass data. At first, it was for basic interoperability and equipment state analysis. Later, SEMI data protocol Standards allowed process and metrology data to be used locally and across the fab to approach the goals of Smart Manufacturing and AI – for the equipment itself to make adjustments based on incoming wafer data.

As a part of this evolution, SEMI members developed the latest sensors and computational hardware that could ever better sense, analyze and act on the environment. Often first to use its own newly developed hardware, progress in this area was critical toward improving the likelihood of success for one of the world’s most complicated production processes – and coping with the breakneck speed of Moore’s Law – by accelerating capabilities that would later be regarded as the basis for machine learning and “thinking” systems.

Since then, process steps have increased from about 175 to as many as 1,000 for the leading technology nodes. By the time 300mm wafers were introduced, manufacturing intelligence and automation sharply increased productivity while reducing fab labor by more than 25 percent. Employing adaptive models, modern leading-edge factories are fully automated and operate at nearly 60 percent autonomous control.

Today, AI is akin to where IoT was yesterday in the hype cycle – popping up everywhere as a major consideration for the future. Neither IoT nor AI is hype, though – they’re the future. There is ever more at stake for SEMI members with AI. AI appears to be the next wave helping to maintain double-digit growth for the foreseeable future.

As part of its appeal for the global supply chain, AI can be a key silicon driver for three inflections that should benefit society. First, there is a massive increase in the amount of compute needed. Half of all the compute architectures shipping in 2021 will be supporting and processing AI.

Second, the Cloud will flourish and the Edge will bloom. By 2021, 50 percent of enterprise infrastructure will employ cognitive and artificial intelligence.

Third, new species of chips will emerge, such as the devices fueling IC content and electronics for the rapid growth of disruptive capabilities in vehicles and autonomous cars (as well as medical and agricultural applications, for example). There are also many more advantages created with and for AI as SEMI members enable new materials and advanced packaging.

What results can be measured from these changes for the global electronics manufacturing supply chain? More apps, more electronics, more silicon and more manufacturing.

On the other hand, the technologies alone create relatively little business value if the problems in our factories and markets are not well understood. There’s a great need to anticipate and guide AI. This requires a new kind of collaboration.

To address this need, SEMI’s vertical application platforms have been created for Smart Data (which is all about AI), and also for Smart MedTech, Smart Transportation, Smart Manufacturing and IoT. This higher degree of facilitated collaboration serves to cultivate multiple “smart communities” that accelerate progress for AI, better directing how connected networks and data mining can step up the pace for advancement of global prosperity. This process also provides members with access to untapped business opportunities and new players.

We at SEMI are learning right along with our members. If you attended SEMICON West in July, several lessons about AI were presented by the Executive Panel (“Meeting the Challenges of the 4^th Industrial Revolutions along the Microelectronics Supply Chain”) with Mary Puma (Axcelis), Shaheen Dayal (Intel), Lori Ciano (Brooks Automation) and Regenia Sanders (Ernst & Young). This very timely and excellent panel discussed how and where predictive analytics can have the biggest impact and the implications of sharing (and not sharing) data for problem solving and process optimization.

Ensuring that the SEMI staff gleans everything possible from the experts, we hosted an “encore” of the Executive Panel in October in our headquarters for an even more in-depth discussion about how to enhance collaboration across the supply chain in support of AI.

Going forward, these SEMI vertical platform communities will help to simplify and accelerate supply chain engagement for member value. Collaboration will play an ever greater role for using AI to master the making of advanced node semiconductor devices and enabling limitless cognitive computing. As a result, AI as we know it today, has a big head start over the previous pace of evolution for one of our great trendsetters, Moore’s Law.

Join the conversation. Find out how you can work with SEMI to advance the AI – and especially AI in semiconductor manufacturing. Frank Shemansky Jr., Ph.D., is heading up SEMI’s formation of SEMI’s Smart Data vertical application platform. Let Frank know ([email protected]) you’re interested and he’ll give you more information on what’s to come. As always, please let me know your thoughts.

How to solve the BEOL RC delay problem?

November 7, 2017

The RC delay issues started a few nodes ago, and the problems are becoming worse.

BY ZSOLT TOKEI, imec, Leuven, Belgium

With the 7nm technology node in the development phase and the 5nm node moving into development, transistor scaling gets ever more complex. On top of that, the performance benefits gained at the front-end-of-line (i.e., the transistors) can easily be undone if the back-end-of-line can’t come along. BEOL processing involves the creation of stacked layers of Cu wires that electrically interconnect the transistors in the chip. Today, high-end logic chips easily have 12 to 15 levels of Cu wires. With each technology node, this Cu wiring scheme becomes more complex, mainly because there are more transistors to connect with an ever tighter pitch. Shrinking dimensions also means the wires have a reduced cross-sectional area, which drives up the resistance-capacitance product (RC) of the interconnect system. And this results in strongly increasing signal delay. The RC delay issues started a few nodes ago, and the problems are becoming worse. For example, a delay of more than 30% is expected when moving from the 10nm to the 7nm node.

The current BEOL flow

Cu-based dual damascene has been the workhorse process flow for interconnects since its introduction in the mid 1990s. A simple dual damascene flow starts with the deposition of a low-k dielectric material on a structure. These low-k films are designed to reduce the capacitance and the delay in the ICs. In a next step, this dielectric layer is covered with an oxide and a resist, and vias and trenches are formed using lithography and etch steps. These vias connect one metal layer with the layer above or below. Then, a metallic barrier layer is added to prevent Cu atoms from migrating into the low-k materials (FIGURE 1). The barrier layers are deposited with physical vapor deposition, using materials such as tantalum and tantalum nitride, and subsequently coated by a Cu seed barrier. In a final step, this structure is electroplated by Cu in a chemical mechanical polishing (CMP) step.

A 5nm technology full dual damascene module

The semiconductor industry is hugely in favor of extending the current dual damascene technology as long as possible before moving to a new process. And this starts with incremental changes to the current technology, which should suffice for further scaling to at least the 5nm technology node. Researchers at imec have demonstrated a full dual damascene module for the 5nm technology node. At this node, the BEOL process becomes extremely complex, and interconnects are designed at very tight pitches. For example, a 50% area scaling in logic and 60% scaling of an SRAM cell from 7nm to 5nm results in a gate pitch at around 42nm and an intermediate first routing metal at 32nm pitch (or 16nm half pitch, which is half the distance between identical features). In these BEOL layers, trenches are created which are then filled with metal in a final metallization step. In order to create electrically functional lines, perpendicular block layers to the trenches are added, where metal traces are not formed. One of the many challenges to scaling the interconnects relates to the patterning options. Patterning these tight pitch layers is no longer possible by using single immersion lithography and direct etch steps. Only multi-patterning – which is known to be very costly and complex – is possible either by immersion or by EUV or by a combination of immersion and EUV exposures to form a single metal layer. At IITC, imec showed a full integration flow using multi-patterning, which enables the patterning of tight-pitch metal-cut (the blocks), and effectively scaling the trench critical dimension to 12nm at 16nm half pitch. The researchers also looked at the reliability, for example at electromigration issues caused by the movement of atoms in the interconnect wires. They demonstrated the ability of imec’s Cu metallization scheme at 16nm critical dimension with extendibility to 12nm width, and investigated full ruthenium (Ru) metallization as copper replacement.

Scaling the BEOL beyond the 5nm node

For the technology nodes below the 5nm, the team of imec is investigating a plethora of options and comparing their merits. Options include new materials for conductors and dielectrics, barrier layers, vias, and new ways to deposit them; innovative BEOL architectures for making 2.5D/3D structures; new patterning schemes; co-optimization of system and technology, etc.

For example, to achieve manufacturable processes and at the same time control the RC delay, scaling boosters, such as fully self-aligned vias, are increasingly being used. Via alignment is a critical step in the BEOL process, as it defines the contact area between subsequent interconnect levels. Any misalignment impacts both resistance and reliability. Imec’s team has shown the necessity of using a fully self-aligned via to achieve overlay specifications, and proposed a process flow for 12nm half pitch structures.

Also, self-assembled monolayers (SAMs) open routes to new dielectric and conductor schemes. SAMs composed of sub-1nm organic chains and terminated with desired functional groups can help engineering thin-film dielectric and metal interfaces, and can strongly inhibit interfacial diffusion. The use of SAMs has been a topic of research for the past ten years. Imec has now moved this promising concept from lab to fab, and combined SAMs with a barrier/liner/metallization scheme on a full wafer. The researchers investigated the implica- tions on the performance and scaling ability of this process flow, and demonstrated a ~18% reduction in the RC of 22nm half-pitch dual damascene intercon- nects, due to a better interface and thinner barrier.

For conventional BEOL metallization, a barrier layer is coated by a Cu seed barrier, and this structure is electroplated with low-resistive Cu, which acts as the conductor. But when moving to sub-10nm interconnects, the resistivity of Cu continues to increase. At the same time, the diffusion barrier – which is highly resistive and difficult to scale – is taking up more space, thereby increasing the overall resistance of the barrier/Cu structure. Therefore, alternative metals are being investigated that could possibly serve as a replacement for Cu and do not require a diffusion barrier. Among the potential candidates, such as Co, Ni, Mo, etc., platinum-group metals, especially ruthenium (Ru), have shown great promise due to their low bulk resistivity and resistance to oxidation. They also have a high melting point which can result in better electromigration behavior (FIGURE 2). Imec has realized Ru nanowires with 58nm2 cross section area. The nanowires exhibit low resistivity and robust wafer-level reliability. For example, a very high current carrying capacity with fusing currents as high as 720MA/cm2 was demonstrated.

At the 2017 IITC conference, this author was invited to take part in a panel discussion, organized by Applied Materials, to discuss the latest developments in metallization at single-digit nodes, the challenges and bottlenecks arising at these very small dimensions, and new application-driven requirements. Distinguished speakers from the technical field reviewed viable solutions for extending the current technology and alternative options were discussed. From the discussion it is clear that the biggest immediate benefit can be found in the area of conductors – both from the material side as well as design. Indeed, it is driving the replacement of copper at specific metallization levels. Other avenues – such as dielectric innovations, functionality in the BEOL or 2D materials – remain interesting options for the R&D pipeline.

As an option that is further out, spin wave propagation in conductors is an alternative signaling to traditional electron based propagation.

Adding additional functionality in the BEOL

In the future, more and more technology options may get dictated by the requirements of systems or even applications. This could result in a separate technology for e.g. high-performance computing, low-power mobile communication, chips for use in medical applications, or dedicated chips for IoT sensors. Along the same lines, imec is investigating the benefits of introducing additional functionality in the BEOL.

More specifically, imec is evaluating the possibility of integrating thin-film organic transistors – with typically low-leakage level – into the BEOL interconnect circuitry of Si FinFETs. The potential advantages of fabricating them together are mainly a reduced power consumption and improved area saving. A variety of circuits can fully utilize the benefits of this hybrid processing, including portable applications, eDRAM, displays and FPGA applications. As a concrete example, imec researchers are currently merging imec’s expertise in BEOL technologies and in thin-film-based flat panel displays, thereby opening opportunities for new applications…

Broadcom proposes to acquire Qualcomm

November 6, 2017

Broadcom Limited (NASDAQ: AVGO) (“Broadcom”), a semiconductor device supplier to the wired, wireless, enterprise storage, and industrial end markets, today announced a proposal to acquire all of the outstanding shares of Qualcomm Incorporated (NASDAQ: QCOM) (“Qualcomm”) for per share consideration of $70.00 in cash and stock.

Under Broadcom’s proposal, the $70.00 per share to be received by Qualcomm stockholders would consist of $60.00 in cash and $10.00 per share in Broadcom shares. Broadcom’s proposal represents a 28% premium over the closing price of Qualcomm common stock on November 2, 2017, the last unaffected trading day prior to media speculation regarding a potential transaction, and a premium of 33% to Qualcomm’s unaffected 30-day volume-weighted average price. The Broadcom proposal stands whether Qualcomm’s pending acquisition of NXP Semiconductors N.V. (“NXP”) is consummated on the currently disclosed terms of $110 per NXP share or the transaction is terminated. The proposed transaction is valued at approximately $130 billion on a pro forma basis, including $25 billion of net debt, giving effect to Qualcomm’s pending acquisition of NXP on its currently disclosed terms.

“Broadcom’s proposal is compelling for stockholders and stakeholders in both companies. Our proposal provides Qualcomm stockholders with a substantial and immediate premium in cash for their shares, as well as the opportunity to participate in the upside potential of the combined company,” said Hock Tan, President and Chief Executive Officer of Broadcom. “This complementary transaction will position the combined company as a global communications leader with an impressive portfolio of technologies and products. We would not make this offer if we were not confident that our common global customers would embrace the proposed combination. With greater scale and broader product diversification, the combined company will be positioned to deliver more advanced semiconductor solutions for our global customers and drive enhanced stockholder value.”

Tan continued, “We have great respect for the company founded 32 years ago by Irwin Jacobs, Andrew Viterbi and their colleagues, and the revolutionary technologies they developed. Following the combination, Qualcomm will be best positioned to build on its legacy of innovation and invention. Given the common strengths of our businesses and our shared heritage of, and continued focus on, technology innovation, we are confident we can quickly realize the benefits of this compelling transaction for all stakeholders. Importantly, we believe that Qualcommand Broadcom employees will benefit from substantial opportunities for growth and development as part of a larger company.”

Thomas Krause, Broadcom Chief Financial Officer, added, “The Broadcom business continues to perform very well. Broadcom has completed five major acquisitions since 2013, and has a proven track record of rapidly deleveraging and successfully integrating companies to create value for our stockholders, employees and customers. Given the complementary nature of our products, we are confident that any regulatory requirements necessary to complete a combination with Qualcomm will be met in a timely manner. We look forward to engaging immediately in discussions with Qualcomm so that we can sign a definitive agreement and complete this transaction expeditiously.”

“The combined Qualcomm/Broadcom operation would represent the third largest global semiconductor supplier. The Qualcomm shareholders are likely to be split with many viewing this opportunity as a solution to the worsening relations with Apple, whom Broadcom has a good relationship with. The potential merger raises significant questions surrounding the difficult takeover of NXP by Qualcomm and much is still to be discerned regarding the value of the Qualcomm patent holdings and its associated lucrative high-margin revenue stream,” said Stuart Carlaw, Chief Research Officer at ABI Research.

Costs of 55-inch OLED TV display production catch up to LCD TV panels

November 3, 2017

A major decrease in manufacturing cost gap between organic light-emitting diode (OLED) display and liquid crystal display (LCD) panel is expected to support the expansion of OLED TVs, according to new analysis from IHS Markit (Nasdaq: INFO).

The OLED Display Cost Model analysis estimates that the total manufacturing cost of a 55-inch OLED ultra-high definition (UHD) TV panel — at the larger end for OLED TVs — stood at $582 per unit in the second quarter of 2017, a 55 percent drop from when it was first introduced in the first quarter of 2015. The cost is expected to decline further to $242 by the first quarter of 2021, IHS Markit said.

The manufacturing cost of a 55-inch OLED UHD TV panel has narrowed to 2.5 times that of an LCD TV panel with the same specifications, compared to 4.3 times back in the first quarter of 2015.

“Historically, a new technology takes off when the cost gap between a dominant technology and a new technology gets narrower,” said Jimmy Kim, principal analyst for display materials at IHS Markit. “The narrower gap in the manufacturing cost between the OLED and LCD panel will help the expansion of OLED TVs.”

However, it is not just the material that determines the cost gap. In fact, when the 55-inch UHD OLED TV panel costs were 2.5 times more than LCD TV panel, the gap in the material costs was just 1.7 times. Factors other than direct material costs, such as production yield, utilization rate, depreciation expenses and substrate size, do actually matter, IHS Markit said.

The total manufacturing cost difference will be reduced to 1.8 times from the current 2.5 times, when the yield is increased to a level similar to that of LCD panels. “However, due to the depreciation cost of OLED, there are limitations in cost reduction from just improving yield,” Kim said. “When the depreciation is completed, a 31 percent reduction in cost can be expected from now.”

Dialog Semiconductor announces completion of its acquisition of Silego Technology

November 2, 2017

Dialog Semiconductor plc (XETRA:DLG), a provider of highly integrated power management, AC/DC power conversion, charging, and low power connectivity technology, announced today that it has completed the acquisition of privately-held Silego Technology Inc. (“Silego”), a provider of Configurable Mixed-signal ICs (CMICs).

Headquartered in Santa Clara, California with approximately 235 employees worldwide, Silego is the pioneer and market leader in CMICs that integrate multiple analog, logic, and discrete component functionality into a single chip. Silego’s product portfolio will strengthen Dialog’s presence in markets including IoT, computing and automotive.

“The acquisition of Silego brings a highly complementary technology to Dialog. What Silego has developed is truly unique – a mixed-signal platform which customers can configure to their design requirements on the fly, drastically reducing the time to bring their products to market,” said Jalal Bagherli, CEO of Dialog. “With global scale and customer access, Dialog is the right platform to further accelerate industry wide CMIC adoption. Furthermore, we gain an exceptional group of talented people that will fit well with Dialog’s culture. Together, we will significantly increase the value we can bring to our customers by creating a better-positioned and more-diversified mixed signal offering.”

“We believe Dialog will be a great environment for the Silego team to grow as part of a much larger company serving global customers,” stated John Teegen, CEO of Silego Technology. “Our proprietary and configurable approach has allowed Silego to establish leadership while creating a new market. By leveraging Dialog’s technology and capabilities, I am confident we can further drive adoption of CMICs.”

Silego anticipates achieving over $80 million of revenue in 2017 and double-digit growth in 2018. The transaction is expected to be accretive to Dialog’s underlying EPS for full calendar year 2018 and accretive to Dialog’s gross margin.

Global semiconductor industry posts highest-ever quarterly sales

November 1, 2017

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $107.9 billion for the third quarter of 2017, marking the industry’s highest-ever quarterly sales and an increase of 10.2 percent compared to the previous quarter. Sales for the month of September 2017 were $36.0 billion, an increase of 22.2 percent over the September 2016 total of $29.4 billion and 2.8 percent more than the previous month’s total of $35.0 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales increased sharply year-to-year in September, and year-to-date sales through September are more than 20 percent higher than at the same point last year,” said John Neuffer, SIA president and CEO. “The industry posted its highest-ever quarterly sales in Q3, and the global market is poised to reach its highest-ever annual revenue in 2017.”

Regionally, year-to-year and month-to-month sales increased in September across all markets: the Americas (40.7 percent year-to-year/5.9 percent month-to-month), China (19.9 percent/2.5 percent), Europe (19.0 percent/1.8 percent), Asia Pacific/All Other (16.8 percent/1.9 percent), and Japan (11.9 percent/0.5 percent).

“The Americas market continued to stand out, notching its largest year-to-year sales increase in more than seven years,” Neuffer said. “Standouts among semiconductor product categories included memory products like DRAM and NAND flash, both of which posted major year-to-year growth in September, as well as Logic products, which enjoyed double-digit growth year-to-year.”