Tag Archives: letter-pulse-top

Power transistor growth returns after volatile period

September 27, 2017

Since the 2009 semiconductor downturn and strong 2010 recovery year, power transistor sales have been rocked by market volatility, falling in three of the last five years because of inventory corrections and drawdowns by systems makers worried about ongoing economic weakness and price erosion in some product categories. After recovering from a 7% drop in 2015, power transistor sales grew 5% in 2016 to $12.9 billion and are forecast to set a new record high this year with worldwide revenues rising 6% to $13.6 billion, according to IC Insights’ 2017 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discrete Semiconductors.

The expected 2017 growth in power transistor sales will be the first back-to-back annual increase in this semiconductor market segment in six years, and that will push dollar volumes past the current record high of $13.5 billion set in 2011. In 2012 and 2013, power transistors suffered their first back-to-back annual sales decline in more than three decades—dropping 8% and 6%, respectively—after rising 12% in 2011 and surging 44% in the 2010 recovery from the 2009 downturn year. The power transistor market then rebounded in 2014 with a strong 14% increase, only to drop 7% in 2015. In 2016, this semiconductor discretes market category began to stabilize and is expected to continue expanding at a modest rate in the next several years, based on IC Insights’ O-S-D Report forecast (Figure 1).

Power transistors are the primary growth engine in the $23 billion discrete semiconductor market because they play a vital role in controlling and conditioning electricity for all types of electronics—including a growing number of battery-operated systems. Worldwide efforts to reduce the waste of power in electric utility grids have significantly increased the importance of power transistors in consumer, commercial, and industrial systems. Renewable-energy applications (e.g., wind and solar systems) as well as electric and hybrid vehicles have also become important applications for power transistors in the last 15 years.

Figure 1

However, volatility in the first half of this decade resulted in an uncharacteristic drop in market size for power transistors during the last five years. Between 2011 and 2016, power transistor sales fell by a compound annual growth rate of -0.9% compared to a 25-year historical annual average increase of 6.4% (between 1991 and 2016). The 2017 O-S-D Report is projecting that worldwide power transistor sales will grow by a CAGR of 4.2% between 2016 and 2021, reaching $15.8 billion in the final year of the forecast.

All power transistor technology categories are expected to register sales growth in 2017 with MOS field effect transistor (FET) products increasing 6% to nearly $7.7 billion, insulated-gate bipolar transistor (IGBT) products also rising 6% to $4.1 billion, and bipolar junction transistor products growing 4% to about $875 million. RF/microwave power transistors and module sales are forecast to rise 3% in 2017 to $960 million, according to the O-S-D Report.

Itâs gonna be a bright, bright sun-shiny day

September 26, 2017

BY ARABINDA DAS and JUN LU, TechInsights, Ottawa, ON

Last year was a great year for photovoltaic (PV) technology. According to Renewable Energy World magazine, since April 2016, 21 MW of solar PV mini-grids were announced in emerging markets [1]. The exact numbers of installed solar grids for 2016 has not been published yet but looking at the data for 2015, the PV industry is growing, helped by the $/watt for solar panels continuing to drop. The $/watt is obtained by taking the ratio of total cost of manufacturing and the number of watts generated. According to the Photovoltaic Magazine, the PV market continued to grow worldwide in 2015. The magazine also makes reference to the newly published report by the International Energy Agency Photovoltaic Power System (IEA PVPS) programme’s “Snapshot of Global Photovoltaic Markets 2015,” which also states that the total capacity around the globe has crossed the 200 GW benchmark and is continuing to grow [2]. This milestone of 200 GW in installed systems is a remarkable achievement and makes us think of the amazing journey of PV technology. The technology was born in Bell Labs, around 1954, with a solar cell efficiency of just 4% [3]. By the end of the 20th century, the overall solar cell efficiency was close to 11% and the worldwide installed capacity of PV was only 1 GW [3]. Today, seventeen years later, it has soared to 200 GW, with single junction cells having efficiencies around 20% [2].

Si-based solar cells

To celebrate this important milestone, we put TechInsights’ analysis and technical databases to work to investigate the structure of solar cells of two leading manufacturers and compare them to earlier technologies. We chose to analyze Si-based solar cells only, as they represent over 85% of the global market. According to the 2016 IHS Markit report, the top three PV module suppliers in the world are Trina Solar, SunPower, and First Solar [4]. We procured panels from Trina Solar, a Chinese based company, and SunPower, an American company, and carried out a structural analysis of these panels. These analyses helped us take a snapshot of current PV technology. We compared these two types of panels with an older panel from our database. This panel is about eight years old and was made by Kaneka (Japan). We will provide an overview of each panel and their underlying structure.

Table 1 consolidates some of the important param- eters of the three panels. The SunPower panel is based on monocrystalline silicon and the Trina solar panels are based on polycrystalline silicon. The older Kaneka panel is based on amorphous Si thin film technology. The panel from Kaneka is an earlier product; their recent products are made using hybrid technology, a combination of amorphous films and polycrystalline substrates, The Kaneka panel complements very well the other two products which are based on Si crystalline wafers. The technology to fabricate the solar cells (thin film, multi-crystalline or mono-crystalline) has a direct impact on the efficiency of the cells and on their electrical parameters like the open circuit voltage (Voc) and the short circuit current (Isc), as can be seen in Table 1. This table also shows that the Kaneka thin-film based panel has the lowest nominal power among the three. The ratio of nominal power to the light power that is received by the PV panel is indicative of its efficiency. It can be seen also that Kaneka’s thin film panel has the highest open circuit voltage which is the maximum voltage available from the solar cell without any load connected to it.

Table 1 indicates that SunPower is the only one among the three that uses an n-type substrate and has the highest solar efficiency. SunPower has the lowest weight per meter-square of all the panels assessed (9.3kg).

Unlike SunPower panels, most installed Si solar panels employ a p-type substrate, even though the first silicon-based solar cells developed at Bell Labs were based on n-type Si substrates [3]. Researchers J. Libal and R. Kopecek posit that the industry transitioned to p-type substrates because the initial usage of solar cells was in space applications and p-type wafers demonstrated less degradation in the presence of cosmic rays. They suggest that for terrestrial applications there is growing evidence that n-type based solar panels are preferred over p-type based panels [5]. The reasons for choosing n-type Si substrates rather than p-type substrates are because the former are less sensitive to metallic impurities and thus are less expensive to fabricate. In general, the minority carrier diffusion lengths in n-type substrates are higher than p-type Si substrates. Also, n-type Si substrates can withstand higher processing temperatures than p-type substrates, which are prone to boron diffusion. According to the International Technology Roadmap for Photovoltaic (ITRPV), n-type based substrates will increase in prevalence and may eventually replace the p-type monocrystalline Si cells [6].

Thin film based solar panels are very different from monocrystalline Si cells. Thin film cells have the lowest efficiency and yet they too have a role to play in the PV industry. They are the most versatile; they can be coated on different substrates such as glass, plastic or even flexible substrates. The other big advantage of amorphous solar films is that they can be manufac- tured in a range of shapes, even non-polygonal shapes, thus they can be used in various applications. Also, thin film solar panels are not affected by high temper- atures, unlike crystalline solar panels. Thin film based panels made from amorphous Si are more effective for wavelengths between 400 nm to 700 nm, which is also the sensitive spectrum of the human eye; thus they can be used as light sensors [7]. Usually, thin film panels are almost half the price of monocrystalline panels. Amorphous silicon solar cells only require 1% of the silicon used in crystalline silicon solar cells [7].

Multi-crystalline (MC) solar panels are also cheaper than monocrystalline solar panels. MC panels are made by melting raw silicon and confining them into square molds, where they are cooled. This MC-Si process does not require the expensive Czochralski process. In the early days, the cost of fabrication of MC-Si panels was higher than thin film based panels. Now, due to the major advances in fabrication technologies, these panels often have the best $/ watt, which represent the ratio of cost to manufacture to energy output [8]. It is difficult to compare $/watt directly from different manufacturers and different types of solar panels as the technology is manufacturing is changing rapidly and often the most recent products of a manufacturer are not compared. A more sensible factor of comparison would be the ratio of total kilowatt-hours the system generates in its lifetime divided by the cost per square unit of the panel. To make a detailed estimation even the installation cost and tolerance to shade, overall reliability must be included in the calculations, which is beyond the scope of this article.

Solar panel overview

FIGURE 1 shows the panel from Kaneka. It indicates that the Kaneka solar panel cells are long strips that run across the whole length of the panel. The color of the panels is a shade of purple. The Kaneka Solar which is amorphous Si-based, has a very uniform color. The inherent structure of amorphous Si-films has many structural defects because they are not crystalline and thus are tolerant to other defects like impurities during manufacturing, unlike crystalline based panels [7]. The color of the thin film panels is strongly thickness dependent because thickness affects the light absorption. A solar cell’s outward appearance can range from blue to black and is dependent on the absorption and reflectivity of their surface. Ideally, if the cell absorbs all the light impinging on the surface it should be black. FIGURE 2 shows the panels from Trina solar and Sunpower. The Trina Solar panel has a blueish color and each cell is perfectly square. The SunPower SPR-X20- 250-BLK solar cell has a uniform blackish color. The spacing between the cells, the interconnect resis- tance, the top contacts and the materials used for the connections affect the overall performance of the panel. All three manufacturers connect their cells within a PV module and PV modules within an array in a series configuration.

Table 2 summarizes the cell dimensions for the three manufacturers. Kaneka panels have the narrowest space (0.55mm) between the cells. The Trina solar panel has a 3 mm wide gap and a 5 mm gap, between two adjacent solar cells, in the horizontal and vertical direction respectively. These gaps are used for bus electrodes. In the SunPower solar panel, the metal grid is placed on the back surface eliminating metal finger width as a layout constraint. This design significantly reduces the finger resistance and improves the series resistance.

For all panels, interconnects are made between the cells. The metallization and interconnects between the cells is a field of technology on its own. There are various techniques like lithography, laser grooving and printed contacts and these details are discussed more in detail elsewhere [9, 10, 11].

Solar panel cross-sections

In this section, we look into the layers deposited on the substrates. Cross-sectioning these big panels is not a trivial feat. These panels are covered with tempered glass and shatter during sawing and cross-sectioning. To extract a small rectangular piece requires patience and involves sawing and grinding processes. In most cases, the glass was removed before doing the cross-section. FIGURE 3 illustrates two SEM cross-sectional images and one schematic drawing. The SEM cross-sectional images show the top and bottom part of the Kaneka solar cell. In figure 3(a), the active layers comprise indium- tin- oxide, an amorphous silicon layer capped with zinc oxide, silver and a very thin layer of Ni-Al. On top of the Ni-Al film, solder is deposited. Ni-Al provides better adhesion to solder. Two electrical contacts are made between the cells, one to the indium-tin-oxide for the back contact and the other to the Ni-Al layer. Figure 3(b) exposes the layers under the glass substrate. The rear surface of the glass substrate is covered by a soft material such as EVA (ethyl-vinyl-acetate), which in turn is covered by a rear Polyvinyl Fluoride (PVF) layer called the backsheet (Tedlar or similar). EVA is also used on the top surface (figure 3(a)). The usage of these layers is standard practice in the PV industry. The main function of these layers is that they are impervious to moisture and are stable under prolonged exposure to sunlight. On the front side, EVA also helps to reduce reflection and provides good adhesion between the top glass and the solar panels. Figure 3(c) shows the complete stack in the Kaneka solar cell.

FIGURE 4 presents the stack of materials on the multi- crystalline substrate of the Trina Solar panel. The substrate is p-type and has a very thin phosphorous doped region near the top surface. This n-doped region forms the PN junction. A silicon nitride anti-reflective coating layer is deposited on top of the substrate and in designated areas the passivation is opened and silver is deposited to make electrical contact to the n-doped regions. At the bottom of the multi-crystalline substrate, there is also a thin region of high p-doping concentration and this forms the back surface field layer. This solar cell module is fabricated using passivated emitter and full metal back-surface-field (BSF) technology. BSF technology is implemented to mitigate rear surface recombination and this is done by doping heavily at the rear surface of the substrate. This high doping concentration keeps minority carriers (electrons) away from the rear contact because the interface between the high and low doped areas of same conductivity acts like a diode and restricts the flow of the minority carriers to the rear surface. Passivated emitters in the front side and BSF layer on the rear side improve the efficiency of the cells. Figure 3(b) is the schematic repre- sentation of the cell without the EVA and PVF layers.

FIGURE 5 shows an optical cross-section of the SunPower cell. Figure 5(a) shows that SunPower employs a backside junction technology with interdigitated backside p-emitter and n-base metal. This means that both the contact’s n and p-electrodes are at the bottom of the substrate and are placed in in an alternating manner. Having all the metal contacts on the rear side has two big advantages:

1. Metallic contacts are reflective and occupy space that can be used to collect more sunlight; transferring these contacts to the rear side improves the cell efficiency and also leaves the front surface with a uniformly black color, which is more aesthetic for the home users.

2. It reduces bulk recombination. The mono-crystalline substrate is only 120 μm thick. It is designed so that the carrier is generated close to the junction. The substrate is n-type and p-electrodes are formed by localized doping on the bottom part of the substrate.

Figure 5(b) illustrates the general structure of the cell.

FIGURE 6 depicts a SEM cross-section of the metal fingers that connect to the interdigitated electrodes. The pitch between the metal fingers is 920 um and repeats over the entire back surface of the panel.

All three manufacturers employ some sort of surface texturing along with anti-reflective coatings to reduce reflection but SunPower uses the most advanced technology for surface texturing. FIGURE 7 illustrates a SEM topographical image of the front surface texture of the monocrystalline substrate having pyramids, which are etched into the silicon surface. These faceted surfaces increase the probability of reflected light entering back to the surface of the substrate. A similar concept is also applied to the back surface.

The future is sunny and bright

Of the three panels we analyzed, SunPower solar panels employ the most advanced technologies and they illustrate how the solar cell has evolved over the ages. It started from a simple PN junction, then passivated emitters were intro- duced along with local back-surface-field (BSF) technology, which came to be known as Passivated-Emitter with Rear Locally (PERL) diffused technology. In contrast, today the most advanced technology is interdigitated back contacts along with passivated contacts.

In addition to these advances, there is great progress in tandem cells and multi-junctions to capture the different wavelength regions of the sun’s rays. A recent article in IEEE spectrum magazine presented the state of art of record-breaking PV cells made with different techniques such as thin film, crystalline Si, single junction, multi-junction cells. PV cells especially the multi-junction cells, have now crossed the 50% efficiency barrier [12]. Similarly, a publication from the alterenergy.org has collected all the major advances made in PV technology and discusses concepts like colloidal quantum dots and GaAs for cell technology, along with new applications [13]. Today, we regularly read about new materials (like perovskites) and come across new techniques that improve solar panel efficiencies, including new manufacturing methods to reduce the overall cost of fabrication. Moreover, PV cells are used in an innovative manner. The installation of PV panels is no more restricted to isolated rooftops or solar farm. An article in the Guardian made a reference to a solar panel road in Normandy, France [14]. At TechInsights, we will continue to keep an eye on emerging solar cell technologies.

The efforts emerging from various organizations all over the world are very encouraging. There are indeed many challenges for renewable energy to overcome before fiscal parity with fossil fuels is achieved; particularly for PV energy. Nevertheless, there is an increased focus on climate change issues. This has resulted in a significant amount of resources being allotted to PV technology in many countries, especially in developing countries such as China, India, and Brazil [1, 2]. This optimistic scenario reminds us of the song “I Can See Clearly Now” by the 1970s American singer Johnny Nash, where the refrain runs optimistically, “It’s gonna be a bright, bright sun-shiny day.”

References

1. http://www.renewableenergyworld.com/articles/2017/01/21-mw- of-solar-pv-for-emerging-market-community-mini-grids-announced- since-april.html;
2. http://www.pv-magazine.com/news/details/beitrag/iea-pvps— installed-pv-capacity-at-227-gw-worldwide_100024068/#ixzz4MB1 a44hq
3. The history of solar: https://www1.eere.energy.gov/solar/pdfs/solar_ timeline.pdf
4. http://news.ihsmarkit.com/press-release/technology/ihs-markit- names-trina-solar-sunpower-first-solar-hanwha-q-cells-and-jinko-
5. www.pv-tech.org/guest…/n_type_silicon_solar_cell_technology_ ready_for_take_off
6. http://www.itrpv.net/; http://www.itrpv.net/Reports/Downloads/2016/ 7. http://www.solar-facts-and-advice.com/amorphous-silicon.html
8. http://energyinformative.org/solar-cell-comparison-chart-mono-
polycrystalline-thin-film/
9. RP_0706-14839-O-4CS-11Kaneka
10. RP_0616-41931-O-5SA-100_Trina
11. RP_0716-42662-O-5SA-100_SunPower
12. http://spectrum.ieee.org/green-tech/solar/what-makes-a-good-pv-
technology
13. http://www.altenergy.org/renewables/solar/latest-solar-technology.
html
14. https://www.theguardian.com/environment/2016/dec/22/solar-panel-
road-tourouvre-au-perche-normandy

Advancements in spintronics

September 25, 2017

BY HIDEO OHNO, MARK STILES, and BERNARD DIENY, IEEE

Spintronics is the concept of using the spin degree of freedom to control electrical current to expand the capabilities of electronic devices. Over the last 10 years’ considerable progress has been made. This progress has led to technologies ranging from some that are already commercially valuable, through promising ones currently in development, to very speculative possibilities.

Today, the most commercially important class of devices consists of magnetic sensors, which play a major role in a wide variety of applications, a particularly prominent example of which is magnetic recording. Nonvolatile memories called magnetic random access memories (MRAMs) based on magnetic tunnel junctions (MTJs), are commercial products and may develop into additional high impact applications either as standalone memories to replace other random access memories or embedded in complementary metal–oxide–semiconductor (CMOS) logic.

Some technologies have appealing capabilities that may improve sensors and magnetic memories or develop into other devices. These technologies include three- terminal devices based on different aspects of spin-transfer torques, spin-torque nano-oscillators, devices controlled by electric fields rather than currents, and devices based on magnetic skyrmions. Even further in the future are Spintronics-based applications in energy harvesting, bioinspired computing, and quantum technologies.

But before we get into detail about where Spintronics is today, we need to cover the history of Spintronics.

The history of spintronics

Spintronics dates to the 1960s and was discovered by a group at IBM headed by Leo Esaki, a Japanese physicist who would later go on to win a share of the Nobel Prize I 1973 for discovering the phenomenon of electronic tunneling. Esaki and his team conducted a study which showed an antiferromagnetic barrier of EuSe sandwiched between metal electrodes exhibits a large magnetoresistance.

Subsequent advances of semiconductor thin film deposition techniques such as molecular beam epitaxy led to the development of semiconductor quantum structures, which prompted studies of magnetic multilayers. Ensuing studies of magnetic multilayers resulted in the discovery of giant magne- toresistance (GMR) in 1988. This effect was used to make magnetic sensors, which boosted the areal density of information stored on hard disk drives and led to the 2007 Nobel Prize in Physics awarded to Albert Fert and Peter Grunberg.

Since then rapid progress has continued to enhance both the role and the potential of Spintronics. So, let’s take a look at where we are now.

Where we are now

Applications now include nanoscale Spintronics sensors that further enhance the areal density of hard disk drives, through MRAMs that are seriously being considered to replace embedded flash, static random access memories (SRAM) and at a later stage dynamic random access memories (DRAM). Applica- tions also include devices that utilize spin current and the resulting torque to make oscillators and to transmit information without current.

Now let’s look at those applications and more in-depth.

Modern Hard Disk Drives: Two breeds of Spintronics sensors have replaced traditional anisotropic magnetoresistance (AMR) sensors. Those sensors include giant magnetoresistance (GMR) sensors (used in hard disk drives between 1998 and 2004) and tunnel magnetoresistance (TMR) sensors (used since 2004).

Those sensors are part of the technology development that enabled the increase of storage density of hard disk drives by several orders of magnitude, laying the foundation of today’s information age in the form of data centers installed by the cloud computing industry.

Magnetoresistive Random Access Memory (MRAM): MRAM and particularly spin-transfer- torque MRAM (STT-MRAM) is a nonvolatile memory with very high endurance and scalability. The current STT-MRAM technology uses an array of MTJs with an easy axis of magnetization oriented out of the plane of the layers. These MTJs utilize interface perpendicular anisotropy at the CoFeB–MgO interface, along with the large TMR of the system, for reading the state of magnetization. The spin-transfer torque exerted by a spin polarized current is used to change the magneti- zation direction, offering an efficient way of rewriting the memory. FIGURE 1 show the main families of MRAM that have evolved since 1995.

Three Terminal Magnetic Memory Devices: Recent physics developments raise the prospect of three- terminal spintronic memory devices. These devices have an advantage over the standard two-terminal devices used in memory applications such as MRAM in that separating the read and write functions poten- tially overcomes several future roadblocks in the devel- opment of MRAM. There are two writing schemes: one is based on spin currents generated by an electrical current running through a heavy metal adjacent to the free layer of the MTJ. The current causes a spin current both in the bulk of the heavy metal and at the interface; this spin current then exerts a torque, called the spin-orbit torque, on the magnetization. In this scheme, the write current does not pass through the MTJ, separating the write and read functions. The other scheme uses current-induced domain wall motion to move a domain wall in the free layer of the MTJ from one side of the fixed layer to the other. In this scheme, the current passes through the free layer, but not the tunnel barrier, again separating the read and write functions.

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing: Spintronic-based nonvolatile embedded working memory used in conjunction with CMOS-based logic applications is a crucial first step toward standby-power-free logic circuits that are much needed for Internet of Things (IoT) applications. MRAM based logic-in-memory reduces the overhead of having memory and logic apart and gives both minimized interconnection delay and nonvolatility.

Security: These devices have shown great promise for logic and memory applications due to their energy efficiency, very high write endurance, and nonvolatility. Besides, these systems gather
many entropy sources which can be advantageously used for hardware security. The spatial and temporal randomness in the magnetic system associated with complex micromagnetic configurations, the nonlinearity of magnetization dynamics, cell-to-cell process variations, or thermally induced fluctuations of magnetization can be employed to realize novel hardware security primitives such as physical unclonable functions, encryption engines, and true random number generators.

Spin-Torque and Spin-Hall Nano-Oscillators: Spin-torque nano-oscillators (STNO) and spin-Hall effect nano-oscillators (SHNO) are in a class of miniaturized and ultra-broadband microwave signal generators that are based on magnetic resonances in single or coupled magnetic thin films. These oscil- lators are based on magnetic resonances in single or combined magnetic thin films where magnetic torques are used to both excite the resonances and subsequently tune them. The torques can be either spin-transfer torques due to spin-polarized currents (STNOs) or spin Hall torques due to pure spin currents (SHNOs). These devices are auto-oscillators and so do not require any active feedback circuitry with a positive gain for their operation. The auto-oscillatory state is strongly nonlinear, causing phase– amplitude coupling, which governs a wide range of properties, including frequency tunability, modulation, injection locking, mutual synchronization, but also causes significant phase noise. STNOs and SHNOs can, in principle, operate at any frequency supported by a magnetic mode, resulting in a potential frequency range of over six orders of magnitude, from below 100 MHz for magnetic vortex gyration modes to beyond 1 THz for exchange dominated modes. Since STNOs and SHNOs can also act as tunable detectors over this frequency range, there is significant potential for novel devices and applications.

Beyond the applications listed, the spin degree of freedom is also being used to convert heat to energy through the spin Seebeck effect, to manipulate quantum states in solids for information processing and communication, and to realize biologically inspired computing. These may lead to new develop- ments in information storage, computing, communication, energy harvesting, and highly sensitive sensors. Let’s take a look at these new developments.

Thermoelectric Generation Based on Spin Seebeck Effects: The study of combined heat and spin flow, called spin caloritronics, may be used to develop more efficient thermoelectric conversion. Much of the focus of research in spin caloritronics has been the longitudinal spin Seebeck effect, which refers to spin-current generation by temperature gradients across junctions between metallic layers and magnetic layers. The generated spin current in the metallic layer gets converted into a charge current by the inverse spin Hall effect, making a two-step conversion process from a thermal gradient perpen- dicular to the interface into a charge current in the plane of the interface. This process can be used for thermoelectric conversion. Device structures using the spin Seebeck effect differ significantly from those using conventional Seebeck effects due to the orthog- onality of the thermal gradient and resulting charge current, giving different strategies for applications of the two effects.

Electric-Field Control of Spin-Orbit Interaction for Low-Power Spintronics: Control of magnetic properties through electric fields rather than currents raises the possibility of low energy magnetization reversal, which is needed for low-power electronics and Spintronics. One specific way to accomplish this low energy switching is through electric-field control of electronic states leading to modification of the magnetic anisotropy. By applying a voltage to a device, it is possible to change the anisotropy such that the magnetization rotates into a new direction. While such demonstrations of switching alone are not sufficient to make a viable device, voltage controlled reversal is a promising pathway toward low-energy nonvolatile memory devices.

Control of Spin Defects in Wide-Bandgap Semiconductors for Quantum Technologies: The spins in deep level defects found in diamond (nitrogen- vacancy center) and in silicon carbide (divacancy) have a quantum nature that manifests itself even at room temperature. These can be used as extremely sensitive nanoscale temperature, magnetic-field, and electric-field sensors. In the future, microwave, photonic, electrical, and mechanical control of these spins may lead to quantum networks and quantum transducers.

Spintronic Nanodevices for Bioinspired Computing: Bioinspired computing devices promises low-power, high-performance computing but will likely depend on devices beyond CMOS. Low-power, high performance bioinspired hardware relies on ultrahigh- density networks built out of complex processing units interlinked by tunable connections (synapses). There are several ways in which spin-torque-driven MTJs, with their multiple, tunable functionalities and CMOS compatibility, are very well adapted for this purpose. Some groups have recently proposed a variety of bioin- spired architectures that include one or several types of spin-torque nanodevices.

Skyrmion-Electronics: An Overview and Outlook: The concept of skyrmions derives from high energy physics. In magnetic systems, skyrmions are magnetic textures that can be viewed as topological objects. Theory suggests that they have properties that might make them useful objects in which to store and manip- ulate information. Many of the ideas are similar to ideas that were developed decades ago for bubble memory or, more recently, racetrack memory. There are several possible advantages for skyrmion devices as compared to other related devices. They are potentially higher density and lower energy, although the arguments for these remain to be experimentally verified.

So, what does the future of spintronics have in store?

The future

Spintronics will continue to have increasing impact, but the future is somewhat uncertain. The importance of magnetic sensors is likely to remain important while the importance of the magnetic sensors in hard disk drives appears to depend on the economics of mass storage in the cloud.

MRAM seems likely to play an increasing role both as standalone memory and embedded in CMOS. The degree of adoption still depends on a few technical and many economic considerations. The acceleration, over the past few months, of announcements and demonstrations related to STT-MRAM produced by major microelectronics companies, seems to indicate that large volume production of STT-MRAM is getting quite close. If the adoption of this technology by microelectronics industry becomes a reality, the whole field will be strongly boosted.

In the future, Spintronics can play a critical role in areas such as IoT, ultralow-power electronics, high-performance computing (HPC). Besides, in the next 10 to 15 years, we are likely to see a much greater role played by alternative forms of computing. The role that Spintronics plays in those technologies is likely to be strongly influenced by the success of MRAM. If MRAM is successful, we will have developed the ability to manufacture it making it easier to import into other technologies.

Some of the recent technical developments that have significant virtues for applications will likely play a role in technology 10 to 15 years from now but many will not. Research on many of these ideas will continue and will spawn related areas. Material research is key along this road.

Innovative materials allowing efficient charge to spin and spin to charge current conversion, or good control of magnetic properties by voltage, or efficient injection/manipulation/detection of spins in semicon- ductors can play major roles. Along with this idea, the use of oxide materials in spintronic devices can become quite important. Oxides share crystal- linity with semiconductors in distinction to metallic magnetic devices. Will the greater control that comes with crystallinity give advantages to oxides in future devices? These are some of the many topics that are likely to be addressed in the coming years.

DSA and EUV: Complementary technologies to enable fine- pitch lithography

September 22, 2017

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography.

BY DOUGLAS J. GUERRERO, Ph.D., Brewer Science, Rolla, MO

Advances in lithography have always been critical in the drive toward each subsequent semiconductor node. Anticipating limitations in the scaling ability of immersion lithography, the industry has been pursuing next-generation lithography techniques. Several techniques have been proposed, including extreme ultraviolet (EUV) lithography, multibeam electron-beam lithography, nanoimprint lithography and directed self-assembly (DSA) of block copolymers.

DSA attracted a great deal of interest from major semiconductor manufacturers for several years, following its initial development in the early 2000s. However, it has since fallen out of favor to some extent, in part because of advances in EUV lithography as a result of focused investment in that technology. Recent developments in DSA materials and processing promise to overcome concerns that have delayed its implementation.

Choosing an appropriate lithography technique does not need to be an either-or proposition. The greatest opportunity may lie in leveraging both EUV lithography and DSA. Although these two technologies are sometimes seen as competing, it makes more sense to envision them as complementary. This article explains how lithography may benefit by taking advantage of both EUV and DSA, and why previously existing roadblocks may no longer pose obstacles.

The material defines the pattern

Unlike most lithography techniques, where the mask defines the pattern, in DSA the pattern exists in the material itself. The original block copolymers (BCPs) for DSA combine polystyrene (PS) and poly(methyl methacrylate) (PMMA), two polymers that naturally segregate themselves into separate phases. Adjusting the relative proportions of PS and PMMA in the PS-b-PMMA material changes the morphology from spherical to cylindrical to lamellar (FIGURE 1). The product of the Flory interaction parameter, χ, and the segment length determine the spacing of the ordered structure. The higher the value of χ, the finer the pitch of the resulting structure.

Standard PS-b-PMMA materials have relatively low χ, which limits the pitch to 20nm or larger. Some materials manufacturers are considering chemistries other than PS-b-PMMA to produce high-χ BCPs, replacing the PMMA component with polydimethylsiloxane or polyhydroxystyrene. Modifying PS-b-PMMA is another approach to increase χ. In this manner, it is possible to tune χ, the molecular weight and the glass transition temperature to achieve lamellar spacing between 14nm and 40nm under various annealing conditions.

The process flow for BCP deposition is straightforward. A neutral layer spin-coated onto the substrate allows for the BCP to separate into its individual domains during the thermal annealing process. The neutral layer allows for domain separation because it does not have affinity for either of the polymer chains in the BCP. Polymer domain separation is responsible for pattern formation.

Processing considerations

The DSA deposition process uses one of two basic approaches (FIGURES 2 and 3). Graphoepitaxy leverages topography to align the BCPs, depositing them into relatively deep trenches. Guide patterns define the trenches, confining the BCPs into configurations in which they align in a preferred direction. Chemical epitaxy, or chemoepitaxy, is based on a chemical pattern on a flat substrate, on top of which the BCPs self-align.

Click to enlarge.

The semiconductor industry is pursuing both graphoepitaxy and chemoepitaxy approaches, favoring the former for producing fine-pitch vias and the latter for creating arrays of parallel lines.

Annealing temperatures are in the range of 250°C to 275°C, making them compatible with standard semiconductor processing. The annealing step can be lengthy—up to two hours to create structures with sufficiently low defect rates—adding cost to the process.

PS-b-PMMA BCPs are being manufactured in high- volume quantities. Worldwide, 1.1 million tons of the material are currently in use for a variety of applica- tions. This quantity is greater than the needs of the entire semiconductor industry. Therefore, although no commercially produced DSA materials are currently targeted for semiconductor applications, the infra- structure is in place to scale up production of suitable materials when the industry is ready.

Why DSA is attractive now

DSA was added to the ITRS roadmap in 2007. Major semiconductor industry players originally believed DSA would enter commercial production anywhere between the 14nm and 7nm logic nodes, and even sooner for DRAM; but so far that has not come to pass. A survey at the 2016 DSA Symposium suggested that the technology is still not ready for the mainstream and won’t be for several years. But some IDMs would like to accelerate the process, and there are reasons to believe this is not only possible, but desirable.

Decreasing the wavelength to 193nm immersion lithography has enabled line width and spacing down to 80nm. Techniques such as self-aligned quadruple patterning (SAQP) can create even smaller features through multiple lithography/etch iterations, but at the expense of adding lithography steps, each requiring a custom mask.

Immersion lithography is reaching its limits, providing an opportunity for next-generation lithographic techniques. Designs with critical dimensions (CD) in the range of 10nm to 30nm create a sweet spot for these state-of-the-art techniques.

Advances in EUV lithography are one factor that has led the industry to favor it over DSA. Today’s EUV materials have greater sensitivity compared with older- generation products, therefore requiring lower UV doses; and line roughness has improved as well. EUV lithography can create vias with 30nm or 40nm spacing that are not feasible with immersion lithography.

DSA enables even finer resolution than the semicon- ductor industry currently demands. Feature sizes are just now approaching a level where DSA can be especially effective. If these trends continue, the technique is poised to be widely adopted before the end of this decade.

DSA and EUV: Better together?

The most effective solution may lie in leveraging EUV and DSA technologies to take advantage of the strengths of each. Both methods can achieve resolution levels that are compatible with the N7 and N5 logic nodes. EUV lithography is well-suited to patterning designs with multiple different pitches, down to line width and spacing around 30nm. For such fine pitches, however, the number of mask steps required may make the technique prohibitively expensive. Local CD uniformity (LCDU) can also be a concern, especially at high throughput rates.

The initial hard-mask lithography process is the same for both EUV and DSA, but they diverge during pattern processing. Once the BCPs are deposited, DSA can achieve 30nm feature size without requiring additional masks. Annealing naturally separates the two phases into the correct morphology. The DSA process, however, is best suited to designs with a single pitch.

EUV can be used to pattern lower-resolution features on a chip, plus create spacers for subsequent DSA deposition. This combination provides the greatest design flexibility while streamlining the fabrication process, eliminating processing steps and reducing mask costs. LCDU is also better than with EUV alone.

DSA is best suited for devices with multiple repeating, regular fine-pitch features. Therefore, it likely will first be implemented in DRAM storage, later migrating to use in via layers on logic devices. Graphoepitaxy, especially using EUV to deposit the spacers, can enable more complex designs using DSA, where different regions of the chip require different pitches. This will presumably be the approach of choice for logic chips.

Despite the promise that leveraging both DSA and EUV offers, the semiconductor industry will only migrate to this approach once suppliers can convince IDMs that the materials have overcome their technical limita- tions. DSA has suffered from several challenges that have delayed its adoption: Primary issues are defectivity, pattern placement accuracy, ease of integration into manufacturing flows, and cost. But there is reason to be optimistic, as advances in chemistry and processing methods are improving all these metrics.

Overcoming technical challenges

The 2016 DSA Symposium survey identified defec- tivity as the greatest technical challenge. Defectivity and cost are related, in that the lowest defect levels are seen with the longest annealing times. While annealing for as little as five minutes causes the two phases to separate, the resulting material contains far too many defects to be suitable for commercial use.

Wafers are typically annealed one at a time, which can make the cost of annealing prohibitive. However, recent research using batch annealing in a vertical furnace showed great promise for reducing cost. By annealing 150 wafers in parallel for 30 minutes, researchers were able to demonstrate sufficiently low defect levels at a cost lower than that of SAQP.

Using both DSA and EUV has the potential to alleviate the problem of pattern placement errors. For example, EUV lithography can create prepatterned holes for doublet vias. The two vias may merge during the EUV process but will then automatically separate during DSA. Without DSA, an additional lithography step may be required to avoid merged vias.

This approach of leveraging EUV and DSA for fine- pitch vias is most reliable when the via shape is optimized. Studies have shown that a peanut shape, rather than an elliptical one, is ideal for creating doublet vias with minimal risk for pattern placement errors, even at the challenging N5 node.

Collaborating to advance DSA adoption

The semiconductor industry has extensive experience with lithography, but DSA requires a shift in mindset. BCP materials are not something that the industry is used to, and revolutionary rather than evolutionary changes in materials and processes can face resistance. DSA needs to be demonstrated on real devices before it can achieve traction in the semiconductor market.

Collaborative efforts between semiconductor industry materials suppliers and chemical companies with deep experience in BCPs are one route to bridge this gap. One such collaboration is currently underway. Brewer Science has teamed up with Arkema, a company with two decades of experience producing BCPs, but little leverage with the semiconductor industry. The partnership, begun in 2015, has led to pilot production of DSA materials, paving the way for the technique to move out of the laboratory and into commercial semiconductor products.

DSA and EUV should be envisioned as complementary, not competing, techniques that will eventually become mainstream for fine-pitch lithography at the N7 node and beyond. Partnerships between materials and chemical companies are poised to enable this transition, unlike previous efforts by single organizations.

Laser marking meets diverse challenges in fab and packaging

September 22, 2017

The basics of laser marking are reviewed, as well as current and emerging laser technologies.

BY DIETRICH TÖNNIES, Ph.D. and DIRK MÜLLER, Ph.D., Coherent Inc., Santa Clara, CA

Laser marking is established at multiple points in semiconductor production and applications continue to diversify. There are several laser technologies servicing the application space. This article reviews the basics of laser marking and the current and emerging laser technologies they utilize. It is intended to give a clear sense of what applications parameters drive the choice of laser (speed, cost, resolution, etc.), and provide those developing a new application some guidance on how to select the optimum technology.

Laser marking basics

Laser marking usually entails inducing a visible color or texture change on a surface. Alternatively, although less commonly, marking sometimes involves producing a macroscopic change in surface relief (e.g.engraving). To understand what laser type is best for a specific marking application, it is useful to examine the different laser/ material interactions that are generated by commonly used laser types.

Most frequently, lasers produce high contrast marks through a thermal interaction with the work piece. That is, material is heated until it undergoes a chemical reaction (e.g. oxidation) or change of crystalline structure that produces the desired color or texture change. However, the particulars of this process vary significantly between different materials and laser types.

CO2 lasers have been employed extensively for PCB marking because they provide a fast method of producing high contrast features. However, they are rarely selected when marking at the die or package level. This is because the focused spot size scales with wavelength due to diffraction. CO2 lasers emit the longest infrared (IR) output of any marking laser. Additionally, IR penetrates far into many materials, which can cause a substantial thermal impact on surrounding structures. Consequently, CO2 laser marking is limited to producing relatively large features where a significant heat affected zone (HAZ) can be tolerated.

Fiber lasers, which offer high power output in the near IR, have emerged over the past few years as one of the most cost effective tools for high-speed marking. Furthermore, the internal construction of fiber lasers renders a compact footprint, facilitating their integration into marking and test handlers. Cost and space savings are further enhanced when the output of a single, high power fiber laser is split, feeding two scanner systems.

But fiber lasers have disadvantages, too. One reason for the low cost of many fiber lasers is that they are produced in high volumes with designs meant for general-purpose applications. For example, they usually produce a high quality beam with a Gaussian intensity profile. This is advantageous for many material processing applications, but not always for laser marking. In fact, a more uniform beam intensity distribution, called a flat-top profile, is sometimes more useful since it produces marks with a sharper, more abrupt edge (rather than a smooth transition from the marked to the unmarked region). Coherent recently introduced a new type of fiber (NuBEAM Flat-Top fiber technology) which enables efficient conversion of single-mode laser beams into flat-top beam profiles, specifically to address this issue.

Other quality criteria, such as high-purity linear polarization, and stability of pulse energy and pulse width, are difficult to achieve with low-cost fiber lasers. This limits their use in more stringent or sensitive marking applications. From a practical standpoint, most fiber lasers cannot be repaired in the field, but are replaced as a whole. This leads to longer equipment downtime and increased maintenance efforts as compared to traditional marking lasers based on diode-pumped, solid-state (DPSS) technology (specifically, DPSS is used here to refer to lasers with crystal resonators).

DPSS lasers also emit in the near infrared. Generally, these lasers are more expensive than a fiber laser of the same output power level. So, infrared DPSS lasers are most commonly used in applications having technical requirements that cannot be met by fiber lasers,such as high volume production of more advanced and expensive semiconductor devices.

One advantage of DPSS laser technology is that it can be configured to directly produce a multi-mode beam profile which is essentially flat-top. The Coherent ❘ Rofin PowerLine E Air 30-1064 IC is an example which has found extensive use in semiconductor marking, since it provides an efficient way to rapidly produce very high contrast marks.

Another useful feature of DPSS lasers, which produce pulsewidths in the nanosecond regime, is that their output is much more stable than that of fiber lasers. This makes it much easier to reliably frequency double or triple their infrared light within the laser head, giving a choice of output in the green or ultraviolet (UV). Output at these wavelengths provides two significant benefits. First, they offer additional options in matching the absorption of the material to the laser wavelength. Stronger absorption generally yields higher marking efficiency and reduced HAZ, since the laser light doesn’t penetrate as far into the material. The second benefit of shorter wavelengths is the ability to focus to smaller spot sizes (because of their lower diffraction) and produce smaller, finer marks.

However, frequency multiplied DPSS lasers are generally more costly and voluminous than either fiber lasers or infrared DPSS lasers with comparable output power. Lower power translates into reduced marking speed.

Therefore, green and UV DPSS lasers are typically employed when they offer a significant advantage due to the particular absorption characteristics of the material(s) being marked.

Another emerging and important class of marking lasers has pulsewidths in the sub-nanosecond range. Due to the nature of the laser/material interaction at short pulsewidths, these lasers tend to produce the smallest possible HAZ with excellent depth control.

There are just a few products currently on the market that exploit this property. One example is the PowerLine Pico 10 from Coherent ❘ Rofin which generates 0.5 ns laser pulses in either the near IR (8 W total power) or green (3 W total power), at pulse repetition rates between 300 kHz and 800 kHz. This combination of output characteristics makes it capable of high speed marking of a wide range of materials where mark penetration depth must neces- sarily be shallow because of low material thickness, or to minimize HAZ.

Laser marking today

Typically, the first consideration in choosing a laser for a specific application is matching the absorption characteristics of the material with the laser wavelength. Similarly, desired feature size is also driven by laser wavelength, as well as by the precision of the beam scanning system. Next, HAZ constraints usually determine the maximum pulsewidth which can be used (although this choice is again highly material dependent). To see how these parameters interact in practice, it’s useful to review some real world applications.

Epoxy-based molding compounds

The most commonly used molding compounds absorb very well in the near IR. Specifically, the near IR laser transforms the usually black molding compound into a gray/white powder, yielding high contrast marks. Plus, many IC packages have mold compound caps thick enough to easily tolerate a marking depth of 30 μm to 50 μm. As a result, many marking systems based on near IR lasers, both fiber and DPSS, are currently in use.

However, some semiconductor devices with small form factor have only thin mold compound caps to protect wire bonded silicon dies, and a marking depth of only 10 μm or less is required. Increasingly, green lasers are used for this type of shallow marking because of a stronger absorption at this wavelength by the epoxy matrix.

Ceramics

The process window when marking ceramics, such as used in packaging power semiconductors, high-brightness LEDs, RF devices, saw filters or MEMS sensors, is relatively narrow. Accurate focus and high pulse energy are critical to ensure reliable marking results, and ideally, the laser marker should have the capability to adjust the focus of the laser beam onto the ceramic surface in real time, in order to compensate for package height variations. Because of their more reliable interaction with ceramic materials, DPSS lasers based on Nd:YAG, which offer high pulse energies and relatively long pulses, are often still used for marking ceramic lids and substrates. Coherent ❘ Rofin has also developed a special fiber laser (the PowerLine F 20 Varia IC), which offers adjustable pulse widths up to 200 ns, specifically to improve process windows for marking applications of this type.

The ceramic substrates used with high-power LEDs often require tiny marks to identify individual devices. IR lasers are the preferred lasers for marking these ceramic substrates, providing their spot size is not too big for the layout to be marked. For very small marking features a green laser or UV laser is often required.

Organic substrates

IC substrates or interposers are marked during production with traceable data matrix codes. The thin green solder resist layer on top of the substrate has to carry the mark, and care has to be taken that the copper underneath the solder resist is not exposed. Moreover, data matrix codes can be quite small, with cell sizes of only 125 μm or even less. Since the spot size of the focused laser beam must thus be much smaller than the cell size, the final spot diameter must be significantly less than 100 μm.

Defective IC substrates often are identified by marking large features (e.g., a cross) into the solder resist layer. Although the part is defective, the properties of the mark are still important. This is because it has to be reliably recognized by subsequent processing tools, and also, because any delamination of the solder resist layer might cause problems during succeeding processes.

IC strips have gold pads along their periphery which are used to identify parts found to be defective after die attach and wire bonding. For defective parts, the gold pad is marked by converting its color from gold to black or to dark grey.

Ideally, it is desirable to have one laser marker that can accomplish all three of these marking applications tasks. The green DPSS laser has become the standard laser marker for these applications, with UV lasers occasionally employed for high-end substrates.

Semiconductors

The growing demand for flip-chip devices, wafer-level packaging and defective die identification drives the need for direct marking of silicon, GaAs, GaN/sapphire or other semiconductors. Silicon is partially trans- parent in the near IR, and lasers at this wavelength are used whenever deep marks into silicon are required, such as placing wafer IDs near the wafer edge. Near IR laser markers are also selected for marking molded fan-out wafer level packaging wafers.

However, for marking either flip-chips or the backside of wafers, green lasers are preferred because of the strong absorption of this wavelength in silicon. Wafer backside marking requires only very shallow marks and the shallow laser penetration avoids potential damage to the circuitry on the reverse side of the flip-chip or wafer. The need for shallow marking also minimizes the laser power requirement. For example, Coherent ❘ Rofin provides a 6 W green laser (the PowerLine E 12 SHG IC) that is well suited for wafer backside marking, and can also mark the wafer through the tape whenever the wafer is mounted on a film frame.

Metals

Near IR lasers are widely used for marking the metal lids used with microprocessors and other high power consumption ICs.

Leadframes, which are plated with tin, silver or gold, are marked either before or after plating. Since leadframes are used for cost sensitive devices, capital investment is critical, and economical fiber lasers are often chosen for this reason.

Laser marking tomorrow

As packages get thinner and smaller, they will require shallower, higher resolution marks. Sub-nanosecond lasers are the most promising method for producing these types of marks, and are compatible with a wide range of materials. The diverse capabilities of this technology are shown in Figure 5, which depicts marking results on four different materials using a sub-nanosecond laser (Coherent ❘ Rofin PowerLine Pico 10-532 IC).

The first image is a flexible IC substrate; very thin solder resist layers and metal coatings make it important that the laser does not cause delamination. Here, the circular gold pad has been converted to black without delamination. In the next image, an IC substrate has been given a white mark, again without delaminating the solder resist.

The third image shows very small characters (< 150 μm) marked on the backside of a silicon wafer containing hundred thousands of tiny discrete semiconductor devices. Producing marks of this resolution through the film would be difficult to accomplish with a nanosecond pulsewidth laser.

The final image is a copper leadframe coated with thin silver film. Here, the goal is to produce a shallow mark with high contrast without engraving the under- lying material, which has been accomplished with the sub-nanosecond laser.

Conclusion

Semiconductor fabrication and packaging represent challenging marking applications, often requiring small, fine marks produced without a significant effect on surrounding material. An overall trend towards smaller and thinner device geometries will drive increased use of higher precision laser tools, such as those utilizing green and UV nanosecond lasers, and even sub-nanosecond lasers, while cost-sensitive applications will continue to utilize inexpensive fiber lasers.

Leading-edge paves the way for pure-play foundry growth

September 20, 2017

IC Insights has just released its September Update to The McClean Report. This 32-page Update includes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends. Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.

In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).

Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year. In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion. Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.

TSMC is by far the technology leader among the major pure-play foundries. In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC. In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC). In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.

In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production. In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.

DARPA calls for Monolithic 3D â 3DSoC

September 19, 2017

By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

On Sept 13, DARPA come out with Electronic Resurgence Initiative (ERI) programs. Quoting: “with an eye toward the times we now live in, [Gordon Moore] laid out the technical directions to explore when the conditions under which scaling will be the primary means for advancement are no longer met. A trio of simultaneously-released ERI BAAs—this one among them—parallel the research areas detailed on page three of Moore’s paper: materials and integration, architecture, and design. These new page-three-inspired investments, along with a series of related investments from the past year, comprise the overall Electronics Resurgence Initiative.”

Among these programs is the “Three Dimensional Monolithic System-on-a-Chip (3DSoC): Develop 3D monolithic technology that will enable > 50X improvement in SoC digital performance at power.”

In perfect timing, this year’s IEEE S3S 2017 at the Hyatt Regency at the San Francisco Airport will feature a comprehensive show case for monolithic 3D IC technologies.

At the start Al Fazio, Intel Senior Fellow, will give a plenary talk on how 3D NAND and 3D XPoint™ happened to be the trailblazing monolithic 3D IC technologies that have matured to volume production, taking over the fast growing memory market. The first day will end with two 3D IC focus sessions comprised of a mix of invited and submitted papers covering exotic technologies and the use of the emerging nano-wire transistor for 3D scaling.

The first half of the second day includes a collaborative event organized by Qualcomm and CEA Leti – the COOLCUBE/3DVLSI Open Workshop. The second half will include an open 3D tutorial providing full coverage of the various 3D integration technologies from TSV to Sequential Integrations.

The third day of the conference will include a full day with four sessions of invited and submitted talks on monolithic and other forms of 3D integration. These sessions will include a talk by us, MonolithIC 3D Inc., in which we will present a monolithic 3D technology that is ready to be rapidly deployed using the current transistor process. In that talk we will also describe how such an integration technology could be used to improve performance, reduce power and cost of most computer systems, suggestive of a 1,000x total system benefit.

In addition, the IEEE S3S conference will have full coverage of SOI and low power technologies, making it the place to be and to learn about alternative technologies to dimensional scaling. I am looking forward to seeing you at the S3S from October 16th thru 19th, 2017.

GLOBALFOUNDRIES announces enhanced RF SOI process design kit

September 18, 2017

GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications.

GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design.

“GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.”

“This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.”

GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs.

SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com.

Driven by TV size migration, large TFT display market continues to grow 6% by area in 2017

September 15, 2017

The large thin film transistor (TFT) display market is expected to continue to expand in 2017 despite slower end-market demand, according to IHS Markit (Nasdaq: INFO).

While unit shipments are expected to be up 1 percent in 2017 to 688 million units, compared to the previous year, area shipment forecasts show growth of 6 percent in the same period, to 180 million square meters.

Figure 1

Among displays of 9 inches or larger, tablet PC displays are on track to record the highest year-on-year growth in unit shipments in 2017, with 10 percent growth to 93 million units. “It is because first-tier set brands are increasing the number of tablet PC models with larger screens. The new 10.5-inch iPad pro is a good example,” said Peter Su, principal analyst at IHS Markit.

The second fastest-growing application is notebook PC displays, with a 4 percent year-on-year growth to about 175 million units. “Chinese panel makers are aggressively trying to expand in this market, while first-tier panel makers are actually retreating panel production,” Su said.

On the flip side, TV displays are showing a contraction in 2017 by 3 percent year on year, dropping to 257 million units due to slower end-market demand. “Prices of large displays, particularly TV panels, have stayed high for almost a year. TV brands started revising down their business plan, cutting their panel purchases,” Su said.

In terms of area shipments, however, large displays for all applications are forecast to see growth in 2017 as larger screens become more popular with consumers. TV display accounts for 78 percent of total large display shipments by area, and is expected to see a 5 percent growth in 2017.

“First-tier panel makers, especially South Korean companies, already started shifting their production to larger sizes — 49 inches or larger — while reducing production of smaller panels, with lower profitability, to achieve better financial performance,” Su said. “Chinese panel makers are following suit and started increasing production of larger TV displays to 43-inch or larger.”

For a panel manufacturer’s perspective, preparing for potential oversupply in the near future is another reason behind the TV size migration. New fabs are under construction in China, including 10.5 generation, and could increase supply significantly. “One way for panel makers to overcome the oversupply is to increase area consumption via size migration,” Su said.

LG Display is expected to continue accounting for the largest market share in 2017 with 21 percent as measured by unit shipments. BOE, a Chinese display maker that has been increasing its shipments significantly, is forecast to take 20.7 percent, up 2 percentage points from 2016, gaining on LG Display.

Figure 2

Semiconductor industry records best second quarter in three years

September 14, 2017

Despite a slightly down first quarter, the semiconductor industry achieved near record growth in the second quarter of 2017, posting a 6.1 percent growth from the previous quarter, according to IHS Markit (Nasdaq: INFO). Global revenue came in at $101.4 billion, up from $95.6 billion in the first quarter of 2017. This is the highest growth the industry has seen in the second quarter since 2014.

The memory chip market set records in the second quarter, growing 10.7 percent to a new high of $30.2 billion with DRAM and NOR flash memory leading the charge, growing 14 percent and 12.3 percent quarter-on-quarter, respectively.

“The DRAM market had another quarter of record revenues on the strength of higher prices and growth in shipments,” said Mike Howard, director for DRAM memory and storage at IHS Markit. “Anxiety about product availability in the previous third and fourth quarters weighed on the industry. This led many DRAM buyers to build inventory — putting additional pressure on the already tight market. This year is shaping up to smash all DRAM revenue records and will easily pass the $60 billion mark.”

“For NOR, the supply-demand balance has tightened raising average selling prices and revenue,” said Clifford Leimbach, senior analyst for memory and storage at IHS Markit. “This mature memory technology has been in a steady decline for many years, but some market suppliers are reducing supply or leaving the market, which has tightened supply recently, resulting in the increase of revenue.”

In terms of application, consumer electronics and data processing saw the most growth, increasing in revenue by 7.9 percent and 6.8 percent, respectively, quarter-on-quarter. A lot of this growth can be attributed to the continual growth in memory pricing, as supply still remains tight.

Industrial semiconductors showed the third highest growth rate at 6.4 percent during the same period. This growth can be attributable to multiple segments, such as commercial and military avionics, digital signage, network video surveillance, HVAC, smart meters, traction, PV inverters, LED lighting and medical electronics including cardiac equipment, hearing aids and imaging systems.

Another trend in the industrial market is increasing factory automation, which alone is driving growth for discrete power transistors, thyristors, rectifiers and power diodes. The market for these devices is expected to reach $8 billion in 2021, up from $5.7 billion in 2015.

Intel remains the number one semiconductor supplier in the world, followed by Samsung Electronics by a slight margin. IHS Markit does not include foundry operations and other non-semiconductor revenue in the semiconductor market rankings.

Among the top 20 semiconductor suppliers, Advanced Micro Devices (AMD) and nVidia achieved the highest revenue growth quarter over quarter by 24.7 percent and 14.6 percent, respectively. There was no market share movement in the top 10 semiconductor suppliers. However, seven of the 10 companies in the 11 to 20 market share slots did change market share.