Tag Archives: letter-pulse-top

With its unique characteristics, FD-SOI is generating increasingly strong interest from major players in the semiconductor ecosystem for a very wide range of markets.

BY MANUEL SELLIER, Soitec, Bernin (Grenoble), France

Fully depleted silicon-on-insulator or FD-SOI is the only technology bringing together two substantial characteristics of CMOS transistors: 2D planar transistor structure and fully depleted operation. It relies on a unique substrate whose layer thicknesses are controlled at the atomic scale. FD-SOI offers remarkable transistor performance with one of the best power, performance, area and cost tradeoffs (PPAC) among all advanced CMOS technologies. In addition, FD-SOI has numerous other unique advantages including back bias ability, very good transistor matching, near threshold supply capability, ultra-low sensitivity to radiation and very high intrinsic transistor speed, which allows it to handle mmWave frequencies.

All these key features are progressively making FD-SOI a de facto technology for many applications including entry-level application processors for smartphones, system-on- chip (SoC) devices for autonomous driving and IoT, and all mmWave applications such as 5G transceivers and radar systems for automotive electronics.

FD-SOI technology is supported by multiple foundries and IDMs with full technology offerings now available for the 28nm and 22nm nodes and emerging for the 65nm and 12nm nodes. With this global ecosystem in place, FD-SOI is ready for applications development for diversified markets.
There are several striking characteristics of FD-SOI substrates that give this technology unique advantages. This article summarizes the latest advances and the various elements of the global ecosystem that supportwidespread implementation of FD-SOI as well as the applications that most benefit from it.

The heart of FD-SOI

Everything in FD-SOI technology starts with the substrate. The substrate directly defines the transistor architecture, as shown in FIGURE 1. To allow the fully depleted operation of transistors, the thickness of the top silicon layer defining the device channel represents a real challenge, with the thickness target typically around 60 Å or 11 atomic layers. Given the consumption of silicon material during device fabrication, a 120 Å incoming top silicon specification is usually required by foundries. Uniformity is another very challenging specification needed to keep transistor variability as low as possible. Uniformity of +/-5 Å or 1 atomic layer is typically considered essential. Buried oxide (BOx) thickness also must be very thin – around 20nm – to maximize electrostatic control in the transistor channel due to the ground plane effect.

Screen Shot 2017-04-27 at 12.01.02 PM

Manufacturing a 300mm piece of crystalline silicon with a thickness specification as low as 11 +/-1 atomic layers is understandably difficult. Ten years ago, it sounded unachievable so people studied other paths to enable fully depleted transistors [1]. But it is now possible.

Fabrication relies on the well-known Smart Cut TM process (FIGURE 2). As shown, wafer A first undergoes an oxidation step followed by high-dose ion implantation, creating a weakened layer just beneath the surface. After careful cleaning steps, wafer A is bonded to wafer B through molecular-bonding technology. Splitting is then induced at the precise location of the weakened zone of wafer A. Finally, the formed SOI wafer is subjected to other smoothing process steps to achieve the targeted thickness specification. It is noteworthy that high-quality wafer A can be recycled for further reuse, making Smart Cut the most cost- effective solution for SOI manufacturing.

Screen Shot 2017-04-27 at 12.01.10 PM

The FD-SOI substrate-manufacturing process is now fully mature. In particular, thickness uniformity is very well controlled at all levels, from transistor to wafer, as shown in FIGURE 3. This ensures a very low level of transistor variability.

Screen Shot 2017-04-27 at 12.01.22 PM

When less is more

The way of getting more performance out of silicon below 28nm node adds more complexity to the manufacturing process. Consequently, as illustrated in FIGURE 4, the smaller nodes get, the greater number of masks are needed to create chips. This increases manufacturing costs as well as other non-recurring engineering costs including design flow, design verification, mask sets and more.

Screen Shot 2017-04-27 at 12.01.32 PM

On the other hand, FD-SOI is a simple technology from a manufacturing standpoint. In fact, it offers more perfor- mance while decreasing the manufacturing process complexity. Most of the channel engineering work is actually done directly at the substrate level, making FD-SOI easier to implement than bulk silicon, as major foundries have reported [2] [3].

The next level of transistor performance

In addition to simpler manufacturing, FD-SOI offers other substantial benefits, as depicted below and summarized in FIGURE 5.

Screen Shot 2017-04-27 at 12.01.46 PM Screen Shot 2017-04-27 at 12.01.53 PM

1. Better design flexibility through body bias

The thin BOx of FD-SOI not only enhances electro- static control of the channel, but also makes it possible to completely tune the threshold voltage through back biasing. All the complex Vth adjustment techniques through channel doping can be avoided. Low, mid-range and high Vth can be achieved simply through back-gate polarization. The thin BOx behaves like a real second gate and, most importantly, it can be used dynami- cally. This means that the same functional block can operate under high or low power, on demand. Back bias potential is huge: selective body bias for critical path improvements [4], process variation compensation [5] and reliability drift compensation [6]. Full back biasing is a very unique feature, only achievable with SOI on thin BOx technology.

2. Power-performance-area-cost tradeoff: Best PPAC of all planar technologies.

Thanks to simpler manufacturing, better control of random mismatch, minimizing of junction leakage and capacitances, enhanced electrostatic control through fully depleted transistor operation and the possibility of tuning body bias, FD-SOI technology presents the best power- performance-area-cost tradeoff (PPAC) among all planar technologies.

3. Ultra-low power through near-threshold supply voltage

Almost all CMOS technologies achieve their best energy efficiency – i.e., the lowest amount of energy per function, regardless of the frequency – at around 0.4 V supply voltage, often referred to as Vdd [7]. At this level of supply voltage, variability management is a real challenge. Thanks to body bias and to its intrinsic low-variability characteristics, FD-SOI can achieve very low supply voltages. More generally, the ability to lower the supply voltage, although not necessarily as low as 0.4 V, is a real challenge in many applications in which power is a greater challenge than performance. Given the fact that dynamic power scales with Vdd2, a technology like FD-SOI that is capable of strong power savings through tremendous supply voltage reduction presents a unique advantage.

4. Best RF-CMOS technology with almost 2 times maximum frequency over 3D devices

Integrating as many analog/RF functions as possible into a single RF-CMOS silicon platform is becoming an increasingly important issue in many markets for obvious cost and power reasons. However, one limitation of RF-CMOS platforms is the limited ability to increase frequency, especially in the mmWave spectrum (30 GHz and above). This is a bigger issue with 3D devices such as FinFETs, which must carry very strong parasitic capaci- tances due to their 3D structures [8]. As a result, SiGe- Bipolar platforms are often used for this frequency range. FD-SOI is a planar technology and, as such, it should not suffer from the limitations of 3D devices. Ft/Fmax in the range of 325-350 GHz have been reported [3], allowing full usage of the mmWave spectrum up to 100 GHz and giving FD-SOI RF-CMOS platforms a bright future in many applications.

5. Enhanced reliability

Low sensitivity to high-energy particles is another key characteristic of FD-SOI. High-energy particles can interact with silicon and generate a significant amount of charges capable of flipping transistor logic state, thus increasing the soft errors rate (SER). FD-SOI devices are completely isolated from the substrate due to the BOx layer. This means that any charge generated in the substrate is unlikely to modify the device logic state. In short, FD-SOI is much less sensitive to SER [9]. This has very important consequences for safety-critical devices such as autonomous car systems.

6. Outstanding analog transistor characteristics

Often, analog designers have to make their designs work with more and more degraded transistors as technology shrinks. Meeting speed, noise, power, leakage and variability requirements is increas- ingly challenging. By providing a transistor with improved matching, gain and parasitic, FD-SOI can greatly simplify device design [10]. Moreover, the back bias has potential for the design of many new analog structures [11].

FD-SOI’s growing use at foundries

Some of the most pioneering work with FD-SOI has been done at semiconductor foundries around the world.

STMicroelectronics adopted FD-SOI technology in 2012 [12] and started several projects. The company demonstrated an ARM-based application processor for smart-phones with 3 GHz+ operating frequency on 28nm FD-SOI [13]. The technology is now used at STMicroelectronics for many diversified markets [14] [15].

In 2014, Samsung announced the adoption of 28nm FD-SOI technology for its foundry division [15]. Mass production maturity was reached in 2016 [2], and the first product release was announced recently [16] [17].

In 2015, GLOBALFOUNDRIES developed a 22nm FD-SOI technology called 22FDX [18], which it positioned as offering the best performance/cost ratio. This FD-SOI technology platform achieved performance close to 16nm/14nm FinFET at a cost similar to 28nm bulk silicon [19]. The first commercial product was announced in February 2017 by GLOBALFOUNDRIES and Dream Chip Technologies [20]. GLOBALFOUNDRIES’ technology is now almost fully qualified, with volume ramp-up expected this year.

In Asia, the Chinese foundry Huali has announced its intention to include 22nm FD-SOI technology in its fab2 plan [21], offering the Chinese market greater access to FD-SOI technology.

In Japan, Renesas’ experience with FD-SOI includes work on a very low-power FD-SOI technology called silicon- on-thin-BOx (SOTB), which targets low-power MCU markets. This technology has been supported by the LEAP initiative (Low-Power Electronics Association and Project) and is now available in 65nm. Renesas has reported very low-power consumption with this platform, as small as a tenth of that achieved using bulk silicon.

IP/CAD status and roadmap

The design ecosystem is well established for 28nm FD-SOI with complete libraries and foundation IP and growing at a fast pace for 22nm technology. EDA companies are on board and developing IP ported to FD-SOI.

In September 2016, GLOBALFOUNDRIES announced a new partner program called FDXceleratorTM to facil- itate 22FDX SoC design and reduce time to market for its customers including Synopsys, Cadence, INVECAS, VeriSilicon, CEA-Leti, Dream Chip and Encore Semi [22]. In December 2016, the foundry announced the addition of eight new partners to its growing FDXcel- erator program including Advanced Semiconductor Engineering (ASE Group), Amkor Technology, Infosys, Mentor Graphics, Rambus, Sasken, Sonics and Quick- Logic [23].

As for the technology roadmap, FD-SOI is available on a wide range of technology nodes from 65nm to 12nm with visibility down to 7nm. Building on the success of its 22FDX offering, in 2016 GLOBALFOUNDRIES unveiled a new 12nm FD-SOI semiconductor technology called 12FDX [24]. Staying with fully depleted planar processing allows the foundry to take advantage of the low parasitic capacitance, avoid the complex lithog- raphy steps required by equivalent 3D transistors, and leverage back biasing to boost transistor performance, especially at low supply voltages. Customer product tape-outs are expected to begin by the end of 2017.

Leti, which pioneered FD-SOI development 15 years ago, worked with GLOBALFOUNDRIES on the 22FDX and 12FDX platforms. The organization recently developed test devices on 10nm FD-SOI technology and produced models for 10nm and 7nm on FD-SOI. Leti strongly believes that FD-SOI can be scaled down to 7nm.

Both Samsung and GLOBALFOUNDRIES plan to have embedded non-volatile memory integrated into their FD-SOI technology platforms by 2018 [2] [3].

FD-SOI traction in power and analog/RF integration ThankstothegrowingmaturityoftheFD-SOIecosystem, there is now a wide range of applications seeing strong differentiation possibilities through FD-SOI. These include single-chip solutions for entry-level mobile communications, general purpose application processors, image signal processors, SoC for set-top boxes, embedded computer vision, microcontrollers, mixed-signal applications such as transceivers, GPS/satellite receivers, wi-fi/ BT combos and mmWave radar systems.

For all these applications, power budget is typically very limited and must be balanced with performance targets. A good example of this can be found in embedded computing applications such as ADAS, where designers must constantly find compromises to achieve the required performance with a very limited power budget, typically around 3 W. For all embedded computing applications, FD-SOI – and its ability to run on very low supply voltages – is gaining momentum as the reference technology.

In addition, RF/analog integration is often key for these applications. Having best-in-class RF-CMOS technology available on the same silicon die as the digital parts is a unique advantage of FD-SOI. It opens up possibilities for single-chip solutions covering a wide range of functions. This is particularly advantageous in entry-level markets such as low-end mobile, where the price pressure is so great that integration must be pushed to its limits, or in mmWave applications including radar and 5G transceivers, where the mmWave RF functions can be integrated on the same die as the computing functions.

A new wave of ground-breaking products

The list of FD-SOI-based products is increasing at a very fast pace, with multiple product announcements over the past months.

In September 2016, Huami (a Xiaomi partner company) introduced a new fitness smartwatch that includes a FD-SOI-based global positioning system (GPS) chip demonstrating record energy efficiency (FIGURE 6) [25]. The chip allows the watch to reach an unsurpassed battery life of 35 hours with the GPS turned on, which represents two to five times more than today’s similar devices. The chip, revealed in February 2016 at the International Solid- State Circuits Conference (ISSCC) in San Francisco [27], dramatically lowers power usage and opens the door for always-on GPS applications in smartwatches, smart-phones, drones and a large number of devices for the IoT.

Also in 2016, Mobileye posted on its website that its next EyeQ4 product family dedicated to level3 autonomous driving will be based on FD-SOI technology [26] (FIGURE 7).

Screen Shot 2017-04-27 at 12.02.09 PM

In March 2017, NXP released two general-purpose processor families (i.MX7ULP and i.M8X) [16] [17] based on Samsung’s 28FDS FD-SOI technology for ultra-low power consumption and rich graphics in battery-powered applications (see NXP roadmap FIGURE 8). NXP reported a deep-sleep suspended power consumption of 15 μW or less for its i.MX7ULP product, 17 times less in comparison to previous low-power bulk devices, while the dynamic power efficiency improved by 50 percent. This high-performance, low-power solution is optimized for customers developing IoT, home control, wearable and other applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing.

Screen Shot 2017-04-27 at 12.02.17 PM

In March 2017, Eutelsat Communications and STMicroelectronics announced a new-generation SoC for interactive applications that represents a step down in the overall cost of interactive satellite terminals while reducing power consumption [14].

On the 22nm side, Dream Chip announced the industry’s first 22nm FD-SOI product for a new ADAS SoC for automotive computer-vision applications [20]. The SoC device (FIGURE 9) offers high- performance image acquisition and processing capabilities and supports convolutional neural network (CNN) vision workloads to meet the demand for complex automotive object detection and processing.

Screen Shot 2017-04-27 at 12.02.27 PM

The 22nm FD-SOI product portfolio is expected to grow significantly in the coming year as the technology ramps up.

Adding fabs to meet overall FD-SOI demand

Faced with the growing interest of FD-SOI, particularly in China, foundries are organizing themselves to build up enough production capacity. In February 2017, GLOBALFOUNDRIES announced plans to expand the capacity of its Fab 1 facility in Dresden by 40 percent by 2020. Dresden will continue to be the center for FDX technology development [27].

In China, GLOBALFOUNDRIES and the Chengdu munici- pality have announced a partnership to build a fab. The partners plan to establish a 300mm fab to support the growth of the Chinese semiconductor market and to meet accelerating global customer demand for 22FDX [27]. The fab will begin producing mainstream process technologies in 2018 and then focus on manufacturing GLOBALFOUNDRIES’ commercially available 22FDX process technology, with volume production expected to start in 2019.

With these two announcements, GLOBALFOUNDRIES will have a future production capacity of more than 2 million FD-SOI wafers per year.

Regarding FD-SOI substrate manufacturing capacity, Soitec owns one 300mm fab in France and has another one in Singapore (currently in standby mode) with a combined global capacity of 1.5 million wafers per year (for manufacturing FD-SOI and other emerging SOI products). The company has plans to go beyond that to meet additional customer demand.

Conclusion

Growing interest in FD-SOI reflects today’s new paradigm for semiconductor technologies. Customers are demanding for more computing capability with drastically reduced power consumption, enabled by enhanced analog/RF integration. With its unique characteristics, FD-SOI is generating increasingly strong interest from major players in the semiconductor ecosystem for a very wide range of markets, especially for embedded computing applications. FD-SOI is now a mainstream technology, which device designers are leveraging for key competitive advantages.

Acknowledgements

The author would like to warmly thank the Soitec team (Christophe Maleville, Bich-Yen Nguyen, Thomas Piliszczuk, Alexandra Givert, and Camille Dufour) for their valuable contribution and constructive discussions.

References

1. H. Chenming, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices, p. 2320–2325, December 2000.
2. Y. Jeon (SAMSUNG), “The industry’s first mass-produced FD-SOI technology for the IoT era, with single design platform benefits,” in SOI Industry Consortium workshop, Tokyo, 2016.
3. J. Schaeffer (GLOBALFOUNDRIES), “FDX Rising,” in GLOBAL- FOUNDRIES Technology Conference, San Jose, 2016.
4. W. Abbey (ARM), “Realize the potential of FD-SOI,” in SOI Industry Consortium workshop, San Jose, 2016.
5. P. Flatresse (ST), “FD-SOI ULV, Body Biasing & Demonstrators,” in LETI days FDSOICE Workshop, GRENOBLE, 2015.
6. C. Ndiaye (ST), “Performance vs. reliability adaptive body bias scheme in 28nm & 14nm UTBB FD-SOI nodes,” Microelectronics Reliability, 2016.
7. B. Zha, in VLSI symposium, 2006.
8. IMEC, chez VLSI Design, 2010.
9. P. Roche (ST), “Technology downscaling worsening radiation effects in bulk: SOI to the rescue,” in IEDM, 2013.
10. G. Cesana (ST), “Advances in Applications and Ecosystem for the FD-SOI Technology,” in LETI days FDSOICE Workshop, GRENOBLE, 2015.
11. A. Cathelin (ST), “On the usage of FBB for inverter-based Analog and RF 28nm UTBB FD-SOI circuits : example of a 450MHz Gm-C filter with IIP3> 1dBv over a 0.7-1V power supply,” in LETI Days FDSOICE Workshop, GRENOBLE, 2015.
12. STMicroelectronics Announces Its 28nm FD-SOI Technology Is Ready for Manufacturing in Its Leading-Edge Crolles Fab, ST Press Release, 2012.
13. ST-Ericsson brings PC speeds to mobile devices: First 3Ghz smartphone prototype demo at Mobile World Congress, STE Press Release, February 20, 2013.
14. EUTELSAT and STMicroelectronics announce low-cost, low-power, system-on-chip for interactive satellite terminals, EUTELSAT Press Release, March 8, 2017.
15. G. Desoli (ST), «A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems,» chez International Solid-State Circuits Conference (ISSCC), 2017.
16. Samsung and STMicroelectronics Sign Strategic Agreement to Expand 28nm FD-SOI Technology, Samsung/STMicroelectronics Press Release, May 14, 2014.
17. NXP Taps into FD-SOI Technology to Enable the Industry’s Lowest Power General Purpose Applications Processors, NXP Press Release, March 13, 2017.
18. NXP Delivers Increased Safety, Reliability and Scalability to Industrial Applications with New i.MX 8X Processors, NXP Press Release, March 14, 2017.
19. GLOBALFOUNDRIES Launches Industry’s First 22nm FD-SOI Technology Platform, GLOBALFOUNDRIES Press Release, July 13, 2015.
20. S. Jha (GLOBALFOUNDRIES), “The Right Technology at the Right Time,” in SOI Industry Consortium workshop, Shanghai, 2015.
21. Dream Chip Technologies Presents First 22nm FD-SOI Silicon of New Automotive Driver Assistance SoC, DREAM CHIP Press Release, February 27, 2017.
22. R. Merritt, “China Defends Big Chip Bet – Inside Huali’s $5.9 billion bet on Fab 2,” EETIMES, January 12, 2017.
23. GLOBALFOUNDRIES Unveils Ecosystem Partner Program to Accelerate Innovation for Tomorrow’s Connected Systems, GLOBALFOUNDRIES Press Release, September 8, 2016.
24. GLOBALFOUNDRIES Expands Partner Program to Speed Time- to-Market of FDXTM Solutions, GLOBALFOUNDRIES Press Release, December 15, 2016. www.solid-state.com
25. GLOBALFOUNDRIES Extends FDXTM Roadmap with 12nm FD-SOI Technology, GLOBALFOUNDRIES Press Release, September 8, 2016.
26. J. Yoshida, «Sony-Inside Huami Watch: Is It Time for FD-SOI?,» October 4, 2016.
27. K. Yamamoto (SONY), “A 0.7V 1.5-to-2.3mW GNSS receiver with 2.5-to-3.8dB NF in 28nm FD-SOI,” in International Solid-State Circuits Conference (ISSCC), 2016.
28. Mobileye, “The Evolution of EyeQ,” [Online]. Available: http:// www.mobileye.com/our-technology/evolution-eyeq-chip/. [Accessed 29 March 2017].
29. GLOBALFOUNDRIES Expands to Meet Worldwide Customer Demand, GLOBALFOUNDRIES Press Release, February 9, 2017.

The new Samsung Galaxy S8 equipped with 64 gigabytes (GB) of NAND flash memory carries a bill of materials (BOM) cost that comes out to US$301.60, much higher than for previous versions of the company’s smartphones, according to a preliminary estimate from IHS Markit (Nasdaq: INFO).

After $5.90 in basic manufacturing costs are added, Samsung’s total cost to make the Galaxy S8 rises to $307.50; the unsubsidized price for a 64GB Galaxy S8 starts at around $720. The preliminary estimated total at this point is $43.34 higher than that of the Galaxy S7 previously performed by IHS Markit, and is $36.29 higher than the total build cost of the Galaxy S7 Edge, considered a better comparison to the Galaxy S8. IHS Markit has not yet performed a teardown analysis on the larger Galaxy S8 Plus.

“The higher total BOM costs for the Galaxy S8 seem to be part of a trend that reflects something of an arms race in features among Apple, Samsung and other phone manufacturers, as they all try to add new and distinguishing hardware features,” said Andrew Rassweiler, senior director of cost benchmarking services for IHS Markit. “While there are new non-hardware features in the Galaxy S8, such as a virtual assistant called Bixby, from a teardown perspective the hardware in the Galaxy S8 and that of the forthcoming new iPhone is expected to be very similar.”

The introduction of the Galaxy S8 comes at a delicate time for the embattled South Korean electronics giant, which is eager to put behind the challenges associated with the Galaxy Note 7, whose exploding batteries prompted a worldwide recall.

The latest salvo from Samsung shows how it’s keen to regain consumer confidence and attain leadership in the smartphone landscape, a nearly saturated but still highly competitive space that remains key to retaining subscriber loyalties and winning new converts.

First smartphone capable of gigabit-LTE speeds

Both the Galaxy S8 and S8 Plus feature a 10-nanometer (nm) system-on-chip (SoC) along with CAT-16 LTE modem and radio. The CDMA version of the S8, intended for use in the United States as well as in China, will feature the Snapdragon 835 chipset from San Diego-based Qualcomm. In comparison, a version of the phone featuring Samsung’s homegrown Exynos 8895 chipset will be used for the rest of the world.

The CAT-16 LTE radio allows the new Galaxy phone to aggregate three carriers of up to 20 megahertz each. Combined with 4×4 MIMO antennas and higher-order modulation of 256 QAM, the LTE modem is capable of reaching peak theoretical speeds of one gigabit per second. “Gigabit LTE is very much the marquee specification for 2017 flagship smartphones,” said Wayne Lam, principal analyst of smartphone electronics, IHS Markit. “Keep in mind that gigabit speeds are a best-case scenario and that a user’s real-world experience will be limited to what mobile networks can provide.”

New “Infinity Display” design fits better in hand

The redesigned Galaxy S8 has a tall, narrow shape that is 1.5 millimeters narrower than the previous Galaxy S7, providing slick new ergonomics while also optimizing screen real estate. The screen curves around the edges, and Samsung designers have maximized the display, relative to the size of the phone, with a 5.8-inch 2960×1440 AMOLED display and an elongated aspect ratio of 18.5:9. Compared to conventional 16:9 aspect-ratio Quad HD smartphone displays, the Galaxy S8 features an additional 15 percent more pixels in a form factor that is easier to hold in the hand. The device’s haptic engine, which provides the “click” feel for users, also has been improved for longer-duty cycles and a more dynamic response.

Double the base-model storage

Both the Galaxy S8 and S8 Plus feature 4GB of RAM and built-in storage of 64GB—twice the standard built-in storage found in the Galaxy S7 as well as the iPhone 7. Storage for the new Samsung phones can also be expanded, up to 256GB, via a microSD card. The Samsung NAND flash memory and DRAM on the S8 come in at a cost of $41.50. Rassweiler said: “While in previous years the cost per gigabyte has generally fallen in both the NAND flash and DRAM areas, we have seen rising prices in both DRAM and NAND flash recently due to some tightness in the marketplace. The cost of memory in the S8 reflects these recent market dynamics, even though we expect the erosion in memory pricing—something that occurs regularly in the memory market—to resume during the course of the year.”

Battery

The battery capacity on the Galaxy S8, at 3000 milliamp hour (mAh), is the same as that found in last year’s Galaxy S7. However, compared to the Galaxy S7 Edge, which had a 3600mAh battery, Samsung played it safe after the Note 7 incident and included a considerably less dense battery pack. Overall cost estimate for the Galaxy S8 battery pack is $4.50.

Single camera lens

Although the Galaxy S8 and S8 Plus come with new features and the latest components, each still has only a single camera in the back—essentially the same as the camera module found in last year’s Galaxy S7. Apple’s iPhone 7 Plus, the newly launched LG G6 and many Chinese OEMs are now promoting dual cameras as a key feature. Owing to the asymmetric placement of the rear fingerprint sensor, it would have been likely that a dual-camera design was scrapped at the last minute in the design cycle.

T.J. Rodgers, founder and former CEO of Cypress Semiconductor Corporation (NASDAQ:  CY) and the Company’s largest individual stockholder, today filed a lawsuit in the Delaware Court of Chancery seeking to compel the Cypress Board of Directors to make supplemental and corrective disclosures to address numerous material omissions and misstatements of fact in the Cypress Board’s proxy materials.

Rodgers said, “Cypress directors have a legally mandated ‘Duty of Candor’ to make complete disclosures to Cypress stockholders on the issues in this election, including why they are allowing Ray Bingham to serve as executive chairman while he has violated and is continuing to violate numerous provisions of Cypress’s Code of Business Conduct and Ethics.  This second lawsuit seeks to ensure that Cypress stockholders have the information they need to cast an informed vote at the upcoming June 8, 2017 Annual Meeting.”

Bingham’s employment by a Cypress competitor is an ongoing conflict of interest 

While simultaneously serving as Cypress executive chairman, Mr. Bingham is also actively working as a “Founding Partner” of Canyon Bridge, a private equity firm backed by the People’s Republic of China that now competes head-on with Cypress in the critical semiconductor M&A market. The Cypress Board has asserted in the Company’s proxy statement that Mr. Bingham’s simultaneous executive leadership roles at Canyon Bridge and Cypress do not constitute a conflict of interest under the Cypress Business Conduct and Code of Ethics and thus claims that Rodgers’s assertions are “unfounded and have no basis.”

Rodgers said, “I believe that by making this assertion in an important legal document distributed to stockholders, the Cypress Board of Directors has deliberately chosen to ignore our first, successful lawsuit to obtain Cypress documents and thus solicited Cypress stockholders using material misstatements and omissions including the failure to disclose critical legal findings made by the DelawareCourt of Chancery.  In particular the Court stated:

“The dual hats Bingham wears suggest that his interests with respect to Canyon Bridge may well conflict with the business interests of Cypress,” and that a “credible basis” exists “to infer that Bingham violated the Code’s prohibition on ‘simultaneous employment of any kind without written permission of the Company.'”

Rodgers continued, “Cypress stockholders have a right to accurate and complete information before voting at the annual meeting, yet the Cypress Board continues to ignore its Duty of Candor by misleading stockholders regarding Mr. Bingham’s conflicts as well as the Board’s own failure to address this serious problem, which it has known about at least since December 9, 2016 when I wrote a private letter describing the problem and urging Board action.”

In addition to having a conflict of interest, Mr. Bingham also has negotiated excessive compensation for his part-time work at the currently unnecessary job of executive chairman. His annual salary plus target bonus is $877,500, and he has been granted a total of $4.5 million in restricted stock units (RSUs). Despite Mr. Bingham’s part-time attendance at Cypress, the Cypress Board has kept him on as executive chairman and has very recently awarded him RSUs worth $3 million, which vest over three years, undermining the Board’s claim that Mr. Bingham’s executive chairman “mentoring” position is “temporary.” To make matters worse, in stark contrast to all Cypress executives eligible for the Company’s PARS (Performance Accelerated Restricted Stock) program, his RSUs vest without any performance requirements – meaning that Mr. Bingham will receive $4.5 million in compensation for simply remaining at Cypress in a part-time position, while also working for a direct Cypress Chinese-sovereign-backed competitor.

On April 21, 2017, the Delaware Court of Chancery entered an order requiring Cypress to produce documents in response to Rodgers’s Section 220 demand to investigate potential breaches of fiduciary duty and violations of Cypress’s Code of Business Conduct and Ethics by Ray Bingham and the failures by the Cypress Board to take corrective action. The Court’s Post-Trial Opinion, issued on April 17, 2017, held that Rodgers was entitled to all the categories of documents that he sought but which Cypress had refused to produce.

Rodgers stated, “As a major Cypress fan and major stockholder with most of my net worth invested in the Company, I am driven by my belief that these serious wrongdoings, unaddressed by the Cypress Board, are a threat to stockholder value. The Board has a duty to the Cypress stockholders to resolve the executive chairman’s obvious conflict of interest and gross overcompensation problems. I have made a standing offer to the Cypress Board that if candidates J. Daniel McCranie and Camillo Martino are seated on the Board under appropriate terms and with appropriate committee positions, despite their being a distinct minority of two among current directors, I would trust in their energy and integrity to resolve these problems – without the need for further litigation or a proxy contest and without the requirement that Mr. Bingham and lead independent director Eric Benhamou leave the Cypress Board. Does this offer sound vendetta-driven to you? The Board is fully aware of my offer, which still stands, yet it has resorted to what I believe are false proxy statements and ad hominem attacks on the nominees and me as a smokescreen to cover for its refusal to address the big problem: Cypress should not be forced to complete against its own executive chairman in the M&A market.”

Rodgers’s second lawsuit focuses on the Cypress Board’s refusal to disclose the truth about Bingham’s work for a direct Cypress competitor

Rodgers’s claims in the second lawsuit filed today in the Delaware Court of Chancery include specific allegations regarding Cypress’s Definitive Proxy Statement and other proxy materials which:

  • Fail to describe accurately and completely the timing and scope of Mr. Bingham’s activities at Canyon Bridge;
  • Fail to mention even one of the seven separate and individually applicable ethical guidelines and procedures that Mr. Bingham violated by founding and acting on behalf of Canyon Bridge—a direct competitor of Cypress in the critical semiconductor M&A market;
  • Falsely state that Rodgers’s concerns regarding Bingham’s irreconcilable conflict of interest are unfounded despite the finding to the contrary by the Delaware Court of Chancery that Rodgers has a credible basis to believe that Mr. Bingham’s relationships with Canyon Bridge and Cypress represent a conflict of interest;
  • Fail to disclose the Cypress Board’s actual factual findings, conclusions, and decisions regarding Mr. Bingham’s relationship with Canyon Bridge, Bingham’s non-compliance with Cypress’ Code of Business Conduct and Ethics, and the potential risks to Cypress resulting from Mr. Bingham’s work for a direct competitor of Cypress;
  • Fail to disclose what was discussed, what decisions made, and what actions taken as a result of a call between Cypress “lead independent director” Eric Benhamou and an unidentified senior representative of Canyon Bridge (and their respective lawyers) on January 23, 2017.

Rodgers calls on the Board of Directors of Cypress to make full and accurate disclosures to Cypress stockholders promptly regarding these important issues at the heart of the upcoming election of directors.

Rodgers concluded, “At the upcoming Annual Meeting, stockholders will have the opportunity to elect two extraordinary new Directors, who would upgrade the Cypress Board. Dan McCranie and Camillo Martino have the operational expertise necessary to guide Cypress through the next stage of its growth and to take appropriate steps to protect Cypress from future ethical conflicts. In contrast to the current members of the Cypress Board, McCranie and Martino have experience as semiconductor company CEOs to complement their governance experience and reputations for integrity.”

North America-based manufacturers of semiconductor equipment posted $2.03 billion in billings worldwide in March 2017 (three-month average basis), according to the March Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in March 2017 was $2.03 billion. The billings figure is 2.6 percent higher than the final February 2017 level of $1.97 billion, and is 69.2 percent higher than the March 2016 billings level of $1.20 billion.

“March billings reached robust levels not seen since March 2001,” said Dan Tracy, senior director, Industry Research and Statistics, SEMI. “The equipment industry is clearly benefiting from the latest semiconductor investment cycle.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Year-Over-Year
 October 2016

$1,630.4

20.0%
 November 2016

$1,613.3

25.2%
 December 2016

$1,869.8

38.5%
 January 2017

$1,859.4

52.3%
 February 2017 (final)

$1,974.0

63.9%
 March 2017 (prelim)

$2,026.2

69.2%

Source: SEMI (www.semi.org), April 2017

SEMI ceased publishing the monthly North America Book-to-Bill report in January 2017. SEMI will continue publish a monthly North American Billings report and issue the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions.

By Douglas G. Sutherland and David W. Price

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

While working at the Guinness® brewing company in Dublin, Ireland in the early-1900s, William Sealy Gosset developed a statistical algorithm called the T-test1. Gosset used this algorithm to determine the best-yielding varieties of barley to minimize costs for his employer, but to help protect Guinness’ intellectual property he published his work under the pen name “Student.” The version of the T-test that we use today is a refinement made by Sir Ronald Fisher, a colleague of Gosset’s at Oxford University, but it is still commonly referred to as Student’s T-test. This paper does not address the mathematical nature of the T-test itself but rather looks at the amount of data required to consistently achieve the ninety-five percent confidence level in the T-test result.

A T-test is a statistical algorithm used to determine if two samples are part of the same parent population. It does not resolve the question unequivocally but rather calculates the probability that the two samples are part of the same parent population. As an example, if we developed a new methodology for cleaning an etch chamber, we would want to show that it resulted in fewer fall-on particles. Using a wafer inspection system, we could measure the particle count on wafers in the chamber following the old cleaning process and then measure the particle count again following the new cleaning process. We could then use a T-test to tell if the difference was statistically significant or just the result of random fluctuations. The T-test answers the question: what is the probability that two samples are part of the same population?

However, as shown in Figure 1, there are two ways that a T-Test can give a false result: a false positive or a false negative. To confirm that the experimental data is actually different from the baseline, the T-test usually has to score less than 5% (i.e. less than 5% probability of a false positive). However, if the T-test scores greater than 5% (a negative result), it doesn’t tell you anything about the probability of that result being false. The probability of false negatives is governed by the number of measurements. So there are always two criteria: (1) Did my experiment pass or fail the T-test? (2) Did I take enough measurements to be confident in the result? It is that last question that we try to address in this paper.

Figure 1. A “Truth Table” highlights the two ways that a T-Test can give the wrong result.

Figure 1. A “Truth Table” highlights the two ways that a T-Test can give the wrong result.

Changes to the semiconductor manufacturing process are expensive propositions. Implementing a change that doesn’t do anything (false positive) is not only a waste of time but potentially harmful. Not implementing a change that could have been beneficial (false negative) could cost tens of millions of dollars in lost opportunity. It is important to have the appropriate degree of confidence in your results and to do so requires that you use a sample size that is appropriate for the size of the change you are trying to affect. In the example of the etch cleaning procedure, this means that inspection data from a sufficient number of wafers needs to be collected in order to determine whether or not the new clean procedure truly reduces particle count.

In general, the bigger the difference between two things, the easier it is to tell them apart. It is easier to tell red from blue than it is to distinguish between two different shades of red or between two different shades of blue. Similarly, the less variability there is in a sample, the easier it is to see a change2. In statistics the variability (sometimes referred to as noise) is usually measured in units of standard deviation (σ). It is often convenient to also express the difference in the means of two samples in units of σ (e.g., the mean of the experimental results was 1σ below the mean of the baseline). The advantage of this is that it normalizes the results to a common unit of measure (σ). Simply stating that two means are separated by some absolute value is not very informative (e.g., the average of A is greater than the average of B by 42). However, if we can express that absolute number in units of standard deviations, then it immediately puts the problem in context and instantly provides an understanding of how far apart these two values are in relative terms (e.g., the average of A is greater than the average of B by 1 standard deviation).

Figure 2 shows two examples of data sets, before and after a change. These can be thought of in terms of the etch chamber cleaning experiment we discussed earlier. The baseline data is the particle count per wafer before the new clean process and the results data is the particle count per wafer after the new clean procedure. Figure 2A shows the results of a small change in the mean of a data set with high standard deviation and figure 2B shows the results of the same sized change in the mean but with less noisy data (lower standard deviation). You will require more data (e.g., more wafers inspected) to confirm the change in figure 2A than in figure 2B simply because the signal-to-noise ratio is lower in 2A even though the absolute change is the same in both cases.

Figure 2. Both charts show the same absolute change, before and after, but 2B (right) has much lower standard deviation. When the change is small relative to the standard deviation as in 2A (left) it will require more data to confirm it.

Figure 2. Both charts show the same absolute change, before and after, but 2B (right) has much lower standard deviation. When the change is small relative to the standard deviation as in 2A (left) it will require more data to confirm it.

The question is: how much data do we need to confidently tell the difference? Visually, we can see this when we plot the data in terms of the Standard Error (SE). The SE can be thought of as the error in calculating the average (e.g., the average was X +/- SE). The SE is proportional to σ/√n where n is the sample size. Figure 3 shows the SE for two different samples as a function of the number of measurements, n.

Figure 3. The Standard Error (SE) in the average of two samples with different means. In this case the standard deviation is the same in both data sets but that need not be the case. With greater than x measurements the error bars no longer overlap and one can state with 95% confidence that the two populations are distinct.

Figure 3. The Standard Error (SE) in the average of two samples with different means. In this case the standard deviation is the same in both data sets but that need not be the case. With greater than x measurements the error bars no longer overlap and one can state with 95% confidence that the two populations are distinct.

For a given difference in the means and a given standard deviation we can calculate the number of measurements, x, required to eliminate the overlap in the Standard Errors of these two measurements (at a given confidence level).

The actual equation to determine the correct sample size in the T-test is given by,

Equation 1

Equation 1

where n is the required sample size, “Delta” is the difference between the two means measured in units of standard deviation (σ) and Zx is the area under the T distribution at probability x. For α=0.05 (5% chance of a false positive) and β=0.95 (5% chance of a false negative), Z1-α/2 and Zβ are equal to 1.960 and 1.645 respectively (Z values for other values of α and β are available in most statistics textbooks, Microsoft® Excel® or on the web). As seen in Figure 3 and shown mathematically in Eq 1, as the difference between the two populations (Delta) becomes smaller, the number of measurements required to tell them apart will become exponentially larger. Figure 4 shows the required sample size as a function of the Delta between the means expressed in units of σ. As expected, for large changes, greater than 3σ, one can confirm the T-test 95% of the time with very little data. As Delta gets smaller, more measurements are required to consistently confirm the change. A change of only one standard deviation requires 26 measurements before and after, but a change of 0.5σ requires over 100 measurements.

Figure 4. Sample size required to confirm a given change in the mean of two populations with 5% false positives and 5% false negatives

Figure 4. Sample size required to confirm a given change in the mean of two populations with 5% false positives and 5% false negatives

The relationship between the size of the change and the minimum number of measurements required to detect it has ramifications for the type of metrology or inspection tool that can be employed to confirm a given change. Figure 5 uses the results from figure 4 to show the time it would take to confirm a given change with different tool types. In this example the sample size is measured in number of wafers. For fast tools (high throughput, such as laser scanning wafer inspection systems) it is feasible to confirm relatively small improvements (<0.5σ) in the process because they can make the 200 required measurements (100 before and 100 after) in a relatively short time. Slower tools such as e-beam inspection systems are limited to detecting only gross changes in the process, where the improvement is greater than 2σ. Even here the measurement time alone means that it can be weeks before one can confirm a positive result. For the etch chamber cleaning example, it would be necessary to quickly determine the results of the change in clean procedure so that the etch tool could be put back into production. Thus, the best inspection system to determine the change in particle counts would be a high throughput system that can detect the particles of interest with low wafer-to-wafer variability.

Figure 5. The measurement time required to determine a given change for process control tools with four different throughputs (e-Beam, Broadband Plasma, Laser Scattering and Metrology)

Figure 5. The measurement time required to determine a given change for process control tools with four different throughputs (e-Beam, Broadband Plasma, Laser Scattering and Metrology)

Experiments are expensive to run. They can be a waste of time and resources if they result in a false positive and can result in millions of dollars of unrealized opportunity if they result in a false negative. To have the appropriate degree of confidence in your results you must use the correct sample size (and thus the appropriate tools) that correspond to the size of the change you are trying to affect.

References:

  1. https://en.wikipedia.org/wiki/William_Sealy_Gosset
  2. Process Watch: Know Your Enemy, Solid State Technology, March 2015

About the Authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Samsung Electronics Co., Ltd. announced today that its second generation 10-nanometer (nm) FinFET process technology, 10LPP (Low Power Plus), has been qualified and is ready for production. With further enhancement in 3D FinFET structure, 10LPP allows up to 10-percent higher performance or 15-percent lower power consumption compared to the first generation 10LPE (Low-Power Early) process with the same area scaling.

Samsung was the first in the industry to begin mass production of system-on-chips (SoCs) products on 10LPE last October. The latest Samsung Galaxy S8 smartphones are powered by some of these SoCs.

To meet long-term demand for the 10nm process for a wide range of customers, Samsung has started installing production equipment at its newest S3-line in Hwaseong, Korea. The S3-line is expected to be ready for production by the fourth quarter of this year.

“With our successful 10LPE production experience, we have commenced production of the 10LPP to maintain our leadership in the advanced-node foundry market,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “10LPP will be one of our key process offerings for high performance mobile, computing and network applications, and Samsung will continue to offer the most advanced logic process technology.”

According to the latest market study released by Technavio, the electrostatic discharge (ESD) packaging market is projected to grow to USD 5.42 billion by 2021, at a CAGR of more than 8% over the forecast period.

Global_ESD_Packaging_Market

This research report titled ‘ESD Packaging Market 2017-2021’ provides an in-depth analysis of the market in terms of revenue and emerging market trends. This market research report also includes up to date analysis and forecasts for various market segments and all geographical regions.

Communication network infrastructure

“The communication network infrastructure end-user segment occupies a significant 26% of the global ESD packaging market. The high rate of deployment of next-generation wireless networks such as Wi-Fi, WiMAX, 3G/4G, and ultra-wideband is responsible for the dominance of the market segment,” says Sharan Raj, a lead analyst at Technavio for packaging research.

The growth in the wireless network infrastructure market drives the demand for printed circuit boards (PCBs), which require ESD protection. Also, the increase in virtualization and cloud computing have resulted in increased Internet traffic worldwide, which is also indirectly boosting the market growth.

Consumer electronics industry

The consumer electronics segment includes smartphones, PCs, audio systems, video systems, and TVs, all of which incorporate sophisticated and high-performance printed circuit boards (PCBs) and semiconductors for efficient working. These electronic devices, combined with the rapid adoption of 3G and 4G networks, are driving the growth of ESD packaging in the market segment. Currently, APAC is showcasing an impressive growth curve in the market segment, driven by an extremely high mobile phone subscription rate.

Computer peripherals

“The computer peripherals segment is expected to reach a value of around USD 1,141 million by 2021. This segment includes products such as a mouse, keyboards, printers, hard drives, flash drives, scanners, webcams, and digital cameras which require ESD protection,” says Sharan.

This end-user segment is expected to be driven by the increased demand for tablets, notebooks, ultrabooks, and digital cameras. Further, the introduction of Windows 10 and lightweight ultrabooks will add a boost to the growth of the market segment.

The top vendors highlighted by Technavio’s research analysts in this report are:

  • BASF
  • Desco Industries
  • Dow Chemical
  • PPG Industries

Technavio is a global technology research and advisory company.

Worldwide semiconductor revenue is forecast to total $386 billion in 2017, an increase of 12.3 percent from 2016, according to Gartner, Inc. Favorable market conditions that gained momentum in the second half of 2016, particularly for commodity memory, have accelerated and raised the outlook for the market in 2017 and 2018. However, the memory market is fickle, and additional capacity in both DRAM and NAND flash is expected to result in a correction in 2019.

“While price increases for both DRAM and NAND flash memory are raising the outlook for the overall semiconductor market, it will also put pressure on margins for system vendors of smartphones, PCs and servers,” said Jon Erensen, research director at Gartner. “Component shortages, a rising bill of materials, and the prospect of having to counter by raising average selling prices (ASPs) will create a volatile market in 2017 and 2018.”

PC DRAM pricing has doubled since the middle of 2016. A 4GB module that cost $12.50 has jumped to just under $25 today. NAND flash ASPs increased sequentially in the second half of 2016 and the first quarter of 2017. Pricing for both DRAM and NAND is expected to peak in the second quarter of 2017, but relief is not expected until later in the year as content increases in key applications, such as smartphones, have vendors scrambling for supply.

“With memory vendors expanding their margins though 2017, the temptation will be to add new capacity,” said Mr. Erensen. “We also expect to see China make a concerted effort to join the memory industry, setting the market up for a downturn in 2019.”

Unit production estimates for premium smartphones, graphics cards, video game consoles and automotive applications have improved and contributed to the stronger outlook in 2017. In addition, electronic equipment with heavy exposure to DRAM and NAND flash saw semiconductor revenue estimates increase. This includes PCs, ultramobiles, servers and solid-state drives.

“The outlook for emerging opportunities for semiconductors in the Internet of Things (IoT) and wearable electronics remains choppy with these markets still in the early stages of development and too small to have a significant impact on overall semiconductor revenue growth in 2017,” said Mr. Erensen.

The new, higher-speed DDR4 DRAM generation gained significant marketshare in 2016, representing 45% of total DRAM sales. Previously, DDR3 DRAM, including low-power versions used in tablets, smartphones, and notebook PCs, accounted for 84% of total DRAM sales in 2014 and 76% in 2015, but in 2016, DDR4 price premiums evaporated and prices fell to nearly the same ASP as DDR3 DRAMs. A growing number of microprocessors, like Intel’s newest 14nm x86 Core processors, now contain DDR4 controllers and interfaces.  As a result, IC Insights expects DDR4 to become the dominant DRAM generation in 2017 with 58% marketshare versus 39% for DDR3 (Figure 1).

Figure 1

Figure 1

The Joint Electron Devices Engineering Council (JEDEC) officially launched the fourth generation of DDR in 2012.  In 2014, DDR4 memories first began appearing on the market in DRAM modules for powerful servers and a small number of high-end desktop computers, which had souped-up motherboards or the “extreme” versions of Intel’s 22nm Haswell-E processors for high-performance gaming software and PC enthusiasts, but volume sales remained low until 2015, when data centers and Internet companies began loading up servers with the new-generation memories to increase performance and lower power consumption. In 2016, DDR4 memories quickly spread into more data center servers, mainframes, and high-end PCs, accounting for about 45% of total DRAM sales versus 20% in 2015.  In 2017, DDR4 will move into more notebook PCs, high-end tablets, and smartphones and is expected to hold a 58% share of DRAM sales.

The DDR4 standard contains a number of features that are expected to speed up memory operations and increase SDRAM storage in servers, notebook and desktop PCs, tablet computers, and a wide range of consumer electronics.  The DDR4 standard supports stacked memory chips with up to eight devices presenting a single signal load to memory controllers.  Compared to DDR3, DDR4 can potentially double the module density, double the speed, and lower power consumption up to 20%, thereby extending battery life in future 64-bit tablets and smartphones.

Meanwhile, the DRAM average selling price has been increasing very rapidly since mid-2016.  Figure 2 shows that the DRAM ASP increased 54% from $2.41 in April 2016 to $3.70 in February 2017.  As a result of this big increase, IC Insights raised its 2017 DRAM market forecast to $57.3 billion, which is a 39% increase over 2016.  IC Insights believes that DRAM ASPs will continue to trend upward through most of the first half of 2017, though probably not as rapidly as they did between the period from April 2016 to February 2017.

Figure 2

Figure 2

In its latest quarterly financial conference call, Micron indicated its DRAM outlook through the balance of its fiscal year 2017 (ending August 31) was very encouraging, with solid demand coming from PC, server, communication, automotive, and several other applications.

However, the bigger question for Micron and other top DRAM suppliers is available supply and whether (more accurately, when will) prices plateau and begin trending downward.  One indication that DRAM prices could soften in the second half of the year is the fact that Samsung and SK Hynix are bringing additional DRAM capacity online that features smaller process geometries. Samsung is slated to begin operations at its new Fab 18, in Pyeongtaek, South Korea in 2Q17.  Fab 18, with capacity of 300,000 300mm wafer starts per month, features five production lines that are dedicated primarily to making DRAM.  The company plans to begin DRAM operations at the fab using an 18nm process technology.

SK Hynix has transitioned most of its South Korean-based DRAM output from Fab M10 to Fab M14. With Fab M14 and its dedicated DRAM fab in Wuxi, China, SK Hynix has DRAM capacity of about 280,000 300mm wafer starts per month.  SK Hynix is manufacturing most of its DRAM at the 21nm node, but expects to begin using sub 20nm process technology later this year, thereby helping to reduce costs and increase the number of chips on a wafer.

Following a year of extraordinary gains in pricing, a boost to DRAM supply in the second half of 2017 could lead to reduced ASPs and the inevitable start of a cyclical slowdown in the DRAM market.

Participating in the DRAM market has always been a big challenge for suppliers.  Hot or cold, boom or bust—the DRAM market is rarely moving along in a steady, predictable manner.  For at least the first half of 2017, it appears that DRAM market will be very favorable for these top three suppliers.

“In 2016, the MOSFET market recovered, after a minor downturn in 2015,” announced Yole Développement (Yole) in its latest power electronics report, Power MOSFET: Market & Technology Trends. With stable growth, mainly in automotive and industrial sales in 2016 the overall silicon power MOSFET market size surpassed 2014’s performance.

“We expect the market to grow steadily thanks to increasing demand for efficient electronics, in which power MOSFETs play a vital role”, explains Zhen Zong, Technology & Market Analyst, Power Electronics at Yole. Overall market revenue neared US$6.2 billion. From 2016 to 2022 Yole estimates a 3.4% CAGR.

mosfet market

Under this dynamic ecosystem, Yole reinforces its market positioning within the power electronics industry. The “More than Moore” market research and strategy consulting company is covering step by step the whole power electronics supply chain: from substrates with innovative WBG materials including GaN , SiC , Bulk GaN… to devices (IGBT, MOSFET, gate drivers IC …), modules and systems. In parallel, the company also enlarges its core expertise towards batteries and energy management sector. Yole’s strategy is clearly to propose a deep understanding of the overall power electronics industry by taking into account technical innovations such as WBG technologies, analyze the impact on the supply chain and identify business opportunities.

Yole’s power electronics team attends PCIM Europe with a booth and its annual powerful Power Electronics Market Briefing. During this briefing, the consulting company is inviting industrial leaders to speak and proposes detailed presentations focused on the power semiconductor industry.

Power MOSFET report is one of the key 2017 reports proposed by Yole’s team. It provides an overview of the entire market, with a comprehensive analysis of the players in each market segment with their product range and technologies.

“Under this new report, our aim is to propose our vision of the power electronics industry, from an end-users perspective,” explained Dr Pierric Gueguen, Business Unit Manager at Yole. “Our analysis highlights the corresponding impact on MOSFET technologies and the introduction of WBG technologies which represent only less than 2% of the overall power electronics market today but are showing a real growth potential in a near future.”

In 2016, 25 million electrified vehicles were sold. Power MOSFET sales in automotive applications have surpassed computing and data storage, now representing more than 20% of the total market. As vehicle numbers increase worldwide and people adopt electrified vehicles, this sector’s rapid growth will continue at 5.1% CAGR between 2016 and 2022.

Power MOSFETs are widely used in various automotive applications involving braking systems, engine management, power steering and other small motor control circuits, in which a low conduction loss and high commutation speed device is very much appreciated. Silicon power MOSFETs are also becoming increasingly popular in EV/HEV converters, depending on their electrification level. For battery chargers MOSFETs can handle roughly 3-6 kW, which is perfect for small size plug-in EVs or full EVs. They are also used for 48V DC/DC converters and other micro inverters in the start/stop function module. With the trend of EV/HEV adoption led by Tesla, Yole’s analysts believe this market segment will become increasingly important in the next 5-10 years.

Computing and storage market segment which includes desktops, laptops, as well as different kinds of servers in the datacenters comes to the second largest market. With the declining sales number of personal PCs this market segment is slowing down and has been surpassed by automotive part in 2016. However with the increasing demand for servers and datacenters, the whole segment is still having a steady increase, posting a 2.8% CAGR for the 2016-2022 period.

Power electronics market future may depend on governmental decisions concerning electrified vehicles as well as renewable energies applications. It includes CO2 reduction targets, energy efficiency increases… Both markets could be the most important in 2030, announces Yole in its MOSFET report. On the other hand, other large volume applications may come, such as 5G, drones or robots. All those applications, demanding power supply, will clearly pull the MOSFET market.

Today it is not possible to get a comprehensive understanding of the MOSFETs market without taking into account the impact of the innovative WBG technologies including SiC and GaN.
Silicon power MOSFETs have been developing for 20 years. Ceaseless improvement and technology innovations from planar to trench structure and today’s super junction, have reduced silicon MOSFET device sizes and costs dramatically. They have been massively used in various application segments – but today, device performance has reached silicon’s theoretical limit.
Chasing better performance and even smaller devices size, today the power electronics industry is at the beginning of SiC and GaN’s adoption. Ever more new companies are promoting SiC and GaN solutions and new designs. At Yole, analysts believe this will be the next technology evolution stage. However, this does not necessarily mean doom for silicon power MOSFETs.

“Looking back at the development of bipolar transistors and power MOSFETs in the past 20 years in different applications, we expect that there will still be a very solid market share reserved for silicon power MOSFETs”, analyzes Zhen Zong from Yole. With increasing need in the end applications, the overall market size for MOSFETs will not necessarily decline.

Over the next 5-10 years, Yole envisions some GaN devices coming out and being implemented for high frequency switch applications in the low-to-mid voltage 100-200V range, but remaining a small portion. Both SiC and GaN devices will penetrate the high frequency market around 600V, but will probably only be popular in particular markets, like EV on-board chargers and data center power supply units. The majority of the market will still use silicon power MOSFETs, thanks to their proven reliability and good cost performance ratio.