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By Zvi Or-Bach, President & CEO, MonolithIC 3D Inc.

As we have predicted two and a half years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.

Our March 2014 blog Moore’s Law has stopped at 28nm has recently been re-confirmed. At the time we wrote: “From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.” This reconfirmation can be found in the following IBS cost analysis table slide, presented at the early Sept FD-SOI event in Shanghai.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

As reported by EE Times – Chip Process War Heats Up, and quoting Handel Jones of IBS “28nm node is likely to be the biggest process of all through 2025”.

IBS prediction was seconded by “Samsung executive showed a foil saying it believes 28nm will have the lowest cost per transistor of any node.” The following chart was presented by Samsung at the recent SEMICON West (2016).

Zvi 2

And even Intel has given up on its “every two years” but still claims it can keep reducing transistor cost. Yet Intel’s underwhelming successes as a foundry suggests otherwise. We have discussed it in a blog titled Intel — The Litmus Test, and it was essentially repeated by SemiWiki’s Apple will NEVER use Intel Custom Foundry!

This discussion seems academic now, as the actual engineering costs of devices in advanced nodes have shown themselves to be too expensive for much of the industry. Consequently, and as predicted, the industry is bifurcating, with a few products pursuing scaling to 7nm while the majority of designs use 28nm or older nodes.

The following chart derived from TSMC quarterly earnings reports was published last week by Ed Sperling in the blog Stepping Back From Scaling:

Zvi 3

Yes, the 50-year march of Moore’s Law has ended, and the industry is now facing a new reality.

This is good news for innovation, as a diversity of choices helps support new ideas and new technologies such as 3D NAND, FDSOI, MEMS and others. These technologies will enable new markets and products such as the emerging market of IoT.

A good opportunity to learn more about these new scaling technologies is the IEEE S3S ’16, to be held in the Hyatt Regency San Francisco Airport, October 10th thru 13th, 2016. It starts with 3D and FDSOI tutorials, the emerging technologies for the IC future. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D, and three leading researchers from an imec, MIT, and Korea university collaboration will present their work on advanced monolithic 3D integration technologies. Many other authors will discuss their work on monolithic 3DIC and its ecosystem, in addition to tracks focused on SOI, sub-VT and dedicated sessions on IoT.

Asia-Pacific’s grip as the dominant market for IC sales is forecast to strengthen in 2016 with the region expected to account for 61.0% of the $282.0 billion IC market this year, based on analysis published in IC Insights’ mid-year Update to the 2016 IC Market Drivers report.  The forecast calls for another small gain in total IC marketshare in 2016 after Asia-Pacific held 57.7% share in 2013, 58.4% in 2014, and 60.5% in 2015. The Asia-Pacific region is particularly dominant with regard to IC marketshare in the communications and computer categories, and to a lesser extent in the consumer and industrial categories (Figure 1).  In 2016, IC Insights expects the Asia-Pacific region to surpass Europe and become the largest region for automotive ICs for the first time, as China continues to account for a large and growing portion of new car shipments.  That will leave only the Government/Military end use segment where Asia-Pacific does not have top IC marketshare—a condition that is forecast to hold through 2019.

Figure 1

Figure 1

IC Insights’ Update to the IC Market Drivers 2016 report forecasts total IC usage by system type through the year 2019. Highlights from the forecast include the following items.

– The Asia-Pacific region is forecast to increase its share of the IC market to 62.3% in 2019, from 61.0% forecast for 2016. Over the same time, North American is also forecast to increase marketshare to 23.8%. Conversely, Europe and Japan are expected to lose IC marketshare through 2019. Japan’s IC marketshare is forecast to slip to 5.5% and Europe is forecast to slide to 8.3% in 2019.

– The two fastest growing end-use markets for ICs through 2019 are forecast to be the automotive and industrial/medical segments, having 2015-2019 CAGRs of 8.0% and 7.1%, respectively.  Though having the greatest CAGR through 2019, the automotive IC market is not expected to account for more than 8.0% of total IC sales any time through the forecast period.

– After slumping to only $10.6 billion in 2009, the automotive IC market is forecast to reach nearly 3x that amount ($28.0 billion) in 2019.

– The two largest end-use markets (computer and communications) are forecast to account for 73.7% of the total IC market in 2019, almost the same as the 73.9% share they are forecast to hold in 2016.

– In 2016, analog ICs are forecast to account for the greatest share of IC sales within the automotive (45%) and industrial (50%) segments; logic devices are expected to account for the greatest share of IC sales in communications (41%), consumer (41%), and government/military (32%) applications, and microprocessors are forecast to account for the greatest share (42%) of IC sales in the computer segment.

BY DR. BERND DIELACHER, DR. MARTIN EIBELHUBER and DR. THOMAS UHRMANN, EV Group, St. Florian, Austria

Over the past several decades, miniaturization has significantly improved clinical diagnostics, pharmaceutical research and analytical chemistry. Modern biotechnology devices— such as biosensors, fully integrated systems for diagnostics, cell-analysis or drug discovery—are often chip-based and rely on close interaction of biological substances at the micro- and nanoscale. Thus, process technologies that enable the production of surface patterns and integration of fluidic components with small feature sizes are needed (FIGURE 1).

FIGURE 1. Biotechnology devices utilize a variety of structures at the micro- and nanoscale that interact with biological substances.

FIGURE 1. Biotechnology devices utilize a variety of structures at the micro- and nanoscale that interact with
biological substances.

Today’s miniaturized biotechnology devices can be found in numerous applications, including fields related to human health as well as environmental and industrial sciences. For example, chemical sensors and biosensors are commonly used to analyze pH values, levels of electrolytes and blood-gas. Glucose sensors are a prominent example of highly successful commercial devices used for diabetes monitoring, where miniaturization has enhanced the development of implantable chips for continuous glucose level monitoring inside the human body.Fully integrated systems, including micro- and nanopumps for accurate insulin release, have also been shown. In general, such controlled drug delivery systems offer new opportunities for the treatment of common acute and chronic diseases. Moreover, microneedle arrays, which allow minimally invasive and painless delivery of drugs through the skin, neural electrodes for stimulation or monitoring signals inside the brain, or prosthetic devices such as artificial retinas, have also been developed.

Microfluidics plays a key role in the transport and manipulation of biological fluids in biotechnology devices. For example, laminar flow behavior can be overserved, which allows a well-defined control of liquids. Capillary forces can enable fluid flow without the need of active pumps. In addition, short distances reduce diffusion times of molecules, which lead to faster biological reactions. Overall, microfluidic devices offer a high degree of parallelization while using extremely-low-volume samples. Microfluidic devices that perform complete tasks or analysis, usually done in a laboratory, are referred to as lab-on-chip (LOC) devices. Other names include bio-chips or micro-Total-Analysis- Systems (μ-TAS). These systems are used in applications such as in-vitro diagnostics, high-throughput screening, genomics and drug discovery. LOC devices are also ideally suited for point-of-care testing (POCT), where they provide rapid diagnostics at the patient site.

Nanoimprint lithography

To successfully commercialize such products in a fast growing market with stringent requirements and high regulatory hurdles, precise and cost-effective micro- structuring technologies are essential. Nanoimprint lithography (NIL) has evolved from a niche technology to a powerful high-volume manufacturing method that is able to serve today’s needs and overcome the challenges of increasing complexity of microfluidic devices in particular, and biotechnology devices in general. NIL is a patterning technique capable of producing a multitude of different sizes and shapes on a large scale by imprinting either into a biocompatible resist or directly into the bulk material with resolutions down to 20 nm. NIL can be distinguished between three types of imprint technologies: hot-embossing or thermal NIL, UV-NIL, and micro- contact printing (μ-CP).

Hot-embossing is a cost-effective and relatively simple process, well suited for the fabrication of polymer microfluidic devices with very high replication accuracy of small features down to 50 nm (FIGURE 2). A polymer sheet or spin-on-polymer is heated above its glass transition temperature, transforming the material into a viscous state. A stamp containing the negative copy of the struc- tures is then pressed into the polymer with sufficient force to conformally mold the polymer. De-embossing is done after cooling the substrate below a certain temperature where the material retains its shape when removing the stamp. During hot-embossing, the structure is trans- ferred by displacement of the viscous material. The process is characterized by short flow paths of the material, moderate flow velocities and imprinting temperatures. Residual stress is therefore low, especially when comparing the process to injection molding, which is an alternative production technique for microfluidics.

FIGURE 2: a) 200-μm wide microfluidic channels and b) 10- μm pillar arrays with high aspect ratios (7:1) fabricated by hot- embossing (Courtesy of National Research Council Canada). c) Schematic drawing of hot-embossing process flow.

FIGURE 2: a) 200-μm wide microfluidic channels and b) 10- μm pillar arrays with high aspect ratios (7:1) fabricated by hot- embossing (Courtesy of National Research Council Canada). c) Schematic drawing of hot-embossing process flow.

FIGURE 2: a) 200-μm wide microfluidic channels and b) 10- μm pillar arrays with high aspect ratios (7:1) fabricated by hot- embossing (Courtesy of National Research Council Canada). c) Schematic drawing of hot-embossing process flow.

Because of the much higher process temperatures and pressures associated with injection molding, final products produced by this process usually experience higher internal residual stress, which easily results in significant deformation, such as warpage and shrinkage. In addition, a surface solidifi- cation layer is formed at the interface of the cold mold during the injection of the high-temperature molten polymer. This effect significantly influences the replication accuracy and optical quality. Extensive effort in process development and simulation is therefore often necessary for injection molding to replicate small features in an accurate manner. In contrast, hot-embossing allows precise replication of micro- and nanostructures with less effort and is superior when replicating high-aspect ratio features or when using very-thin substrates. Structures with high-aspect ratios are often needed in microfluidic chips for filtration elements, particle separation or cell sorting.

The ability to use very thin substrates enables the patterning of spin-on-polymer layers on top of other materials or even roll-to-roll embossing using polymer foils for very-high-throughput production. Parallel wafer-based batch processing also enables fabrication of typical-sized microfluidic chips with throughputs compa- rable to or even higher than injection molding or similar techniques. Since master stamps for hot-embossing do not need to withstand the high temperatures and forces required for mold inserts for injection molding, they are less expensive to produce. Therefore, hot-embossing is also a well suited technology for R&D and allows easier design changes in volume-production. UV-NIL refers to a technique where a transparent stamp is pressed into a photo-curable resist and cross-linked by UV-light while still in contact (FIGURE 3). In biotechnology applications, the resist is usually coated onto silicon or glass substrates. Unlike hot-embossing, the UV-NIL stamp is brought in contact with the resist using minimum force to conformally join the stamp and substrate. The different mechanisms of curing and stamp attachment account for different advantages and fields of application of the respective technologies.

FIGURE 3: (a) 100-nm grating with residual layer <10 nm imprinted into 90 nm height resist on silicon substrate and (b) 350-nm photonic crystal fabricated by UV-NIL. c) Schematic drawing of UV-NIL process flow.

FIGURE 3: (a) 100-nm grating with residual layer

UV-NIL provides very-high-alignment accuracy, pattern fidelity, and throughput whereas hot-embossing is capable of imprinting higher aspect ratios and larger structures in the upper micron range as well as combinations of micro- and nanostructures. UV-NIL offers additional opportunities for biotechnology devices where features with ultra- high precision are needed. Examples include optical-based biosensors that often rely on noble metal nanostructures that influence properties of coupled light upon the binding of molecules onto the nanostructures.Regardless of what the sensing principle is based on (e.g. localized surface plasmon resonance or photonic band gaps), small changes in shape and size can significantly alter the properties of the sensing element.

In order to produce nanostructures made of metals, either additive or subtractive processes can be used. The former involves the deposition of a metal layer onto the patterned resist followed by a lift-off process, whereas the latter involves the transfer of the pattern into an underlying metal layer by etching processes. In both cases, the small residual layer must first be removed. Having a uniform residual layer is of high importance, especially for subse- quent etching processes, and can be easily achieved with current equipment over large areas. Imprinted UV-NIL resists can also be used directly as functional layers. After many years of continuous resist development, a broad portfolio of optimized resist materials is available for various bio-applications. Another interesting aspect, especially for microfluidic devices, is the potential of nanostructures to influence surface properties. For example, nanostructures can change the surface behavior from hydrophilic to hydrophobic, which can be used to locally influence the fluid flow.

While UV-NIL is ideally suited for fabricating very small features, it is not well suited for features larger than several tens of micrometers. In cases where both highly-accurate nanostructures and large microfluidic channels are needed, hot-embossing can be used to imprint the channels on a separate substrate. The two substrates can subsequently be bonded together to produce the final device.

A third NIL option is μ-CP, where a pre-inked stamp is used to transfer materials such as biomolecules onto a substrate in a distinct pattern (FIGURE 4). Local modification of surface chemistry can, for example, be used to guide the growth of neurons on a chip. On the other hand, it can be used for the precise placement of capture molecules in biosensor fabrication. This technique is applicable on all common surfaces, such as silicon, glass or polymers with micro- and nanometer resolution and offers new possibilities for functionalization of biotechnology devices.

FIGURE 4: Bio-functionalized, micro-patterned array
created by micro-contact printing for the detection of protein- protein interactions in live cells. a) Antibody-patterns induce the recruitment of two interacting proteins to micro-patterns, which is detected by fluorescence microscopy. b) Missing interaction of the two candidate proteins leads to homogenous distribution on the functionalized surface. c) Schematic drawing of micro-contact printing process flow. [Images adapted from Schwarzenbacher et al., 2008, Nature Methods; Weghuber et al., 2010, Methods in Enzymology].

FIGURE 4: Bio-functionalized, micro-patterned array
created by micro-contact printing for the detection of protein- protein interactions in live cells. a) Antibody-patterns induce the recruitment of two interacting proteins to micro-patterns, which is detected by fluorescence microscopy. b) Missing interaction of the two candidate proteins leads to homogenous distribution on the functionalized surface. c) Schematic drawing of micro-contact printing process flow. [Images adapted from Schwarzenbacher et al., 2008, Nature Methods; Weghuber et al., 2010, Methods in Enzymology].

Although most current microfluidic devices do not follow the same degree of miniaturization in terms of chip-size compared to the microelectronics industry, large-scale parallel processing has a significant advantage in terms of costs and flexibility (FIGURE 5). Alternative fabrication techniques for microfluidic chips, such as injection molding, are principally serial processes and have limita- tions in up-scaling.Using nanoimprinting,30chipsofthe size of a microscopy slide (25 x 75 mm) can easily fit on a single 300-mm substrate. This format can be considered a good reference for an average- sized microfluidic chip. In terms of throughput, wafer-based batch processing is able to reach similar or better cycle times per device compared to alternative solutions, such as injection molding. UV-NIL has even been introduced on GEN2 substrates (370 x 470 mm). In addition, roll- to-roll processing can reach even higher throughput levels but is restricted to the structuring of flexible foils.

FIGURE 5: Large-area parallel processing offers significant advantages in terms of cost and flexibility. Additional processes, such as electrode fabrication or spotting of reagents, can also be efficiently integrated.

FIGURE 5: Large-area parallel processing offers significant advantages in terms of cost and flexibility. Additional processes, such as electrode fabrication or spotting of reagents, can also be efficiently integrated.

Wafer bonding

NIL has an additional advantage in terms of post- processing. Electrode fabrication, surface treatments or spotting of bio-reagents can be efficiently integrated in a large-area batch. The same is true for sealing and encapsulation, an essential process step for all biotechnology devices. It is usually mandatory to close micro-fluidic channels, to fabricate a hermetic sealing for protection against environmental influences or even to provide packaging that is compatible for implantation into human bodies. In addition, interconnections to the outer world have to be incorporated, such as holes or fluidic connectors. Electronic connections or assembling the device together with an integrated microelectronic chip is also often necessary. Thus, bonding of different device layers, capping layers or interconnection layers is a key process that can be implemented together with NIL in a cost-effective large-area batch process. NIL has an additional advantage of providing a high surface quality that can significantly improve subsequent bonding of polymer devices. Surface roughness, total-thickness variation as well as warpage are usually lower than in devices fabricated by injection molding. In the following section, several well-suited bonding processes for sealing biotechnology devices are discussed (FIGURE 6).

FIGURE 6: Typical bonding options for biotechnology devices that are well suited in combination with NIL processes.

FIGURE 6: Typical bonding options for biotechnology devices that are well suited in combination with NIL processes.

A common requirement in biotechnology applications is optical transparency, at least from one side, since most devices rely on optical readouts. Glass is therefore often used as a capping layer for highly complex devices made of silicon. In such cases, anodic bonding can provide a high-quality hermetic seal, where bonding is achieved by high voltage and heat causing inter-diffusion of ions. Another process for joining glass or polymer devices is thermal bonding using high temperatures and pressures. Special attention has to be paid when using this technique for bonding polymer and, in particular, polymer micro-fluidic devices. Thermal bonding is performed by heating the substrate near or above the glass transition temper- ature, which softens the material. The additional pressure generates sufficient flow of polymer at the interface to achieve intimate contact and inter-diffusion of polymer chains. Pressure is removed after the substrate is cooled down to a specific value below the glass transition temperature. Un-optimized temperature and pressure can easily lead to deformation of microstructures. Plasma as well as UV and ozone treatment can be used to activate the polymer surface, which allows bonding at reduced temperatures and reduces the risk of deformation. Anodic and thermal bonding are interlayer-free processes and therefore do not introduce any additional material to the device.

Adhesive bonding is another process that found widespread use in sealing or encapsulating bio-technology devices. Many biocompatible adhesives are available today and high bond strength can be expected from this technique. Bonding with adhesives can be used to join many different materials. Often liquid adhesives are used, which can be cured thermally or by exposure to UV light. The latter offers a significant advantage that addresses another important issue in many pharmaceu- tical or diagnostic devices where bio-molecules have to be incorporated before sealing the device. UV-curing allows bonding at room-temperature whereas higher temperatures usually lead to denaturation or complete destruction of bio-molecules.

Adhesives usually have to be selectively deposited on the substrate, which can be achieved with μ-contact printing. Similar to bio-molecule printing, an adhesive can be trans- ferred onto the substrate according to the pattern of the stamp. In contrast, however, an adhesive can be spin coated onto a transfer plate, which is then brought into contact with the substrate. By releasing the transfer plate, the adhesive will remain on the heightened structures. This production process is an elegant solution for micro-fluidic devices where micro-channels stay free of adhesive without the need for alignment. With these methods the adhesive can be coated as a thin layer (typically on the order of several microns) with very good uniformity over large areas. Commercially available adhesive tapes offer another solution, which can be easily laminated onto the microfluidic chips either in the form of double-side-adhesive tapes or pressure-sensitive-tapes. By using this process, the tape covers the top of microfluidic channels and can alter chemical or physical parameters of the channels, which can then influence the fluidic behavior or biological function of the device. Due to the availability of a variety of different tapes, however, such influences can be addressed and eliminated in many applications.

Summary

Micro- and nanotechnology combined with biotechnology has the potential to revolutionize many areas of healthcare, agriculture and industrial manufacturing. The market for miniaturized bio-devices is rapidly growing with technologies becoming increasingly complex. For successful translation of these technologies into new products, the availability of fabrication tools is key. Today’s NIL equipment offers a well suited solution, where complexity in design does not necessarily add manufacturing cost. Together with sealing and bonding processes that are well aligned with these structuring techniques, limitations of current fabrication methods can be overcome to enable the production for next-generation biotechnology devices.

Further reading

T. Glinsner and G. Kreindl, “Nanoimprint Lithography,” in Lithography, M. Wang, Ed. InTech, 2010.
T. Glinsner, T. Veres, G. Kreindl, E. Roy, K. Morton, T. Wieser,
C. Thanner, D. Treiblmayr, R. Miller, and P. Lindner, “Fully automated hot embossing processes utilizing high resolution working stamps,” Microelectron. Eng., vol. 87, no. 5–8, pp. 1037–1040, May 2010.
G. Kreindl, T. Glinsner, and R. Miller, “Next-generation lithography: Making a good impression,” Nat. Photonics, vol. 4, no. 1, pp. 27–28, Jan. 2010.

An overview of liquid-to-liquid cooling systems and their operating principles

BY MARKO NIEMANN, Regional Sales Director, Laird Engineered Thermal Systems, Cologne, Germany

Cooling and temperature control systems are used throughout semiconductor fabrication facilities. In fabrication facilities both large and small, hundreds to thousands of cooling systems are installed and operate continuously. The processes employed are usually setup as copy-exact, which means the process systems are developed and transferred from the OEM of the process tool. These crtitical production tools used in a semiconductor fabrication facilities are required to be reliable and easy to service to deliver minimum downtime. The same is required of the cooling systems that support them. Usually the cooling systems employed have a water- cooled evaporator instead of an air-cooled evaporator. A liquid-liquid unit is quieter than a liquid to air unit because a fan is not required. Even more important, the heat can be rejected by available general facility cooling water and the heat is not rejected into the air temperature conditioned environment. These cooling systems can be placed near the tool, hidden in a false floor or on the lower level in a sub-floor. Cooling systems are built to meet SEMI S2 or F47 standards. OEM customers vary in their demand according to their unique requirements, but compliance is mandatory and sometimes OEM customers ask to get certifications for SEMI S2 or F47, which includes for example seismic “protections.” In these fabrication facilities a variety of liquid cooling systems are used including: compressor and thermoelectric based recirculating chillers.

Cooling systems

Liquid cooling systems are required to:

  • Protect the tool process against chemical reaction by avoiding an unknown Wetted-Parts-Material-Mix
  • Achieve a stable temperature, independent from facility water temperatures that can change
  • Achieve a temperature below or above the facility water temperature
  • Solve different temperature or fluid requirements at one tool with a multi-loop liquid cooling system

In semiconductor fabrication facilities, the required temperature control range varies from -80°C to +150°C. For the majority of applications, only one stable temperature set point is required. In the final chip test environment however, temperatures are required to vary in order to stress the chip. Here different temperature set points need to be reached with a single thermal management system. Due to the high-precision processes, tool manufacturers demand a very stable temperature environment. Typical of these requirements are +/-0.1K stability (e.g. for etching) to ±0.001K (e.g. for lithography) while cooling capacities can be up to several kilowatts.

In semiconductor fabrication facilities, custom multi- stage compressor based chillers are used to support cooling for very low temperature requirements. Most standard chillers utilized need some form of modification to meet semiconductor process facility requirements and may even require a water-cooled condenser. Some of the installation base also uses thermoelectric (19” rack) cooling systems, i.e. for etch applications, instead of compressor-based systems.

The cooling capacity demands and the range over which the system operates varies from a couple of hundred Watts (thermoelectric chiller and compressor based systems) to hundreds of Kilowatts (liquid-to-liquid cooling systems). The majority of the installed base uses liquid-to-liquid cooling systems that operate close to ambient and are based on a fluid-to-fluid heat-exchange principle.

The cooling systems utilize facility water to prevent heat dissipation of the cooling unit from warming the cleanroom and destabilizing the process tool’s thermal management system. These liquid-to-liquid systems keep the air quality level high by avoiding dust up introduced from the airflow of an air-to-air thermal management system. This consideration is independent of the location of the thermal management system. Due to the cyclic nature of the market, product requirements change and time to market is crucial. The cooling system solution developed is usually a custom product with a unique approach and design specific to the OEM.

Technical requirements

Cooling systems are often placed in the sub-fab, which means they are located one or two floors below the tool they are connected to. For cooling systems that use water as coolant, the height between the tool and the cooling system cannot exceed 10 meters, otherwise the height difference can cause the water to boil as the pressure is lower than the vapor pressure of water.
If the cooling system is placed at a lower level, the coolant circuit can function as a closed loop to the atmosphere. In this case, the cooling unit needs to incorporate a closed pressurized reservoir (7 PSI pressure cap) to minimize over flow conditions. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap (FIGURE 1).

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

A standpipe reservoir introduces additional fluid to the liquid circuit as required, whereas a flow-through reservoir continuously exchange fluid. It is important to know that the pump simply needs to overcome the height and pressure difference one-time during start-up in a closed loop system, as the supply and return lines will equilibrate given that they have the same length and diameter.

Material compatibility

In the semiconductor process environment, copper and brass are materials with limited compatibility due to their susceptibility to galvanic corrosion. Wetted parts, which come in direct contact with the medium (liquid), are typically made of stainless steel. These parts range from the complete plumbing circuit of the cooling unit to the process loop. Stainless steel is usually used in the process loop due its resistance to galvanic corrosion or because a special fluid is used that is not compatible with PVC, copper, and brass etc. When stainless steel is required, the heat exchanger, valves and the pumps will require special consideration. Occasionally, stainless steel may require additional passivation or a limited subset of stainless steel materials may be used.

If copper or brass is used to accomodate cost considerations, the material needs to be insulated to minimize the thermal impact on the system from outside thermal sources. Special particle free insulation may be required in this instance.

Special fluids used in the semiconductor environment include: di-electric fluids (Galden, 3M Novec), which are non-conductive. Special hoses and sealings need to be used for these fluids and special attention to handling is also required. These coolants run in a closed loop as the fluid vapor pressure is relatively low compared to water.

The use of de-ionized water is common. Copper or brass can be run up to 3 MOhm-cm resistivity if the set point temperature does not exceed 30°C for extended periods of time. However to ensure long lifetimes and for higher resistivity demands, the cooling system should be equipped with a nickel brazed or complete passivated stainless steel evaporator/heat-exchanger. The pumps should be stainless steel and all component parts in contact with the fluid should be made of passivated stainless steel to prevent corrosion. This is referred to as high-purity plumbing. In addition, a DI cartridge can be equipped with an indicator light or regulated through the cooling system and the DI level will be constantly measured and monitored keeping to a preset resistivity. The DI cartridge filters the ions out of the fluid and needs to be replaced to ensure its effectiveness.

Valves

If the unit is placed below the fabrication floor, an anti- siphoning package can be used to avoid backflow of the fluid and prevent overflowing the unit in event the pump stops. The anti-siphoning package consists of a one-way check valve in the supply line and normally open solenoid valves triggered by the unit in the return line. The solenoid valve would close in case the pump stops and the one-way check valve allows for the flow in only one direction. Instead of a one-way check valve, another solenoid valve can be used, though this depends on the flow rate and size (FIGURE 2).

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

For a process facility, constant monitoring and control of the facility process water is required and modulating solenoid valves from Siemens or Bellimo need to be used. The valve diameter and actuating motor have to be sized correctly to achieve stable temperatures and trigger the correct switching cycles. Assuring this means the inclusion of a long- lasting actuator and facility water flowing through an acceptable pressure drop from the facility water supply and return. Sometimes three-way mixing valves are used. This allows for continuous flow into the facility water loop and adds cooling for the heat exchanger of the thermal management system when required. The constant flow back to the facility water loop avoids a water hammer in cases where it would close and reopen when cooling is required. Flow requirements can go be as high as hundreds of liters per minute.

Space consideration

Cleanroom costs can be up to $60,000 /m2, therefore the chiller footprint is important and can have a costly impact. Semiconductor cooling systems should be stackable (stacked high) and preferable narrow to maximize space and minimize their impact on costs. Therefore the design of a cooling system’s footprint needs to be closely examined. The system should also be located where it is easy to access from two sides. Routine maintenance on cooling systems is required to exchange components such as pumps, motors, valves and fans to maximize system uptime.

SEMI requirements

For a completed tool, OEMs require a SEMI S2 certification and sometimes a Semi F-47 certification in areas with high earthquake probability. As the SEMI S2 certification requires a high amount of documentation, subsystems like a cooling unit will finally be integrated into the tool. Most of the time it is sufficient to meet the intent of SEMI S2 and the OEM will do a full certification of the final tool with all sincorporated subsystems in their NRTL laboratory. Below are some items to consider when designing a cooling unit to meet SEMI S2 and F-47 standards.

SEMI S2:

  • Drip tray must be large enough to hold 110% of the volume of the largest container in the cooling product
  • EMO button and/or EMO connection
  • Seismic brackets, seismic tie downs for standalone units
  • A specific power connection setup depending on the power consumption

F-47:

  • Continue to run during a power drop for a given time and fixed reduction of power

These requirements vary from customer to customer, but to some extent the certification is known to the manufacturer of the system.

If the unit is not placed below the fabrication facility flooring, the cooling system will instead be placed in the cleanroom or a grey room. Again, requirements here can vary drastically from customer to customer. If the cooling system, sub-assembly or any component is required to be in the cleanroom, then the entire assembly including each component must be as clean as possible. This requires the entire manufacturing process to have a high level of attention to cleanliness. Debris, dust, burrs or chips occurring at every process step need to be examined and removed ideally after every fabrication step. The industry is quite sensitive to this.

After the final assembly, the cooling unit needs to go through a manual check with UV-light and wipe down for final cleaning with gloves. The unit is then double bagged and each bag needs to be labeled appropriately. There are suppliers who specialize in cleaning, to semicon- ductor standards, and this can be subcontracted. Since it contributes to the cost and lead-time, the level of detail used requires scrutiny.

Service

Selling a cooling unit into the semiconductor market requires long-term servicing agreements in the contract. If a product is qualified in one facility other facilities can take over the setup as a copy exact requirement and use the existing cooling solution. For this after-market service and support, full understanding of the end users demands is critical. Service and support needs to responsive. In the event a tool unexpectedly goes down, immediate support is required or the OEM can lose millions of dollars in revenue.

Once the tool is installed service needs to be done on-site on the same day of failure, as large cooling systems cannot be replaced easily or shipped back to manufacturer for repair. OEMs have moved away from purchasing redundant cooling systems as their processes are getting leaner and expenses are reviewed more closely. This puts the contractual emphasis on service and a global service infrastructure.

Ideally the manufacturer is aware of the service demands and support strategy of their customers. Systems today are designed to minimize the downtime and make use of hot swappable parts, such as pumps on rails or modular exchange of complete assemblies, including electrical control boxes.

Conclusion

A semiconductor fabrication facility’s unique environment makes designing and building a liquid based cooling system one of the most challenging environments. Careful consideration is required not only for component selection, but also on the overall liquid cooling system unit and its integration with a semiconductor tool. Challenges designers face include the type of heat transfer mechanism utilized on the control and heat dissipation sides, material compat- ibility, valve control, cleanliness, space optimization, semi compliance and serviceability. These are all areas in need of attention to detail to properly ensure an optimized total cost of ownership.

GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry’s first multi-node FD-SOI roadmap. Building on the success of its 22FDX offering, the company’s next-generation 12FDX platform is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

As the world becomes more and more integrated through billions of connected devices, many emerging applications demand a new approach to semiconductor innovation. The chips that make these applications possible are evolving into mini-systems, with increased integration of intelligent components including wireless connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption. GLOBALFOUNDRIES’ new 12FDX technology is specifically architected to deliver these unprecedented levels of system integration, design flexibility, and power scaling.

12FDX sets a new standard for system integration, providing an optimized platform for combining radio frequency (RF), analog, embedded memory, and advanced logic onto a single chip. The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate energy efficiency.

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

GLOBALFOUNDRIES’ new 12FDX technology is built on a 12nm fully-depleted silicon-on-insulator (FD-SOI) platform, enabling the performance of 10nm FinFET with better power consumption and lower cost than 16nm FinFET. The platform offers a full node of scaling benefit, delivering a 15 percent performance boost over today’s FinFET technologies and as much as 50 percent lower power consumption.

“Chip manufacturing is no longer one-shrink-fits-all. While FinFET is the technology of choice for the highest-performance products, the industry roadmap is less clear for many cost-sensitive mobile and IoT products, which require the lowest possible power while still delivering adequate clock speeds,” said Linley Gwennap, founder and principal analyst of the Linley Group. “GLOBALFOUNDRIES’ 22FDX and 12FDX technologies are well positioned to fill this gap by offering an alternative migration path for advanced node designs, particularly those seeking to reduce power without increasing die cost. Today, GLOBALFOUNDRIES is the only purveyor of FD-SOI at 22nm and below, giving it a clear differentiation.”

“When 22FDX first came out from GLOBALFOUNDRIES, I saw some game-changing features. The real-time tradeoffs in power and performance could not be ignored by those needing to differentiate their designs,” said G. Dan Hutcheson, chairman and CEO of VLSI Research. “Now with its new 12FDX offering, GLOBALFOUNDRIES is showing a clear commitment to delivering a roadmap for this technology — especially for IoT and Automotive, which are the most disruptive forces in the market today. GLOBALFOUNDRIES’ FD-SOI technologies will be a critical enabler of this disruption.”

“FD-SOI technology can provide real-time trade-offs in power, performance and cost for those needing to differentiate their designs,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ new 12FDX offering delivers the industry’s first FD-SOI roadmap that brings the lowest cost migration path for advanced node design, enabling tomorrow’s connected systems for Intelligent Clients, 5G, AR/VR, Automotive markets.”

GLOBALFOUNDRIES Fab 1 in Dresden, Germany is currently putting the conditions in place to enable the site’s 12FDX development activities and subsequent manufacturing. Customer product tape-outs are expected to begin in the first half of 2019.

“We are excited about the GLOBALFOUNDRIES 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”

“NXP’s next generation of i.MX multimedia applications processors are leveraging the benefits of FD-SOI to achieve both leadership in power efficiency and scaling performance-on-demand for automotive, industrial and consumer applications,” said Ron Martino, vice president, i.MX applications processor product line at NXP Semiconductors. “GLOBALFOUNDRIES’ 12FDX technology is a great addition to the industry because it provides a next generation node for FD-SOI that will further extend planar device capability to deliver lower risk, wider dynamic range, and compelling cost-performance for smart, connected and secure systems of tomorrow.”

“As one of the first movers of design for FD-SOI, VeriSilicon leverages its Silicon Platform as a Service (SiPaaS) together with experience in delivering best-in-class IPs and design services for SoCs,” said Wayne Dai, president and CEO of VeriSilicon. “The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments. We look forward to extending our collaboration with GLOBALFOUNDRIES on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market.”

“12FDX development will deliver another breakthrough in power, performance, and intelligent scaling as 12nm is best for double patterning and delivers best system performance and power at the lowest process complexity,” said Marie Semeria, CEO of Leti, an institute of CEA Tech. “We are pleased to see the results of the collaboration between the Leti teams and GLOBALFOUNDRIES in the U.S. and Germany extending the roadmap for FD-SOI technology, which will become the best platform for full system on chip integration of connected devices.”

“We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering. Now this new 12FDX offering will further expand FD-SOI market adoption,” said Paul Boudre, Soitec CEO. “At Soitec, we are fully prepared to support GLOBALFOUNDRIES with high volumes, high quality FD-SOI substrates from 22nm to 12nm. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”

By Christian G. Dieseldorff, Industry Research & Statistics Group at SEMI (September 6, 2016)

SEMI’s Industry Research and Statistics group has published its August update of the World Fab Forecast report. The report has served the industry for 24 years, observing and analyzing spending, capacity, and technology changes for all front-end facilities worldwide, from high-volume to R&D fabs.  SEMI’s latest data show increasing equipment spending, reaching 4.1 percent YOY in 2016 and 10.6 percent in 2017. Figure 1 (below) shows a forecast of  -2 percent decline from 2H2015 to 1H2016 and an 18 percent increase from 1H2016 to. 2H2016.

Figure 1: Fab Equipment Spending by Quarter

Figure 1: Fab Equipment Spending by Quarter

The largest growth drivers for the industry are mobile devices (including devices using SSDs), automotive, and soon anticipated to be IoT, with these applications, in many cases, requiring 3D NAND and Logic 10nm/7nm.

The SEMI report indicates that the two industry segments leading to the biggest increase in 2H16 are Foundry (29 percent) and Memory (21 percent).  Growth in Memory is driven by a significant increase in 3D NAND spending in 2016. Comparing 2016 to 2017, Foundry growth remains quite steady, with a 14 percent increase in 2016 and 13 percent in 2017.

Companies like Samsung, Micron, Flash Alliance, Intel, and SK Hynix drive Memory growth with 3D NAND to an astounding 152 percent increase in 2016 and 29 percent in 2017. However, utilization of all this equipment is still low in 2016 but is expected to increase in 2017.

Looking at other product segments, DRAM equipment spending is expected to decline by 31 percent in 2016 and then recover slightly with 2 percent growth in 2017. Power devices also show strong growth with 25 percent in 2016 and 16 percent in 2017. The Analog segment will slump by -15 percent in 2016 but increase by 20 percent in 2017. Similarly, MPU will drop -20 percent in 2016 and then is expected to increase by 48 percent in 2017.

Comparing spending by region in 2016, SE Asia shows the largest growth, with 157 percent in 2016, driven mainly by 3D NAND (see Figure 2).

China, in third place for overall spending, shows 64 percent growth for 2016 primarily due to 3D NAND by non-Chinese companies, closely followed by Foundry companies. Although the largest spenders in China currently are overseas device companies, China-based chipmakers are starting to pick up investment activity.

Figure 2: Fab Equipment Spending by Region

Figure 2: Fab Equipment Spending by Region

By contrast, the largest growth rate in 2017 is in Europe/Mideast with about 60 percent which is mainly due to ramping of 10nm facilities. Korea is in second place for total spending, mainly driven by Samsung’s investment in DRAM and Flash. Japan in third place driven by Flash Alliance (3D NAND).

The World Fab Forecast report provides more detailed information by company and fab for construction spending, equipment spending and capacities by region and product type.  Since the last publication in May 2016, the SEMI research team has made over 330 changes to 300 facilities/lines. This includes 27 new records and 18 records closed.

For information about semiconductor manufacturing for the remainder of 2016 and in 2017, and for details about capex for construction projects, fab equipping, technology levels, and products, order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 82 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.  Using a bottoms-up approach methodology, the SEMI Fab Forecast provides high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab.

The SEMI Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data tracks only new equipment for fabs and test and assembly and packaging houses.  The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment. Also check out the Opto/LED Fab Forecast. Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

Global growth in the number of “things” connected to the Internet continues to significantly outpace the addition of human users to the World Wide Web. New connections to the “Internet of Things” are now increasing by more than 6x the number of people being added to the “Internet of Humans” each year. Despite the increasing number of connections, IC Insights has trimmed back its semiconductor forecast for Internet of Things system functions over the next four years by about $1.9 billion, mostly because of lower sales projections for connected cities applications (such as smart electric meters and infrastructure). Total IoT semiconductor sales are still expected to rise 19% in 2016 to $18.4 billion, as shown in Figure 1, but the updated forecast first presented in the Update to the 2016 IC Market Drivers Report reduces the market’s compound annual growth rate between 2014 and 2019 to 19.9% compared to the original CAGR of 21.1%. Semiconductor sales for IoT system functions are now expected to reach $29.6 billion in 2019 versus the previous projection of $31.1 billion in the final year of the forecast.

Figure 1

Figure 1

The most significant changes in the new outlook are that semiconductor revenues for connected cities applications are projected to grow by a CAGR of 12.9% between 2014 and 2019 (down from 15.5% in the original forecast) while the connected vehicles segment is expected to rise by a CAGR of 36.7% (up from 31.2% in the previous projection). IoT semiconductor sales for connected cities are now forecast to reach $15.7 billion in 2019 while the chip market for connected vehicle functions is expected to be $1.7 billion in 2019, up from the previous forecast of $1.4 billion.

For 2016, revenues of IoT semiconductors used in connected cities applications are expected to rise 15% to about $11.4 billion while the connected vehicle category is projected to climb 66% to $787 million this year.

Sales of IoT semiconductors for wearable systems have also increased slightly in the forecast period compared to the original projection.  Sales of semiconductors for wearable IoT systems are now expected to grow 22% to about $2.2 billion in 2016 after surging 421% in 2015 to nearly $1.8 billion following Apple’s entry into the smartwatch market in 2Q15.  The semiconductor market for wearable IoT applications is expected to be nearly $3.9 billion in 2019.  Meanwhile, the forecast for IoT semiconductors in connected homes and the Industrial Internet categories remains unchanged.  The connected homes segment is still expected to grow 26% in 2016 to about $545 million, and the Industrial Internet chip market is forecast to increase 22% to nearly $3.5 billion.  The semiconductor forecast for IoT connections in the Industrial Internet is still expected to grow by a CAGR of 25.7% to nearly $7.3 billion in 2019 from $2.3 billion in 2014.

Driven by rising demand for thinner wafers and stronger die, dicing technology is evolving.

“Reaching more than US$100 million in 2015, the dicing equipment market will double by 2020-2021,” announced Yole Développement (Yole) (Source: Thin Wafer Processing & Dicing Equipment Market report, Yole Développement, May 2016). Yet at the same time thin wafers are creating new challenges of significant interest in the dicing equipment industry such as die breakage, chipping, low die strength, handling issues and dicing damage.

Yole’s Technology & Market Analyst, Amandine Pizzagalli, is pleased to give her vision of the dicing technologies, market forecast and competitive landscape during the webcast “Plasma Dicing for Next Generation Ultra Small and Ultra Thin Die” organized by SPTS Technologies, an Orbotech company. This webcast will take place on September 14. To register click PLASMA DICING.

Today, the most common dicing technology applied across memory, logic, MEMS, RFID and power devices is mechanical dicing, also known as blade dicing. 

“Blade dicing represents more than 80% of the dicing brand equipment business in terms of dicing tools and stealth dicing 20%,” explained Amandine Pizzagalli from Yole.

However, companies are showing a growing need for thinner wafers and smaller devices in general and Yole sees a trend towards adopting alternative dicing technologies. These include stealth dicing and plasma dicing based on deep reactive ion etching technology. Yole’s analysts details the plasma dicing market per application:

  • Memory specifically has predominantly relied on a combination of blade and laser dicing applied together to singulate complex stacks. Using only blade dicing on top layers leads to delamination issues because of the high metal density. However, it’s difficult to safely singulate 50 µm thin wafers even with laser dicing and this could allow plasma dicing to enter this area. “Even if the philosophy of the designers is changing, memories manufacturers are still the most conservative”, details Amandine from Yole.
  • In MEMS devices blade dicing is largely applied for singulating the ASIC, capping and MEMS sensors. However, exposure to water from the process can contaminate some sensors and destroy sensitive MEMS structures, example in MEMS microphones. In such cases, stealth dicing has been already adopted in large volume production. Plasma dicing has also been adopted in low volume production today for MEMS devices.
  • In parallel, the RFID is a growing market segment: plasma dicing is already in production but the adoption rate is still small. According to Yole’s analysts, a fast growth for plasma dicing especially for RFID devices is expected. Indeed plasma dicing has the ability to reduce die fragility, boost die strength, increase the number of chips per wafer and thus reduce Cost Of Ownership of equipment overall.

“As die sizes continue to shrink, singulation by plasma etching offers considerable benefits for die quality and strength as compared to traditional dicing solutions,” stated Richard Barnett, Etch Product Manager at SPTS Technologies, an Orbotech company. And he adds: “Ultra-small and ultra-thin devices like RFID chips or fragile devices like MEMS are more susceptible to damage from the vibration and chipping caused by mechanical saws, or from the heat caused by lasers.”

Under its new thin wafer & dicing equipment market report, the “More than Moore” market research and strategy consulting company is analyzing the competitive landscape: the current market is today controlled by DISCO and Accretech, which today claim market shares of almost 80% focused on blade dicing and stealth dicing, respectively:

  • DISCO leads the blade dicing market and offers a large product portfolio including stealth dicing and laser ablation. They have also a partnership with Plasma-Therm which gives them access to the complete range of dicing technologies: Yole’s analysts had the opportunity to discuss the market, its evolution and challenges with Abdul Lateef, CEO, and Thierry Lazerand, Business Development Director, of Plasma-Therm. To discover this interview, click Plasma-Therm solution.
  • Accretech leads the stealth dicing market offering.
  • ASM Pacific is a strong player in laser ablation, especially because their process does not lead to contamination issues compared to standard laser ablation technology.

During SPTS Technologies webcast, Amandine Pizzagalli will describe the today’s competitive landscape of the key dicing technologies across MEMS devices, power devices, CMOS image sensors, and RFID devices, highlighting her major findings on the evolution and trends of the dicing technologies.

These results are part of Yole’s report entitled Thin Wafer Processing & Dicing Equipment Market. Under this analysis, Yole presents a comprehensive overview of the key dicing technologies benchmarks in terms of feature requirements. This report includes insights into the number of tools, broken down by wafer size, by application and by dicing technology… A full description of the report is available on i-micronews.com, manufacturing reports section.

In parallel, SPTS Technologies speaker, Richard Barnett also proposes an overview of the latest advances in plasma dicing. During his talk, Richard will highlight the latest data illustrating how processing routes affect die strength, share experiences with different types of tapes and other die features such as solder balls. SPTS Technologies will share details of the latest equipment which is now available for plasma dicing wafers up to 300mm (on 400mm tape frames) for full production applications.

Technavio analysts forecast the global radio frequency (RF) IC market to grow at a CAGR of nearly 12% during the forecast period, according to their latest report.

The research study covers the present scenario and growth prospects of the global RF IC market for 2016-2020. To calculate the market size, the report considers revenue generated from the shipment of RF ICs globally.

Asia-Pacific (APAC) is expected to be the major demand generating region and is expected to be the major contributor to the market during the forecast period. This is because of the growing demand for RF IC’s in the consumer electronics segment and increasing need for logic and multipoint control units (MCUs) in the automotive segment in the region. The presence of major buyers such as Samsung Electronics, LG Electronics, and Toyota Motor led to the increasing consumption of RF ICs in this region.

Increased demand for electronics from countries such as China and India drives the market in APAC. China’s massive demand for electronics exceeds the production levels in the country. Despite the phenomenal growth, only a small share of semiconductors’ demand in China is actually produced domestically.

Technavio hardware and semiconductor analysts highlight the following four factors that are contributing to the growth of the global RF IC market:

  • Deployment of next-generation LTE wireless networks
  • Advent of carrier aggregation
  • Use of new materials for manufacture of RF devices
  • Growing traction of RF technology for remotes

Deployment of next-generation LTE wireless networks

The increase in data consumption has resulted in the adoption of next-generation LTE networks such as 3G and 4G. The growing consumption has resulted in the growth of commercial networks, making LTE the fastest developing mobile technology. Though specific bands have been designated for LTE, they vary from carrier to carrier.

Sunil Kumar Singh, one of the lead embedded systems research analysts at Technavio, says, “LTE-based computing devices allow consumers to upload and download music and photographs, play games online with minimum signal interference, and watch online TV shows uninterrupted. This has created an opportunity for manufacturers of transceiver chips to offer solutions that address the consumer needs for faster and smoother access to mobile data.”

Advent of carrier aggregation

Carrier aggregation results in an increase in RF content in smartphones and tablets. Carrier aggregation combines a wide range of the available spectrum at the same time to increase download and upload speeds. Though carrier aggregation is not a widespread concept currently, it has already been implemented in South Korea.

“The RF signals are transmitted and received using transceiver chips, which are integrated into RF modules as a component. The advent of carrier aggregation will compel transceiver chip manufacturers to improve and upgrade their offerings according to the requirements of the OEMs,” adds Sunil.

Use of new materials for manufacture of RF devices

The manufacture of RF devices such as power amplifiers incurs huge costs for vendors because of the high cost of raw materials. This has resulted in vendors searching for new materials that can reduce the expenditure incurred in the manufacturing process of RF devices. The development of new materials such as GaAs and indium phosphide (InP) will ramp up the production of RF power amplifiers. GaAs-RF power amplifiers use high saturated electron velocity and electron mobility to function, especially at high frequencies.

The new materials display a superior level of integration with other electronic components such as switches being fabricated in silicon on sapphire or other silicon on insulator processes. While, SAW filters and duplexers are being fabricated with piezo-effective materials such as lithium tantalate and lithium niobate. Therefore, companies such as Murata and TriQuint are trying to use cost-effective and superior-performing materials to manufacture RF power amplifiers.

Growing traction of RF technology for remotes

RF remotes accounted for 13% of the global remote market in 2015 and are expected to witness increased adoption during the forecast period, accounting for a little more than 20% by 2020. One of the major factors contributing to it is the decrease in the development cost of RF technology-based products. Moreover, RF remotes are expected to gain traction in the market because of advantages compared with IR remotes. RF remotes have lower power consumption, longer range, and do not need line-of-sight to control the device.

The RF remotes segment will witness high demand considering the demand for advanced TVs such as 3D smart TVs and 4k UHD smart TVs. Consumers demand visually aesthetic TVs that deliver a unique experience in terms of picture quality, viewing angle, and internet connectivity. With such advanced features, remote manufacturers are also manufacturing advanced and sophisticated RF remotes. RF has benefits such as out-of-line and sight communication and control, two-way communication, incorporation of gesture recognition and voice controls, and enhanced bandwidth compared to IR.

The key vendors are:

  • Infineon Technologies
  • Qualcomm
  • Avago Technologies
  • Qorvo
  • Skywork Solutions
  • NXP Semiconductors
  • STMicroelectronics
  • Renesas Electronics

By Paul Trio, SEMI

Growing Demands, Constraints Continue

For many years, the ATE industry has been challenged with controlling the cost of both production and development test by implementing innovative approaches and employing clever strategies (e.g., multi-site test implementation, DFT, etc.) to make “ends” meet, so to speak.  This predicament has been a perpetual struggle, but the industry manages to soldier on. However, the demands for next-generation technology continues to introduce new challenges to the ATE realm. For example, shorter production ramp-up and higher yields result in the increasing demand for test data and information in real-time. Not only is there a need for more data quickly, but also for better test data quality. Adding to the complexity is that existing formats are typically slow/limited or even proprietary. As a result, the equipment manufacturers are burdened with supporting multiple proprietary data transport and communications systems.  This requires the use of valuable engineering resources to develop and maintain these multiple proprietary systems, whereas a single standard system would open up resources to develop new ATE features and products.

ATE Industry Alliance

These ATE industry problems are being addressed by CAST – Collaborative Alliance for Semiconductor Test – a SEMI Special Interest Group (SIG). SEMI SIGs provide a forum that fosters discussion and aligns stakeholders on industry-critical issues. CAST was formed in 2008 by semiconductor device makers and test industry suppliers to engage in and resolve common industry issues related to higher test equipment utilization, lower costs, and greater return on investment. In 2009, CAST became a SEMI Special Interest Group. Its charter includes fostering pre-competitive collaboration as well as developing and promoting standards that enable industry productivity improvements.

Figure 1 CAST Industry Stakeholders

Figure 1 CAST Industry Stakeholders

CAST members include a range of semiconductor industry leaders, ranging from automated test equipment (ATE) companies to integrated device manufacturers (IDMs) to fabless manufacturers to outsourced semiconductor assembly and test (OSAT) companies. Companies participating in CAST include: Advantest, ASE, Galaxy Semiconductor, GLOBALFOUNDRIES, Infineon, Maxim, Nvidia, Optimal+, PDF Solutions, Qualcomm, Roos Instruments, STMicroelectronics, Teradyne, Tesec, Texas Instruments, Xcerra.

CAST Structure

The CAST organization is primarily comprised of a steering committee and two working groups. The CAST Steering Committee meets quarterly to review progress on programs and identify new solutions needed by the industry. The Steering Committee is comprised of decision-makers and strategic thinkers of the participating companies mentioned above.

The current CAST working groups that are addressing data transport and control are the Rich Interactive Test Database (RITdb) WG and the Tester Event Messaging for Semiconductor (TEMS) WG.

Figure 2 SEMI CAST Working Group Focus Areas

Figure 2 SEMI CAST Working Group Focus Areas

Enabling Adaptive Test through Next Generation Standard Test Data Format

While Standard Test Data Format (STDF) is widely used in the semiconductor industry today, its current specification does not directly support the new use models in today’s test environment, such as real time or pseudo real time queries, adaptive test and streaming access. The STDF V4 record format is not extendible and the specification itself can be imprecise, such that it tends to result in many interpretations. These limitations become apparent when there is a need for more efficient and flexible format to manage “big test data.”

The RITdb group has been working on the next generation format following STDF with more flexibility in data types as well as allowing support for adaptive test. The WG aims to provide a standards-driven data environment for semiconductor test including simple standards-based data capture, transport and relationship model for eTest, probe, and final test data. Their work also aims to support equipment configuration management and operational performance data. RITdb is a SQLite database with one table, independent from an operating system. Key value store optimized for test data.

Figure 3 STDF to RITdb: PTR

Figure 3 STDF to RITdb: PTR

To date, the group has defined the mapping from STDF v4 to RITdb. A translator developed by the RITdb is also available. The overall schema has already been defined and many file translations have already been tested. Work by the RITdb group will ultimately be developed into SEMI Standards. Therefore, the group has been working on the (SEMI Standard) spec which will be in MS Word, while the database itself will be in a different format. There will be a spec editor that will help ensure the spec is used correctly. The group also plans to expand the spec beyond probe and final test. Meanwhile, the group is working on experiments related to streaming RITdb as well as work on using different extensions (e.g., tester log, streaming). Additional work will be needed on probe maps as well as on doing test cases (i.e., be able to run verifiers to validate the spec).

Improving Test Yield through Common ATE Data Communication Interface

Semiconductor test operations involved in ATE today continues to see a surging demand for data for real-time data analysis and real-time ATE input and control of the test flow to improve test yield, throughput, efficiency, and product quality.  At the same time, test equipment and test operations around the world utilize a diverse range of data formats, specifications, and interface requirements that create significant customer service and application engineering costs for ATE vendors, OSAT companies, IDM test operations, software providers, and handler equipment. A common ATE hardware and software communications interface would help reduce the cost, time and complexity of integrating ATE equipment into data-intensive test operations.

The TEMS WG was chartered to develop a standardized ATE data messaging system based on industry standard internet communication protocols between a Test Cell host and a server.  The standard will be limited to ATE data messaging, using RITdb entity types, where applicable, as well as the standard data format, and control requirements. It will have no impact on other test communication interfaces such as those involving handlers, probers, test instrumentation, and other systems covered by existing standards (e.g., SEMI E30, E4, E5, STDF, etc.).

The group will essentially develop a set of standards to define a vendor neutral way to collect test cell data. The primary spec defines the Model while a subordinate spec defines the Transport layer to maintain consistency with prior standards.

Figure 4 TEMS Focus Area

Figure 4 TEMS Focus Area

Similar to the RITdb activity, the TEMS group plans to transition its two working documents to the SEMI Standards space. As the group continues to fine-tune these documents while maintaining alignment with the RITdb WG, the preliminary SEMI Standards work (e.g., authorize formation of corresponding task force) is expected to occur by the end of the year.

Other ATE Challenges Looming

System Level Test (SLT) is an approach used to guarantee the performance of a product for a particular customer application. However, the term “System Level Test” (SLT) is frequently applied to both the testing of full systems as well as to the testing of chips to ensure their ultimate performance in target systems. This often leads to confusion.

For its 2016 workshop to be held in early November, CAST will address the topic of “Component SLT”, which is the set of application-specific functional tests that are performed prior to I.C. shipment to guarantee a chip’s quality and performance when it will be ultimately used in the final system.  It may also encompass incoming inspection of I.C. components by customers prior to assembly into systems.  Currently, component SLT tends to be implemented primarily on complex SoC devices using custom hardware and software.

Component SLT considerations:

  • Normally component SLT would be applied using a card or board based on the target system’s functional card or board — but with a socket where the IC component is temporarily placed while SLT tests are applied.
  • Component SLT is used by some chip vendors as an IC component test after conventional Final Test on ATE.
  • Potentially, component SLT could also be applied using a custom card within the ATE system that mimics system application tests.
  • Any level of standardization will ease the capital burden and operational flexibility at OSATs.
  • It will be a key requirement to be able to generate data from component SLT that can be shared backwards and forwards along the semiconductor supply chain for yield optimization and quality/reliability management.

Those looking to share their perspectives on component SLT and their vision for its future direction are invited to present at the CAST workshop. The community is particularly interested in opportunities to improve the Component SLT ​infrastructure or methods — that is, identify potential opportunities for CAST to drive improvements through pre-competitive collaboration.

Participating in SEMI CAST Special Interest Group

The SEMI CAST Special Interest Group is open to all SEMI Members. For more information or to join CAST, please contact Paul Trio at SEMI ([email protected]).