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BY ALLYN JACKSON, CyberOptics Corp., Minneapolis, MN

Key IC fabrication steps are sensitive to moisture in semiconductor wafer environments. As the technology node advances, the need for characterizing and minimizing the exposure to relative humidity (RH) has become critical in all 29nm geometry fabs and below. These RH control requirements create a need for a wireless wafer-like humidity sensor which simultaneously measures RH at several points across the wafer as well as throughout the entire IC manufacturing environment.

Challenges with current methods for characterizing N2 FOUPS

Current methods for characterizing N2 Purge FOUPs have problems. These methods are typically not real time, are time consuming, are hard to use and are not able to take RH measurements under production conditions therefore are not reflective of these conditions. In addition, wired (FIGURE 1) hand-held RH meters (FIGURE 2) and single trace hand-held meters are limited to one area and cannot move throughout the process environment. Other options are hand-made alternatives (FIGURE 3) such as a wafer with RH sensors simply taped on. Lastly, they are often limited without data files generated so conse- quently statistics and quality standards cannot be established.

FIGURE 1. FOUP with Wired RH Sensors Attached

FIGURE 1. FOUP with Wired RH Sensors Attached

FIGURE 2. Hand-held RH Meter with Single Trace RH Reading

FIGURE 2. Hand-held RH Meter with Single Trace RH Reading

FIGURE 3. Silicon Wafer With 4 RH Recording Sensors Taped on.

FIGURE 3. Silicon Wafer With 4 RH Recording Sensors Taped on.

RH environment test target and goals

The test at the customer involved putting an RH meter inside the FOUP pointing around slot 13. The goal was to repeat the RH meter profile for testing a FOUP on one loadport without the need to open the FOUP. Starting at 40% RH (cleanroom environment), the first step was to run high purity, high volumnet N2 pre-purge for 4-5 minute and then take the reading. The second step is to conduct a maintenance purge to 5% and measure the results in 5 locations across the wafer. The next step was to run a process purge to 20% and take sample readings across various locations. The goal of the testing it to test the efficiency of the N2 purge FOUP diffusers to ensure that uniform purge levels are maintained.

In response to the need for a reliable easy to use method of qualifying N2 and XCDA environments, the WaferSense® Auto Multi-Sensor (AMS) by CyberOptics (FIGURE 4) was developed. Wafer- Sense AMS is a wireless wafer-like device with five RH sensors to measure the RH profile across the entire wafer surface.

FIGURE 4. WaferSense® Auto Multi Sensor Measurement Device.

FIGURE 4. WaferSense® Auto Multi Sensor Measurement Device.

FIGURE 5. N2 Purge FOUP with 3 Inlet and one Outlet Ports.

FIGURE 5. N2 Purge FOUP with 3 Inlet and one Outlet Ports.

AMS is a complete and easy-to-use system which communicates wirelessly via Bluetooth to the MultiViewTM application (FIGURE 6) and moves like a normal wafer to all locations in the wafer process environment providing a true characterization of the N2 purge uniformity. Such previously hard to accomplish tasks such as characterizing purge FOUP diffuser uniformity and measuring actual RH percentages are now easily accomplished with AMS. (FIGURE 5) AMS is a true multi-functional device which also measures vibration and can be used for leveling to ensure proper wafer handling.

FIGURE 6. Profile of N2 Purge Using MultiViewTM Software to Displays RH Measurements in 4 Sensor Locations across the Wafer Surface.

FIGURE 6. Profile of N2 Purge Using MultiViewTM Software to Displays RH Measurements in 4 Sensor Locations across the Wafer Surface.

29nm geometry fabs and smaller require well controlled N2 and XCDA purge environments to prevent defects and yield loss. AMS300 simultaneously measures RH in real-time at five locations on the wafer while it transfers like a wafer to qualify N2 and XCDA environments. The AMS device significantly shortens the task of qualifying these environments. In addition, the AMS300 provides and vibration and leveling measurement capabilities to ensure proper wafer handling and reduced particles. The overall result for the fab is improved N2 purge environment uniformity which results in reduced defects and reduced labor costs.

Reducing reticle haze effects

193nm Immersion scanners are adversely affected by a phenomenon called “Reticle Haze” when proper measures are not taken to measure and control it. There are three areas that need to be controlled to reduce this haze effect on reticles, one of which is controlling RH. Reticle haze is accelerated when H2O is present. (FIGURE 7).

FIGURE 7. Reticle Haze Formation Accelerated with H2O

FIGURE 7. Reticle Haze Formation Accelerated with H2O

There is a key need for a measurement device that will eliminate the inefficiencies of the current methods.

Challenges with current methods for monitoring RH in reticle environments

There are several limitations with the current reticle environment RH measurement methods, for example, hand-held RH sensors (FIGURE 9) are inconvenient and they can compromise the reticle environment. Plus, many areas are inaccessible by hand-held RH sensors, in-situ RH sensors or benchtop type RH sensors. (FIGURE 8)

FIGURE 8. Benchtop RH Sensor

FIGURE 8. Benchtop RH Sensor

Figure 9: Wired In-Situ RH Sensor

Figure 9: Wired In-Situ RH Sensor

Additionally, the importance of particle, leveling, vibration and RH control has rarely been overlooked in reticle environment. However, the need to maximize both yields and tool uptimes in reticle mask environments requires best-in-class practices.

Whether for diagnostics, qualification or preventative maintenance, equipment engineers need to efficiently and effectively make measurements and adjustments to the tools. Legacy particle, vibration, leveling and RH measurement methods are typically cumbersome, non-representative, not real time, compromise the production environment and are costly with downtime required to take the tool offline for these tasks.

By contrast, best practice methods involve collecting and displaying data in real-time, speeding equipment alignment or set-up. Real-time data also speeds equipment diagnostic processes, saving valuable time and resources. Equipment engineers can also make the right adjustments consistently by using objective and reproducible data that enhances process uniformity.

The ReticleSense® AMSR (FIGURE 10) is an actual glass reticle that measures H2O in the reticle environment and is compatible with ASML, Canon and Nikon scanners. AMSR is used to travel throughout the entire reticle environment and measures RH. (FIGURE 11) It helps locate the sources of the H2O which results in increased reticle lifetime. Two additional measurement capabilities of the device include measuring X, Y and X vibration (FIGURE 12) and inclination. (FIGURE 13).

FIGURE 10. ReticleSense® Auto Multi Sensor Measurement Device.

FIGURE 10. ReticleSense® Auto Multi Sensor Measurement Device.

FIGURE 11. RH Measurement

FIGURE 11. RH Measurement

FIGURE 12. Vibration Measurement

FIGURE 12. Vibration Measurement

FIGURE 13. Leveling Measurement

FIGURE 13. Leveling Measurement

Conclusion

The AMSR travels the entire path of the reticle and can measure humidity in all locations. In immersion scanner environments, monitoring humidity is critical in reticle reducing haze. Equipment qualifications can be done faster as the same device also measures vibration and leveling. Controlling inclination, RH and vibration are all important factors in increasing yield and reducing downtime.

For RH measurements in N2 and XCDA reticle mask environments, the use of a real-time measurement device, the Auto Multi Sensor, delivers on three compelling bottom lines for the fab – saving time, saving expense and improving yields.

IHS Markit (Nasdaq: INFO) today released its annual 2015 revenue-share ranking of the top LED suppliers in backlighting, automotive, lighting and other applications.

According to the 2016 edition of the IHS Markit Packaged LED Report, Nichia led in both lighting and mobile applications for 2015, with 12.9 percent share of the total packaged LED market. Nichia was followed by Osram and Lumileds with a combined share of 14.7 percent.

“It’s not a surprise that Nichia led in more than one application,” said Alice Tao, senior analyst, LEDs and lighting for IHS Markit. “In 2015, Nichia overtook Cree, which led the lighting category in 2014. Nichia was also very strong in mobile phone LEDs, since the company is a major supplier for Apple’s iPhone.”

Samsung was the leading supplier in backlighting, which includes LEDs used in TVs, monitors, notebook PCs and tablet PCs. Nichia followed in second position and LG Innotek ranked third.

Osram has been the leading supplier of automotive LEDs for many years. Its market share was 35 percent in 2015 for LEDs used in the total automotive market and 40 percent for those used in the automotive exterior market. It also led in the “other” application, which includes LEDs used for industrial, medical, security, projection, signage and off-specification applications.

Leading packaged LEDs suppliers
(Millions of Dollars)  
   
Category

Leading supplier
Lighting

Nichia
Backlighting

Samsung
Mobile phone

Nichia
Automotive

Osram
Other

Osram

 

The IHS Markit Packaged LED Report provides detailed quantitative market sizes and supplier shares by application, region and product type. For more information about purchasing IHS Markit information, contact the sales department at [email protected].

New wafer processing technologies overcome FOWLP’s technical hurdles, paving the way for a new generation of ultra compact, high I/O electronic devices.

BY DAVID BUTLER, SPTS Technologies, an Orbotech company, Hereford, UK

Our ability to create ever-smaller electronic devices that maintain or surpass the performance of their physically larger predecessors – exemplified by today’s wearables, smartphones and tablets – is dictated by many factors that extend well beyond Moore’s Law, from the underlying embedded components to the ways in which they’re packaged together. With regard to the latter, fan-out wafer level packaging (FOWLP) is quickly emerging as the new die and wafer level packaging technique of choice, and is widely antici- pated to underpin the next generation of compact, high performance electronic devices.

Whereas with conventional flip-chip WLP schemes the I/O terminals are spread over the chip surface area, limiting the number of I/O connections, FOWLP embeds individual die in an epoxy mold compound (EMC) with space allocated between each die for additional I/O connection points, avoiding the use of more expensive silicon real estate to accommodate a higher I/O count. Redistribution layers (RDLs) are formed using physical vapor deposition (PVD) and subsequent electroplating and patterning to re-route I/O connections on the die to the mold compound regions on the periphery (FIGURE 1).

FIGURE 1. FOWLP process flow.

FIGURE 1. FOWLP process flow.

Leveraging FOWLP, semiconductor devices with thousands of I/O points can be seamlessly connected via finely-spaced lines as thin as two to five microns, maximizing interconnect density while enabling high bandwidth data transfer. Significant height and cost savings are achieved via the elimination of the substrate.

With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers and power management ICs in these mold wafers, thereby enabling the latest gener- ation of ultra-thin wearables and mobile wireless devices. With continued line and space reductions, FOWLP has the potential to accommodate higher performing devices including memory and application processors, positioning FOWLP to extend into new markets including automotive and medical applications and beyond.

Leading vendors implementing FOWLP today include Amkor, ASE, Freescale, NANIUM, STATS ChipPAC, and TSMC, with TSMC being the most high-profile vendor given its widely-reported contract win to produce A10 processors for Apple’s iPhone 7 – a deal said to be attrib- utable in part to TSMC’s mature FOWLP-based InFO technology.

According to a report entitled “FO WLP Forecast update 09/2015” published by research firm Yole Développement in September 2015, the launch of TSMC’s InFO format is expected to increase industry packaging revenues for FOWLP from $240M in 2015 to $2.4B in 2020. With a projected 54% CAGR, Yole expects FOWLP to be the fastest growing advanced packaging technology in the semiconductor industry.

Low heat, high speed processing

All fan-out wafers feature singulated die embedded in the EMC, with spin-on dielectrics surrounding the RDL. These materials present some unique challenges, including moisture absorption, excessive outgassing and a limited tolerance to elevated temperatures. If not dealt with properly, contamination at the metal deposition stage can compromise contact resistance.

Whereas conventional circuits built on silicon can withstand heat up to 400oC and can be degassed in under one minute, the EMC and dielectrics used in FOWLP have a heat tolerance closer to 120oC. Temperatures exceeding this low threshold can cause decompo- sition and excessive wafer warping. Degassing wafers at such low temperatures naturally takes a longer amount of time, and can drastically reduce the throughput of a conventional sputter system.

Multi-wafer degas (MWD) technology has emerged as a compelling solution to this problem, enabling up to 75 wafers to be degassed at 120oC in parallel before being individually transferred to subsequent pre-clean and sputter deposition, without breaking vacuum.

With this approach, wafers are dynamically pumped under clean, high vacuum conditions, with radiation heat transfer warming wafers directly to temperatures within the operating budget for packaging applications.

Each wafer can spend up to 30 minutes inside the MWD, but because they’re processed in parallel, a “dry” wafer is outputted for metal deposition every 60 to 90 seconds, at a rate of between 30 to 50 wafers per hour. This approach increases PVD system throughput by 2-3 times compared to a single wafer degas processing technology, and as materials emerge with even lower thermal budgets based on increased passivation thickness, longer degas times can be accommodated with no impact on throughput (FIGURE 2).

FIGURE 2. The Sigma fxP PVD system with multi-wafer degas module from Orbotech-SPTS.

FIGURE 2. The Sigma fxP PVD system with multi-wafer degas module from Orbotech-SPTS.

These benefits are not readily attainable, however, unless we can overcome the attendant warping challenges. Epoxy mold wafers can be warped after curing, and the size and shape of the warpage hinge on the different shapes, densities and placement of the embedded die. A FOWLP PVD system must therefore be able to minimize temperature-induced shape shifting, and accommodate wafers with up to a 10mm bow. The acceptable industry threshold for bowing is probably lower than 6mm, however, as it’s not easy to make uniformly thick conductors on a substrate exhibiting 6mm+ warpage.

Utmost integrity

After successful degas, but prior to metal deposition, the FO wafer is pre-cleaned in a plasma etch module. This facilitates the removal of trace oxide layers from the contacts, but due to the composition of the organic dielectric surrounding the contacts, will result in carbon build-upon the chamberwalls.This carbon does not adhere well to ceramic chamber surfaces, and if not carefully managed, can result in early particle failure.

New in-situ paste technologies allow these carbon deposits to better adhere to chamber surfaces during the pre-cleaning process, enabling preventative maintenance intervals that exceed 6,000 wafers. This approach can significantly improve productivity by reducing the frequency of dedicated wafer pastes, which typically require production to be paused every 10 to 20 wafers for chamber pasting when using conventional techniques.

The myriad benefits that FOWLP promises for the production of ultra compact, high I/O electronic devices far outweigh the aforementioned technical barriers to mainstream FOWLP adoption. With the ability to overcome the degassing, warping, and integrity challenges that can impede FOWLP implementations, electronics manufacturers can unlock the full potential of FOWLP while eliminating frictions affecting production speeds and yields.

Recent breakthroughs in materials engineering of low-resistance W barriers/liners and bulk fill are making it possible to extend W use to next-generation devices.

BY JONATHAN BAKKE, Applied Materials, Santa Clara, CA

Tungsten (W), with its low resistivity and minimal electro-migration, has long been used for a variety of applications in fabricating semiconductor devices. For instance, it is used for logic contact, local interconnect (LIC), and metal gate (MG) fill as well as DRAM buried word line and contact and 3D NAND MG and contact. Sustained scaling, however, is posing challenges to its continued use with conventional process flows. Interconnect dimensions have shrunk to the point at which contact resistance is becoming an obstacle to realizing optimum transistor performance; fill integrity degrades as aspect ratios and the degree of re-entrance increase, making it difficult to ensure high-quality metallization.

At earlier nodes, larger dimensions made W fill possible using conformal CVD deposition. Now, overhang around the tops of ultra-small openings or bowing from the interconnect etch open preclude the conformal process from completely filling features without voids, while center seams are an inevitable result of conformal deposition, even in the absence of voids. These attributes render extremely small features vulnerable to breach during CMP, causing high resistance or complete failure of an inter- connect. High feature densities and lack of via redundancy in advanced chip designs mean that a single void can cause complete device failure and significant yield loss.

Fortunately, recent breakthroughs in materials engineering of low-resistance W barriers/liners and bulk fill are overcoming these limitations and making it possible to extend W use to next-generation devices. The former lower resistance by simplifying fill film requirements and enlarging the volume available for W fill; the latter eliminates undesirable seams to create more robust structures.

Low-resistance liners

To date, high-resistivity TiN has been predominantly used as an adhesion layer for CVD W and to block fluorine penetration during the bulk fill process. W does not grow directly on TiN; thus, it requires deposition of a nucleation layer before the fill step. As logic devices scale through the 10 nm node and beyond, the maximum critical dimension (CD) of the LIC willbe

Metal-organic deposition of thin W-based films offers an ideal solution, because it can eliminate high-resistance liners and nucle- ation layers while maintaining adhesion and fluorine-barrier properties equiv- alent to those of the current process flow. A new W liner has been developed that lowers line resistance for further device scaling: plasma-enhanced (PE) CVD W that nucleates on metal and oxides.

The PECVD W film is produced using a specialized chemical in the presence of reactive plasma that breaks down the ligands. The film composition is primarily W, and the atoms from the decomposed ligands are bonded to the W. The amorphous character of the film and the dopants in it from the ligand lead to good adhesion to dielec- trics and fluorine barrier properties in the 20-30Å range.

FIGURE 1 shows a simulation of a contact plug in the 4-30nm range. The model contains parallel and series resistors for the plug and through resistance. Features are assumed to be straight wall trenches. Resistance of 12 μΩ*cm is used for W at all thicknesses, which under-estimates the benefit of PECVD W. Scattering at film interfaces is not taken into account. The inflections in the curves (from right to left) occur when a film is removed due to volume constraints. It is clear that the benefit of PECVD W increases exponentially as CDs decrease, especially without the nucleation layer.

FIGURE 1. Plug resistance simulation demonstrates the significant benefit of PECVD W without a nucleation layer.

FIGURE 1. Plug resistance simulation demonstrates the significant benefit of PECVD W without a nucleation layer.

SiO2 trench structures with CDs ranging from 10nm to 150nm and a depth of 100nm were used to investigate W line resistance and evaluate gap-fill performance. As shown in FIGURE 2, line resistance in a ~10 nm CD dropped by nearly 90% compared with the conventional stack.

FIGURE 2. PECVD W plus gap fill reduces line resistance by nearly 90% over the conventional stack. The inset TEM shows conformal gap fill and CMP integration for PECVD W.

FIGURE 2. PECVD W plus gap fill reduces line resistance by nearly 90% over the conventional stack. The inset TEM shows conformal gap fill and CMP integration for PECVD W.

Seam-suppressed gap fill

Until now, feature dimensions have made W fill integration possible using nucleation followed by conformal CVD deposition – which always leaves a seam in features. At CDs

A new approach employs a unique, “selective” suppression mechanism that results in a bottom-up fill free of seams or voids. Pre-treating the nucleation layer creates preferred W growth from the bottom of the structure upwards and less on the field, minimizing the likelihood of void-creating pinch-off and seams (FIGURE 3). Experiments showed the process to be successful on structures with CDs ranging from 10nm to 150nm.

FIGURE 3. a.Cross-sectional TEM image of SSW partial fill of 30nm CD,100nm deep trench pattern with overhang created byAr sputter and PVD Ti. (b) TEM image of seamless SSW fill of the same structure. (c) TEM image of standard CVD W gap fill with seam.

FIGURE 3. a.Cross-sectional TEM image of SSW partial fill of 30nm CD,100nm deep trench pattern with overhang created byAr sputter and PVD Ti. (b) TEM image of seamless SSW fill of the same structure. (c) TEM image of standard CVD W gap fill with seam.

Electrical tests confirmed that SSW lowered line resistance compared to that of conventional CVD W (FIGURE 4). Post-CMP defect analysis by top-down view SEM revealed a narrow seam in conventional CVD W after W CMP (FIGURE 5a), while none is visible after SSW fill (FIGURE 5b).

FIGURE 4. Line resistance comparison of SSW and conventional CVD W on 10nm trench.

FIGURE 4. Line resistance comparison of SSW and conventional CVD W on 10nm trench.

Tungsten 5-1

FIGURE 5. Top-down SEM image of a) conventional CVD W process with visible seam in the center of the trench and b) SSW fill on the same structure.

FIGURE 5. Top-down SEM image of a) conventional CVD W process with visible seam in the center of the trench and b) SSW fill on the same structure.

Conclusion

For the next several nodes of logic and memory fabrication, W will remain an important material in interconnect and gate metallization. However, as scaling continues, transi- tions in process flows will be necessary to achieve low contact and line resistance while maintaining gap-fill integrity. A new W-based barrier/liner has been produced through precision materials engineering that improves device performance and integration while simplifying process flows. Similarly, a new SSW gap-fill process increases the volume of W (potentially lowering resistance), creates more robust features for post-fill integration, and relaxes requirements on CMP and dielectric etch steps, thus delivering performance, device design, and yield benefits.

For further detail on the processes presented in this article, see Bakke, J., et al., “Fluorine-Free Tungsten Films as Low Resistance liners for Tungsten Fill Applications” and Kai,W.,etal.,“ImprovingTungstenGap-FillforAdvance Contact Metallization,” presented at the 2016 IEEE Inter- national Interconnect Technology Conference.

IC Insights will release its August Update to the 2016 McClean Report later this month. This Update includes an update of the semiconductor industry capital spending forecast, an analysis of the IC foundry industry, and a look at the top-25 semiconductor suppliers for 1H16, including a forecast for the full year ranking (the top 20 1H16 semiconductor suppliers are covered in this research bulletin).

The top-20 worldwide semiconductor (IC and O-S-D—optoelectronic, sensor, and discrete) sales ranking for 1H16 is shown in Figure 1. It includes eight suppliers headquartered in the U.S., three in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and six fabless companies. If the three pure-play foundries were excluded from the top-20 ranking, China-based fabless supplier HiSilicon ($1,710 million), U.S.-based IDM ON Semiconductor ($1,695 million), and U.S.-based IDM Analog Devices ($1,583 million) would have been ranked in the 18th, 19th, and 20th positions, respectively.

IC Insights includes foundries in the top-20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted. With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers. As shown in the listing, the foundries and fabless companies are identified. In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-20 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

Thirteen of the top-20 companies had sales of at least $3.0 billion in 1H16.  As shown, it took $1.86 billion in sales just to make it into the 1H16 top-20 semiconductor supplier list.  There was one new entrant into the top-20 ranking in 1H16 as compared to the 2015 ranking—AMD, which replaced Japan-based Sharp.  In 2Q16, AMD registered a strong 23% increase in sales while Sharp was moving in the opposite direction logging a 13% decline in its 2Q16/1Q16 revenue.

Intel remained firmly in control of the number one spot in the top-20 ranking in 1H16.  In fact, it increased its lead over Samsung’s semiconductor sales from only 20% in 2015 to 33% in 1H16.  The biggest upward move in the ranking was made by Apple, which jumped up three positions in the 1H16 ranking as compared to 2015. Other companies that made noticeable moves up the ranking include MediaTek and the new Broadcom Ltd. (the merger of Avago and Broadcom), with each company moving up two positions.

Apple is an anomaly in the top-20 ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers.  IC Insights estimates that Apple’s custom ARM-based SoC processors had a “sales value” of $2.9 billion in 1H16, which placed them in the 14th position in the top-20 ranking.

In total, the top-20 semiconductor companies’ sales increased by 7% in 2Q16/1Q16.  Although, in total, the top-20 2Q16 semiconductor companies registered a 7% increase, there were seven companies that displayed a double-digit 2Q16/1Q16 jump in sales and only two that registered a decline (Intel and Renesas).

The fastest growing top-20 company in 2Q16 was Taiwan-based MediaTek, which posted a huge 32% increase in sales over 1Q16.  Although worldwide smartphone unit volume sales are forecast to increase by only 5% this year, MediaTek’s application processor shipments to the fast-growing China-based smartphone suppliers (e.g., Oppo and Vivo), helped drive its stellar 2Q16/1Q16 increase.  Overall, IC Insights expects MediaTek to register about $8.8 billion in sales in 2016, which would represent a 31% surge over the $6.7 billion in sales the company had last year.

As expected, given the possible acquisitions and mergers that could/will occur over the next few years, the top-20 ranking is likely to undergo a significant amount of upheaval as the semiconductor industry continues along its path to maturity.

A look at control of process uniformity across the wafer during plasma etch processes.

BY STEPHEN HWANG and KEREN KANARIK, Lam Research Corporation, Fremont, CA

Controlling process variability to achieve repeatable results has always been important for meeting yield and device performance requirements. With every advance in technology and change in design rule, tighter process controls are needed. In all of these cases, there are multiple sources of variability, often generalized as: within die, across wafer, wafer to wafer, and chamber to chamber. Typically, less than one third of the overall variation is allowed for variation across the wafer. For example, at the 14 nm node, the allowable variation for gate critical dimensions (CDs) is less than 2.4 nm, of which only about 0.84 nm is allowed for variation across the wafer [1]. At the 5 nm node, the allowable variation across the wafer may be less than 0.5 nm, or equivalent to two or three silicon atoms. In this article, we will discuss control of process uniformity across the wafer during plasma etch processes, its evolution in the industry, and some key focus areas.

A fundamental challenge in controlling uniformity in etch processes is the complexity of a plasma. Achieving the desired etch result (e.g., post-etch profile with selectivity to different film materials) requires managing the ratio of different ions and neutrals (e.g., Ar+, C4F8, C4F6+, O, O2+). Since the same plasma generates both types of species, the relative amount of ions to neutrals is strongly coupled. As a result, the impact of parameters typically used to control the plasma (e.g., source power and chamber pressure) are also interdependent.

Improving uniformity through design

Since the start of single-wafer processing in the early 1980s, etch chambers have been designed to produce similar plasma conditions on every location on the wafer to achieve uniform process results. This is especially challenging since there can be inherent electrical and chemical discontinuities at the edge (FIGURE 1) that affect uniformity across the wafer. Voltage gradients are created at the wafer edge due to the change from a biased surface to a grounded or floating surface. This bends the plasma sheath at the wafer edge, which changes the trajectory of ions relative to the wafer. The chemical potential discontinuity is analogous and produces concentration gradients for different species across the wafer. The gradients are caused by multiple phenomena, including variation in reactant consumption and by-products emissions rates at the center relative to the edge, as well as differences in temperature between the chamber and wafer that cause different absorption rates of chemical species.

Lam_Research_Figure_01

FIGURE 1. Discontinuities caused by the wafer edge create gradients that impact uniformity across the surface, with a significant impact at the edge.

 

Many chamber design changes have been implemented over the years to improve radial symmetry (FIGURE 2a). For example, a key hardware parameter for capacitively coupled plasma (CCP) chambers is the gap between the cathode and anode. Historically, the gap would be designed to provide the most uniform etch for a given power, pressure, and mixture of gas chemistries. On inductively coupled plasma (ICP) chambers, the gas injection location was a key design feature that would vary by process. In aluminum etch chambers, the reactant gas was delivered from a showerhead above the wafer. For silicon etch, the reactant gases were injected from around the perimeter of the wafer, but then evolved so that the gas was injected from above the center of the wafer.

FIGURE 2. Process non-uniformity has both radial and non- radial components (A). On a wafer map showing overall non- uniformity, removal of radial asymmetry allows isolating the more challenging non-radial component (B).

FIGURE 2. Process non-uniformity has both radial and non- radial components (A). On a wafer map showing overall non- uniformity, removal of radial asymmetry allows isolating the more challenging non-radial component (B).

With continuous optimization of chamber design, non-radial patterns became more apparent. On a uniformity map, the average of all the points within every radius can be taken and subtracted from the map, which leaves the more difficult asymmetric portion (FIGURE 2b). With this awareness, focus shifted toward elimi- nating asymmetries in the chamber design.

In retrospect, some of these improvements seem obvious. For instance, up to the late 1990s, it was not uncommon to have etch chambers with the turbomolecular pump located to the side of the wafer. This design created a side- to-side pattern due to the convective flow of reactants and by-products laterally across the wafer. By moving the pumps under the wafer, the flow became radially symmetric, thereby eliminating the process asymmetry.

In other cases, the source of asymmetry was more subtle. One interesting non-uniformity corrected with design was a problematic side-to-side pattern on the wafer that had a seemingly random orien- tation chamber-to-chamber. After extensive investigation to eliminate possible sources in the chamber hardware, the pattern was correlated with the Earth’s magnetic field (FIGURE 3). This example demon- strates the sensitivity of plasma processes, even to minor external influences. Although not specifically a chamber issue, the problem was corrected by applying special shielding with high magnetic-permeability materials around the chamber.

FIGURE 3. Non-uniformity induced by the Earth’s magnetic field was identified in an etch process (A). Applying magnetic shielding corrected the problem and provided uniform etch results (B).

FIGURE 3. Non-uniformity induced by the Earth’s magnetic field was identified in an etch process (A). Applying magnetic shielding corrected the problem and provided uniform etch results (B).

 

Development of process tuning capabilities

As etch processes became more varied and complex, fixed chamber designs were not sufficiently flexible to meet increasingly stringent requirements since it was not practical to provide a specific uniformity kit optimized for each etch process. Moreover, it was more challenging to achieve uniform results when etch technology transitioned from processing 200 mm to 300 mm wafers in the early 2000s. As a result, tuning capabilities were developed to deliver the uniformity control needed for a wide range of processes and larger wafer sizes.

By the early 2000s, the first uniformity tuning knobs focused on controlling the chemistry over the wafer. This was done in several ways, for example by splitting the main reactant gases into different locations or by adding tuning gases at separate locations from the main reactant gas. Since then, a number of tunable parameters have been identified for etch processes (Table 1). Ideally, orthogonal (independent) tuning knobs are used in order to match compensation as closely as possible to root causes. This provides the greatest impact on the process while limiting impact on other parameters. For example, in many dielectric etch processes, the etch rate is limited by the flux of ions from the plasma. Since gas injection doesn’t significantly impact plasma density uniformity, Lam Research developed tunable gap technology for CCP chambers to achieve uniform flux of ions across the wafer for a given set of process conditions.

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Over the years, continued development has focused on increasing the spatial resolution for better control across the wafer. For example, gas was at first only injected from the center location above the wafer. Then, additional capability was added that allowed controlling the ratio of gas directed to the center or edge of the wafer. Several years later, an additional gas injection location was added around the periphery of the wafer. To use wafer temperature as a control knob, different heating or cooling zones can be added to an electrostatic chuck (ESC), which holds the wafer. Historically, the number of temperature zones has increased from one to two (by 2002) to four radial zones (by 2006) to improve the radial uniformity of CDs. Since temperature directly affects CD uniformity (CDU), this is an effective way to tackle one of the most critical uniformity challenges.

Some of the most complex process flows today rely on these sophisticated tuning capabilities. Innovations that drive continuous scaling, such as 3D FinFET devices, advanced memory schemes, and double/quadruple patterning techniques, add to the challenge of reducing variability due to the increasing number of steps within the integration flows. Even if the uniformity for individual unit processes (including etch) are relatively good, their combined impact can be significant, and there is need to compensate somewhere in the flow.

When the uniformity profile of a step in the sequence, upstream or downstream, is known and difficult to correct, the profile of an etch step can be modified. For example, if one step is center fast, etch can compensate by being edge fast. This may sound simple, but it is actually quite difficult to achieve the level of process control that can essentially provide a mirror image of the non-uniformity in another process. Fortunately, plasma etch is one process that has matured to being capable of this level of control.

Uniformity control today

After many years of innovation, uniformity control capabilities now have the following characteristics:
• A high degree of granularity (numerous independent tuning locations across the wafer)
• Active tuning of both radial and non-radial patterns
• The ability to compensate for non-unifor- mities upstream and downstream of the etch process

One strategy being used at Lam to achieve the degree of control now needed is providing numerous independent heaters or micro-zones to control the wafer temperature, which is a critical parameter impacting CD uniformity. For example, using more than 100 localized heaters on one etch chamber delivers significantly higher spatial resolution than a system using only two or four heater zones for the entire wafer. Control of numerous individual heaters tunes both radial and non-radial patterns, whereas only center-middle-edge tuning was possible in previous generations (FIGURE 4).

FIGURE 4. Active uniformity control has evolved from limited radial tuning of large areas of the wafer to independent tuning of ever smaller regions across the wafer, enabling control of both radial and non-radial uniformity.

FIGURE 4. Active uniformity control has evolved from limited radial tuning of large areas of the wafer to independent tuning of ever smaller regions across the wafer, enabling control of both radial and non-radial uniformity.

With such high granularity, it is challenging for an individual engineer to manually determine the appropriate settings for so many heaters that will achieve a target thermal pattern across the wafer. To address this issue, advanced algorithms and controls with special temperature calibrations were developed so that the system automatically controls the heaters. Moreover, it can be difficult to determine the thermal map profile that will achieve the required process uniformity. Sophisticated software algorithms have also been developed to use process trends, chamber calibration data, and wafer metrology information to automatically create the appropriate thermal maps. With this capability, incoming non-uniformity can be reduced to less than 0.5 nm CDU after etch (FIGURE 5).

FIGURE 5. Proprietary hardware and software map incoming CDs and adjust etch process conditions in the numerous micro- zones across the wafer to compensate for variability from upstream processes.

FIGURE 5. Proprietary hardware and software map incoming CDs and adjust etch process conditions in the numerous micro- zones across the wafer to compensate for variability from upstream processes.

Future focus areas

Beyond the uniformity challenges discussed, performance at the edge of the wafer – the outer 10mm, where up to 10% of the die may be located – is an increasingly important area of future focus for improving yield. In this region, uniformity control is dominated by the electrical discontinuities at the edge of the wafer that can cause sheath bending. The impacted region of sheath bending is much smaller (~10-15 mm from the edge) compared to chemical or thermal effects (50-70 or 30-50 mm, respectively). While fixed edge hardware can be redesigned for optimal uniformity, new technologies are in development to provide in situ tunability of the sheath at the wafer edge.

Looking ahead, we can expect more types of control knobs and further granularity for finer tuning along with a greater focus on automation. Compensatory process control should continue to develop and be used as process modules become increasingly complex.

REFERENCES

1. ITRS 2013: Table FEP 12 Etch Process Technology Requirements

The year 2016 is not expected to be a good one for the total memory market and the main culprit is DRAM. Declining shipments of desktop and notebook computers, the biggest users of DRAM, as well as declining tablet PC shipments and slowing growth of smartphone units have created excess inventory and suppliers have been forced to greatly reduce average selling prices in order to move parts. A DRAM ASP decline of 16% coupled with a forecast 3% decline in DRAM unit shipments is expected to result in the DRAM market declining 19% in 2016 (Figure 1), lowest among the 33 IC product categories IC Insights tracks in detail. This steep decline will be a drag on growth for the total memory market (-11%) and for the total IC market (-2%) in 2016.

Figure 1

Figure 1

Big swings in average selling price are not new to the DRAM market. Annual DRAM average selling price increases of 48% and 26% in 2013 and 2014 propelled the DRAM market to more than 30% growth each year. In fact, the DRAM market was the strongest growing IC product segment in each of those years (Figure 2). Then, marketshare grabs and excess inventory started the cycle of steep price cuts in the second half of 2015 and that continued through the first half of 2016.

Figure 2

Figure 2

Figure 3 plots changes in annual DRAM average selling prices starting in 2007.  Looking more like the profile of an alpine mountain range, DRAM ASP growth has taken several dramatic upward and downward turns since 2007, confirming the volatility of this IC market segment. When coupled with strength or weakness in DRAM unit shipments, bit volume demand, and the amount of capacity and capital spending dedicated to DRAM production each year, this market can turn quickly up or down.

Figure 3

Figure 3

On a positive note, DRAM ASPs strengthened in late 2Q16 and are forecast to continue growing through the balance of 2016 and into 2017.  The boost to DRAM ASP is expected to come from demand for enterprise (server) systems, which have been selling well due to the need to process “big data” (e.g., the Cloud and the Internet of Things).  Also, low-voltage DRAM continues to enjoy solid demand for use in mobile platforms, particularly smartphones.  Demand from new smartphone models is expected to help contribute to increasing DRAM ASPs through the end of this year and into 2017.

The upward DRAM ASP trend may be short lived, however, as two China-based companies, Sino King Technology in Hefei, China, and Fujian Jin Hua IC Company, plan to enter the DRAM marketplace beginning in late 2017 or early 2018.  It remains to be seen what devices and what technology the two new entrants will offer but their presence in the market could signal that another round of price declines is around the corner.

Further trends and analysis relating to DRAM and the total memory market through 2020 are covered in the 250 plus-page Mid-Year Update to the 2016 edition of The McClean Report.

Overall revenue for the power semiconductors market globally dropped slightly in 2015, due primarily to macroeconomic factors and application-specific issues, according to a new report from IHS Markit (Nasdaq: INFO), a world leader in critical information, analytics and solutions.

The global market for power semiconductors fell 2.6 percent to $34 billion in 2015, the report says. Discrete power semiconductor product revenue declined 10.1 percent, while power module revenues decreased by 11.4 percent and power integrated-circuit (IC) revenues increased by 4.5 percent overall.

The report identifies Infineon Technologies as last year’s leading power semiconductor manufacturer, with 12 percent of the market, Texas Instruments with 11 percent and STMicroelectronics with 6 percent.

“While Texas Instruments previously led the market in 2014, the company was overtaken by Infineon Technologies in 2015, following its acquisition of International Rectifier and LS Power Semitech,” said Richard Eden, senior analyst, IHS Markit. “Infineon was the leading global supplier of both discrete power semiconductors and power modules, and the fourth-largest supplier of power management ICs. Infineon has been the leading supplier of discretes for several years, but overtook Mitsubishi Electric to lead the power module market for the first time in 2015, again, due to the International Rectifier and LS Power Semitech acquisitions.”

Figure 1

Figure 1

According to the latest Power Semiconductor Market Share Report from IHS Markit, while Infineon Technologies’ acquisition of International Rectifier was the largest acquisition last year, several other deals also changed the terrain of the power semiconductor market landscape. Key deals in 2015 included the following: MediaTek acquired RichTek; Microchip acquired Micrel; NXP Semiconductors acquired Freescale Semiconductor; NXP Semiconductors also created WeEn Semiconductors, a joint venture with Beijing JianGuang Asset Management Co. Ltd (JAC Capital); CSR Times Electric merged with China CNR Corporation to form CRRC Times Electric; and ROHM Semiconductor acquired Powervation.

“Companies were active in acquisitions for several reasons — especially the low financing cost in multiple regions of the world, which meant that borrowing rates in the United States and European Central bank were nearly zero,” said Jonathan Liao, senior analyst, IHS Markit. “In addition, the acquiring company typically increases its revenues and margins by taking the acquired company’s existing customers and sales without incurring marketing, advertising and other additional costs.”

The Power Semiconductor Market Share Report, part of the Power Semiconductor Intelligence Service from IHS Markit, offers insight into the global market for power semiconductor discretes, modules and integrated circuits. This year’s report includes Power ICs for the first time, as well as discrete power semiconductors and power semiconductor modules. For more information about purchasing IHS Markit information, contact the sales department at [email protected].

Towards a better screen


August 9, 2016

Harvard University researchers have designed more than 1,000 new blue-light emitting molecules for organic light-emitting diodes (OLEDs) that could dramatically improve displays for televisions, phones, tablets and more.

OLED screens use organic molecules that emit light when an electric current is applied. Unlike ubiquitous liquid crystal displays (LCDs), OLED screens don’t require a backlight, meaning the display can be as thin and flexible as a sheet of plastic. Individual pixels can be switched on or entirely off, dramatically improving the screen’s color contrast and energy consumption. OLEDs are already replacing LCDs in high-end consumer devices but a lack of stable and efficient blue materials has made them less competitive in large displays such as televisions.

The interdisciplinary team of Harvard researchers, in collaboration with MIT and Samsung, developed a large-scale, computer-driven screening process, called the Molecular Space Shuttle, that incorporates theoretical and experimental chemistry, machine learning and cheminformatics to quickly identify new OLED molecules that perform as well as, or better than, industry standards.

“People once believed that this family of organic light-emitting molecules was restricted to a small region of molecular space,” said Alán Aspuru-Guzik, Professor of Chemistry and Chemical Biology, who led the research. “But by developing a sophisticated molecular builder, using state-of-the art machine learning, and drawing on the expertise of experimentalists, we discovered a large set of high-performing blue OLED materials.”

The research is described in the current issue of Nature Materials.

The biggest challenge in manufacturing affordable OLEDs is emission of the color blue.

Like LCDs, OLEDs rely on green, red and blue subpixels to produce every color on screen.  But it has been difficult to find organic molecules that efficiently emit blue light. To improve efficiency, OLED producers have created organometallic molecules with expensive transition metals like iridium to enhance the molecule through phosphorescence. This solution is expensive and it has yet to achieve a stable blue color.

Aspuru-Guzik and his team sought to replace these organometallic systems with entirely organic molecules.

The team began by building libraries of more than 1.6 million candidate molecules. Then, to narrow the field, a team of researchers from the Harvard John A. Paulson School of Engineering and Applied Sciences (SEAS), led by Ryan Adams, Assistant Professor of Computer Science, developed new machine learning algorithms to predict which molecules were likely to have good outcomes, and prioritize those to be virtually tested. This effectively reduced the computational cost of the search by at least a factor of ten.

“This was a natural collaboration between chemistry and machine learning,” said David Duvenaud, a postdoctoral fellow in the Adams lab and coauthor of the paper. “Since the early stages of our chemical design process starts with millions of possible candidates, there’s no way for a human to evaluate and prioritize all of them. So, we used neural networks to quickly prioritize the candidates based on all the molecules already evaluated.”

“Machine learning tools are really coming of age and starting to see applications in a lot of scientific domains,” said Adams.  “This collaboration was a wonderful opportunity to push the state of the art in computer science, while also developing completely new materials with many practical applications. It was incredibly rewarding to see these designs go from machine learning predictions to devices that you can hold in your hand.”

“We were able to model these molecules in a way that was really predictive,” said Rafael Gómez-Bombarelli, a postdoctoral fellow in the Aspuru-Guzik lab and first author of the paper.  “We could predict the color and the brightness of the molecules from a simple quantum chemical calculation and about 12 hours of computing per molecule. We were charting chemical space and finding the frontier of what a molecule can do by running virtual experiments.”

“Molecules are like athletes,” Aspuru-Guzik said. “It’s easy to find a runner, it’s easy to find a swimmer, it’s easy to find a cyclist but it’s hard to find all three. Our molecules have to be triathletes. They have to be blue, stable and bright.”

But finding these super molecules takes more than computing power — it takes human intuition, said Tim Hirzel, a senior software engineer in the Department of Chemistry and Chemical Biology and coauthor of the paper.

To help bridge the gap between theoretical modeling and experimental practice, Hirzel and the team built a web application for collaborators to explore the results of more than half a million quantum chemistry simulations.

Every month, Gómez-Bombarelli and coauthor Jorge Aguilera-Iparraguirre, also a postdoctoral fellow in the Aspuru-Guzik lab, selected the most promising molecules and used their software to create “baseball cards,” profiles containing important information about each molecule. This process identified 2500 molecules worth a closer look.  The team’s experimental collaborators at Samsung and MIT then voted on which molecules were most promising for application. The team nicknamed the voting tool “molecular Tinder” after the popular online dating app.

“We facilitated the social aspect of the science in a very deliberate way,” said Hirzel.

“The computer models do a lot but the spark of genius is still coming from people,” said Gómez-Bombarelli.

“The success of this effort stems from its multidisciplinary nature,” said Aspuru-Guzik. “Our collaborators at MIT and Samsung provided critical feedback regarding the requirements for the molecular structures.”

“The high throughput screening technique pioneered by the Harvard team significantly reduced the need for synthesis, experimental characterization, and optimization,” said Marc Baldo, Professor of Electrical Engineering and Computer Science at MIT and coauthor of the paper. “It shows the industry how to advance OLED technology faster and more efficiently.”

After this accelerated design cycle, the team was left with hundreds of molecules that perform as well as, if not better than, state-of-the-art metal-free OLEDs.

Applications of this type of molecular screening also extend far beyond OLEDs.

“This research is an intermediate stop in a trajectory towards more and more advanced organic molecules that could be used in flow batteries, solar cells, organic lasers, and more,” said Aspuru-Guzik. “The future of accelerated molecular design is really, really exciting.”

In addition to the authors mentioned, the manuscript was coauthored by Dougal Maclaurin, Martin A. Blood-Forsythe, Hyun Sik Chae, Markus Einzinger, Dong-Gwang Ha, Tony Wu, Georgios Markopoulos, Soonok Jeon, Hosuk Kang, Hiroshi Miyazaki, Masaki Numata, Sunghan Kim, Wenliang Huang and Seong Ik Hong.

The research was supported by the Samsung Advanced Institute of Technology.

To continue advancing, next-generation electronic devices must fully exploit the nanoscale, where materials span just billionths of a meter. But balancing complexity, precision, and manufacturing scalability on such fantastically small scales is inevitably difficult. Fortunately, some nanomaterials can be coaxed into snapping themselves into desired formations-a process called self-assembly.

Scientists at the U.S. Department of Energy’s (DOE) Brookhaven National Laboratory have just developed a way to direct the self-assembly of multiple molecular patterns within a single material, producing new nanoscale architectures. The results were published in the journal Nature Communications.

“This is a significant conceptual leap in self-assembly,” said Brookhaven Lab physicist Aaron Stein, lead author on the study. “In the past, we were limited to a single emergent pattern, but this technique breaks that barrier with relative ease. This is significant for basic research, certainly, but it could also change the way we design and manufacture electronics.”

Microchips, for example, use meticulously patterned templates to produce the nanoscale structures that process and store information. Through self-assembly, however, these structures can spontaneously form without that exhaustive preliminary patterning. And now, self-assembly can generate multiple distinct patterns-greatly increasing the complexity of nanostructures that can be formed in a single step.

“This technique fits quite easily into existing microchip fabrication workflows,” said study coauthor Kevin Yager, also a Brookhaven physicist. “It’s exciting to make a fundamental discovery that could one day find its way into our computers.”

The experimental work was conducted entirely at Brookhaven Lab’s Center for Functional Nanomaterials (CFN), a DOE Office of Science User Facility, leveraging in-house expertise and instrumentation.

Cooking up organized complexity

The collaboration used block copolymers-chains of two distinct molecules linked together-because of their intrinsic ability to self-assemble.

“As powerful as self-assembly is, we suspected that guiding the process would enhance it to create truly ‘responsive’ self-assembly,” said study coauthor Greg Doerk of Brookhaven. “That’s exactly where we pushed it.”

To guide self-assembly, scientists create precise but simple substrate templates. Using a method called electron beam lithography-Stein’s specialty-they etch patterns thousands of times thinner than a human hair on the template surface. They then add a solution containing a set of block copolymers onto the template, spin the substrate to create a thin coating, and “bake” it all in an oven to kick the molecules into formation. Thermal energy drives interaction between the block copolymers and the template, setting the final configuration-in this instance, parallel lines or dots in a grid.

“In conventional self-assembly, the final nanostructures follow the template’s guiding lines, but are of a single pattern type,” Stein said. “But that all just changed.”

Lines and dots, living together

The collaboration had previously discovered that mixing together different block copolymers allowed multiple, co-existing line and dot nanostructures to form.

“We had discovered an exciting phenomenon, but couldn’t select which morphology would emerge,” Yager said. But then the team found that tweaking the substrate changed the structures that emerged. By simply adjusting the spacing and thickness of the lithographic line patterns-easy to fabricate using modern tools-the self-assembling blocks can be locally converted into ultra-thin lines, or high-density arrays of nano-dots.

“We realized that combining our self-assembling materials with nanofabricated guides gave us that elusive control. And, of course, these new geometries are achieved on an incredibly small scale,” said Yager.

“In essence,” said Stein, “we’ve created ‘smart’ templates for nanomaterial self-assembly. How far we can push the technique remains to be seen, but it opens some very promising pathways.”

Gwen Wright, another CFN coauthor, added, “Many nano-fabrication labs should be able to do this tomorrow with their in-house tools-the trick was discovering it was even possible.”

The scientists plan to increase the sophistication of the process, using more complex materials in order to move toward more device-like architectures.

“The ongoing and open collaboration within the CFN made this possible,” said Charles Black, director of the CFN. “We had experts in self-assembly, electron beam lithography, and even electron microscopy to characterize the materials, all under one roof, all pushing the limits of nanoscience.”