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As the popularity and penetration of wearable and mobile devices increase, so too will demand for innovative flexible displays. In fact, revenue from flexible displays is expected to increase more than 300 percent, from just $3.7 billion in 2016 to $15.5 billion in 2022. Flexible displays will comprise 13 percent of total display market revenue in 2020, according to IHS Inc. (NYSE: IHS).

Samsung Electronics and LG Electronics launched the first smartphones with flexible active-matrix organic light-emitting diode (AMOLED) displays in 2013, and both companies continue to adapt flexible AMOLED displays for their smartphones, smartwatches and fitness trackers. Inspired by these successes, other mobile manufacturers are now developing their own flexible-display devices.

“The varieties of flexible displays include screens that are bendable, curved and edge-curved, but fully foldable form factors are expected within the next two years,” said Jerry Kang, principal analyst of display research for IHS Technology. “Only a few suppliers — including Samsung Display, LG Display, E-ink and Futaba — are now regularly supplying flexible displays to the market. However, many more panel makers are now attempting to build flexible display capacity, leveraging the latest AMOLED display technology.”

According to the IHS Flexible Display Market Tracker, flexible displays are primarily used in smartphones and smartwatches in 2016; however, use in other applications, including tablet PCs, near-eye virtual reality devices, automotive monitors and OLED TVs is expected by 2022. “Consumer device manufacturers will eventually need to innovate their conventionally designed flat, rectangular form-factors to make way for the latest curved, foldable and rollable screens,” Kang said.

Flex_Display_Chart_IHS

The Semiconductor Industry Association (SIA) announced the release of the 2015 International Technology Roadmap for Semiconductors (ITRS), a collaborative report that surveys the technological challenges and opportunities for the semiconductor industry through 2030. The ITRS seeks to identify future technical obstacles and shortfalls, so the industry and research community can collaborate effectively to overcome them and build the next generation of semiconductors – the enabling technology of modern electronics. The current report marks the final installment of the ITRS.

“For a quarter-century, the Roadmap has been an important guidepost for evaluating and advancing semiconductor innovation,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The latest and final installment provides key findings about the future of semiconductor technology and serves as a useful bridge to the next wave of semiconductor research initiatives.”

Faced with ever-evolving research needs and technology challenges, industry leaders have decided to conclude the ITRS and transition to new ways to advance semiconductor research and bring about the next generation of semiconductor innovations. While the final ITRS report charts a path for existing technology research, additional research is needed as we transition to an even more connected world, enabled by innovations like the Internet of Things. Some of these technology challenges were outlined in a recent SIA-Semiconductor Research Corporation (SRC) report, “Rebooting the IT Revolution,” but work continues to define research gaps and implement new research programs.

The ITRS is sponsored by five regions of the world – Europe, Japan, Korea, Taiwan, and the United States. Through the cooperative efforts of the global chip manufacturers and equipment suppliers, research communities and consortia, the ITRS has identified critical gaps, technical needs, and potential solutions related to semiconductor technology.

“SIA appreciates the hard work, dedication, and expertise of those involved with the ITRS over the years and looks forward to continuing the industry’s work to strengthen semiconductor research and maintain the pipeline of semiconductor innovations that fuel the digital economy,” Neuffer said.

By Pete Singer, Editor-in-Chief

The semiconductor industry is moving quickly to adopt a variety of new materials in an effort to increase chip performance. These new materials can create a host of safety concerns that must be addressed. Many of the new process chemicals have low vapor pressures, are highly reactive and present serious hazards to personnel and equipment. Many new CVD precursors and their associated reaction by-products are flammable, pyrophoric, toxic, corrosive or otherwise hazardous to personnel or destructive to equipment. “The problem’s always been there. It’s just becoming more acute as new processes emerge,” said Andrew Chambers, Senior Product Manager at Edwards Ltd., Clevedon, UK.

The Danger That Lurks Figure

Process byproducts are pumped through exhaust lines to a gas abatement system. Residual precursor materials or reaction byproducts often have a tendency to condense in pipe-work, including process exhausts. These exhaust pipes must be cleaned regularly, since condensed material will block the pipe, reduce its conductance and cause process problems.

Epitaxial silicon (“epi”) deposition processes, for example, are particularly notorious for the process decomposition products condensing in exhaust pipes or in the foreline of the pump. The hazard is greatest when the exhaust system is dismantled for cleaning. “The condensed material can react violently when it’s exposed to air and will burn vigorously or even explode. That presents a pretty serious hazard to the service engineers who are charged with taking the pipe apart and cleaning it,” Chambers said.

These problems can largely be avoided, however, by keeping the exhaust pipe or the pump foreline at a high temperature to avoid condensation of the material. If the surfaces in the exhaust system are warm enough, the processed products transit through the exhaust pipe and into the abatement system, where they can be combusted and dealt with in a safe fashion.

In many fabs, the heating is done with heating tape, but that’s not always the best (or safest) way to go. “In principle, that works up to a point but it’s quite difficult to apply that kind of technique when you’ve got accessories like a large ball valve in the line, where there are brackets attaching the exhaust pipe to the wall or there’s a system for injecting nitrogen dilution gas into the exhaust. The idea of heater tapes is convenient but not a very effective fix,” Chambers said. “Furthermore, removing heater tape to dismantle and clean the exhaust pipe can be inconvenient and time consuming” he added.

What’s really required is an approach that involves heating the pipe in a uniform fashion so that the pipe is universally at a high temperature to avoid the condensation. “You can’t afford to have cold spots in the pipe where there’s no heater or there’s no insulation because the moment you have a cold spot in the pipe, then material’s going to condense there and cause a local blockage,” he said.

Edwards offers a new Temperature Management System (SMART TMS) that ensures these compounds remain volatile until they enter the abatement device. SMART TMS is designed to heat both forelines and pump exhaust lines uniformly as far as the inlet of the abatement device. Molded high surface area heaters maximize contact with pipes and are designed to maintain them at a constant temperature between ambient and 180°C, recognizing that when choosing the temperature set point, knowledge of what process materials and byproducts are going to be in the exhaust pipe is invaluable.

Chambers said this approach is also superior to other heating methods using custom heater mats with integral insulation. “The difficulty you encounter with those kinds of systems is that the heater mat and jacket tend to be custom-designed to suit the particular installation. You spend a lot of time designing stuff, placing orders and waiting for it to be manufactured. Once it is manufactured and installed, there’s no flexibility. If you change the configuration of the exhaust pipe, you’ve got to go buy a whole set of new pipeline heating components,” he said.

With the Edwards SMART TMS approach, heater mats are provided separately from the insulation. “The heater mats are provided in standard lengths and as shaped components too, for elbows, valves, T-pieces and so on. You basically assemble the heater mats of sufficient length to heat your pipe from one end to the other. Then, since they’re made from low-particulate material, the insulation jackets can be cut to shape on assembly to fit the exhaust pipe. They’re all basically reusable,” Chambers said.

Success in thermal management goes well beyond mechanical considerations, however. “A lot of the skill and judgment in temperature management of exhaust pipes is knowing what factors you need to take care of to get decent temperature control throughout the system,” Chambers said.

When handling flammable gases, for example, nitrogen is often used to dilute them below their lower flammable limit to make them safe. “Typically, you pour a whole lot of nitrogen dilution gas into your exhaust pipe. The way in which you do that has a very significant impact on the temperature of the gas and the temperature of the exhaust pipe,” Chambers said. “If you’ve heated your exhaust pipe up to a temperature based on the process gases flowing through it and then you flow into it a couple of hundred liters per minute of cold nitrogen, then your heating system is no longer going to be fully effective. You start to run into the kind of condensation problem you were trying to avoid in the first place.”

The Edwards solution to that problem is to employ a system to heat up the nitrogen dilution gas. “Providing a nitrogen heater system as an accompaniment to a temperature management system for the exhaust pipe is sometimes a desirable thing to do,” Chambers added.

SMART TMS includes a sophisticated control system. “In our system, we have a controller which takes care of exhaust pipes on a zone by zone basis. The controller can control nine zones. All of those nine zones may be nine separate pipes. It may be one long pipe with nine zones in it over a long distance,” Chambers said.

The controller has useful operational features such as the ability to set and log different control temperatures and user-defined limits in each zone. If a temperature strays outside the user-defined band, an alert is transmitted from the controller to the process tool, the fab central monitoring system or other fault reporting system, depending on the nature of the fault. Furthermore, recognizing that some processes can cause very hazardous byproduct build-up in cold exhausts, SMART TMS includes a “fail-on” function to ensure that in the event of a component failure or loss of temperature indication a high pipeline temperature is maintained until servicing can be scheduled. In these cases the integrated health-check function provides an alert, while dual safety devices in each heater provide intrinsic safety and protection against thermal runaway.

“In the future, we can imagine the process which is running in the tool can be used to inform the set-up of the sub-fab equipment, the dry pumps or even the temperature management system,” Chambers said. “We’ve come a long way from relatively simple electrical heaters installed on an ad hoc basis to a sophisticated combination of process knowledge, a wide range of heater mats and shaped heaters, very efficient insulation materials and intelligent controllers with data acquisition capability.”

By Pete Singer, Editor-in-Chief

Last year, Rudolph Technologies, Inc. announced the widespread adoption and success of its newest macro defect inspection tool, the NSX® 330 Series. The NSX 330 Series provides high-speed macro defect inspection with 2D\3D metrology for advanced packaging applications, which are being developed primarily to support mobility. The company said it had been “quickly and enthusiastically adopted,” garnering repeat orders from top foundries, integrated device manufacturers (IDMs) and outsourced assembly and test (OSAT) manufacturers.

The NSX 330 Series offers an array of metrology capabilities for both 2D and 3D metrology applications, including 100 percent bump height and coplanarity measurements. The NSX 330 series has now been further improved by incorporating a high speed bump laser triangulation sensor and the highly accurate VT-SS distance and thickness sensor. “We specifically offer these capabilities on a single platform because they improve total measurement accuracy on complex materials which have troubled the industry for some time,” said Scott Balak, director, inspection product management, Rudolph Technologies Inc. (Bloomington, MN).

Figure 1 illustrates the problem. The goal is to measure the actual bump height and overall coplanarity from bump top to polyimide (PI) surface. If one or more bumps are too high or too low, the other bumps won’t connect. A high-speed laser triangulation sensor attempts to see through the polyimide (PI) layer, which is typically 3-6 microns thick. “The problem is that polyimide isn’t completely transparent, so when the triangulation sensor attempts to detect the bottom of this PI layer, it is actually finding it somewhere in the middle. The current industry’s work around is to assume a PI thickness and apply a PI layer offset; however, PI thickness variation limits the accuracy of this approach,” Balak explained.

Figure 1

Figure 1

Inaccurate measurements create unnecessary review work. Because bumps may have acceptable coplanarity, but they are incorrectly flagged for further evaluation. “Customers use the review mode to determine if the bump is actually too big, or too small” Balak said.

Enter Rudolph’s Visible Thickness and Shape Sensor (VT-SS) sensor, which can concurrently measure the transparent layer thickness as well as the metal feature step height above the surface of the transparent layer. This is achieved through the integration of reflectometry and visible light interferometry principles. The direct reflection from the transparent layer provides direct thickness measurement of the transparent material, while the interferometry captures topography (distance from the sensor), allowing the system to measure the thickness of the opaque metals by scanning over the edge of the feature.

“Rudolph samples multiple bumps with both the laser triangulation and VT-SS sensors to accurately obtain a measurement average of wafer PI thickness while simultaneously calibrating the triangulation sensor with an accurate PI offset for the specific wafer being measured.,” Balak said. “The properly calibrated triangulation sensor then quickly and accurately measures millions of bumps per wafer correctly flagging bad bumps and eliminating the need to review good product. Wafer results are then sent to our Discover Analysis solution where customers can analyze correlations between defectivity and process metrology to improve the overall process. Whether it is understanding wafer and lot level trends or specific individual bumps; Discover provides the drill down capability required for root cause analysis.”

Just as many of us might be resigned to clogged salt shakers or rush-hour traffic, those working to exploit the special properties of carbon nanotubes have typically shrugged their shoulders when these tiniest of cylinders fill with water during processing. But for nanotube practitioners who have reached their Popeye threshold and “can’t stands no more,” the National Institute of Standards and Technology (NIST) has devised a cheap, quick and effective strategy that reliably enhances the quality and consistency of the materials–important for using them effectively in applications such as new computing technologies.

To prevent filling of the cores of single-wall carbon nanotubes with water or other detrimental substances, the NIST researchers advise intentionally prefilling them with a desired chemical of known properties. Taking this step before separating and dispersing the materials, usually done in water, yields a consistently uniform collection of nanotubes. In quantity and quality, the results are superior to water-filled nanotubes, especially for optical applications such as sensors and photodetectors.

To prevent cores of single-wall carbon nanotubes from filling with water or other detrimental substances, the NIST researchers advise intentionally prefilling them with a desired chemical of known properties. Taking this step before separating and dispersing the materials, usually done in water, yields a consistently uniform collection of nanotubes, especially important for optical applications. Credit: Fagan/NIST

To prevent cores of single-wall carbon nanotubes from filling with water or other detrimental substances, the NIST researchers advise intentionally prefilling them with a desired chemical of known properties. Taking this step before separating and dispersing the materials, usually done in water, yields a consistently uniform collection of nanotubes, especially important for optical applications. Credit: Fagan/NIST

The approach opens a straightforward route for engineering the properties of single-wall carbon nanotubes–rolled up sheets of carbon atoms arranged like chicken wire or honey combs–with improved or new properties.

“This approach is so easy, inexpensive and broadly useful that I can’t think of a reason not to use it,” said NIST chemical engineer Jeffrey Fagan.

In their proof-of-concept experiments, the NIST team inserted more than 20 different compounds into an assortment of single-wall carbon nanotubes with an interior diameter that ranged from more than 2 down to about 0.5 nanometers. Led by visiting researcher Jochen Campo, the scientists tested their strategy by using hydrocarbons called alkanes as fillers.

The alkanes, which include such familiar compounds as propane and butane, served to render the nanotube interiors unreactive. In other words, the alkane-filled nanotubes behaved almost as if they were empty–precisely the goal of Campo, Fagan and colleagues.

Compared with nanotubes filled with water and possibly ions, acids and other unwanted chemicals encountered during processing, empty nanotubes possess far superior properties. For example, when stimulated by light, empty carbon nanotubes fluoresce far brighter and with sharper signals.

Yet, “spontaneous ingestion” of water or other solvents by the nanotubes during processing is an “endemic but often neglected phenomenon with strong implications for the development of nanotube applications,” the NIST team wrote in a recent article in Nanoscale Horizons.

Perhaps because of the additional cost and effort required to filter out and gather nanotubes, researchers tend to tolerate mixed batches of unfilled (empty) and mostly filled single-wall carbon nanotubes. Separating unfilled nanotubes from these mixtures requires expensive ultracentrifuge equipment and, even then, the yield is only about 10 percent, Campo estimates.

“If your goal is to use nanotubes for electronic circuits, for example, or for fluorescent anti-cancer image contrast agents, then you require much greater quantities of materials of consistent composition and quality,” Campo explained, who was exploring these applications while doing postdoctoral research at the University of Antwerp. “This particular need inspired development of the new prefilling method by asking the question, can we put some passive chemical into the nanotube instead to keep the water out.”

From the very first simple experiments, the answer was yes. And the benefits can be significant. In fluorescence experiments, alkane-filled nanotubes emitted signals two to three times stronger than those emitted by water-filled nanotubes. Performance approached that of empty nanotubes–the gold standard for these comparisons.

As important, the NIST-developed prefilling strategy is controllable, versatile and easily incorporated into existing methods for processing single-wall carbon nanotubes, according to the researchers.

The increasing value of the average IC content in cellular handsets along with the increasing percentage of smartphones sold as a percent of total cellular handsets will help drive the cellphone IC market to $94.3 billion in 2019. Strong double-digit growth rates in the cellular handset IC market were logged in 2013 and 2014 but only a 2% increase was registered in 2015. Despite the expected increase of 4% in 2016, the 2015-2019 total cellphone IC market CAGR is forecast to be 6.7%, 3.0 points higher than the 3.7% CAGR forecast for the total IC market during this same time.  The $94.3 billion 2019 cellphone IC market is forecast to be about 30% higher than the level registered in 2015.

Figure 1

Figure 1

In 2015, the IC product segment that had the highest average content per cellphone was the MPU category ($9.92), which includes the application processors used in smartphones.  The second highest was the application specific logic segment, which had an average $8.55 of IC content per cellular handset.  In total, there was an average of $38.78 worth of ICs in a 2015 cellular handset.

DRAM memory held 59% ($12.3 billion) of the total cellphone memory market in 2015, with NAND flash representing most of the remainder of the market.  The $21.0 billion cellphone memory market in 2015 was driven by the surge in shipments of memory-rich high-end smartphones and the 6% increase in the cellphone DRAM market.

The average analog content in a cellphone increased in 2015 to $6.64 while the total cellphone analog IC market increased by 8%, six points better than the 2% growth rate experienced by the total 2015 analog IC market.  Application specific analog, mostly comprised of mixed-signal devices, represented about 83% of the total $12.5 billion 2015 cellular handset analog IC market.

In 2019, as the market shifts more toward low-end smartphones, the cellphone MPU market is expected to represent 23% of the total cellphone IC market, down two points from 26% in 2015.  Moreover, the cellphone DRAM memory market in 2019 is forecast to reach $19.9 billion and be more than 2x larger than the total flash cellphone IC market ($9.5 billion) in that year.  In contrast to the high-growth cellphone DRAM market, the 2019 cellphone DSP market is forecast to be less than $0.1 billion, down from $1.3 billion in 2012.

By Pete Singer, Editor-in-Chief

On Wednesday, Solid State Technology and SEMI announced the recipient of the 2016 “Best of West” Award — Coventor — for its SEMulator3D. The award recognizes important product and technology developments in the electronics manufacturing supply chain. The Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

Coventor won the “Best-of-West” award for its SEMulator 3D modeling software. Left to right, SEMI’s Karen Savala, Dinesh Bettadapur, vice president, business development at Coventor, who received the award, and Pete Singer, Editor-in-Chief of Solid State Technology.

Coventor won the “Best-of-West” award for its SEMulator 3D modeling software. Left to right, SEMI’s Karen Savala, Dinesh Bettadapur, vice president, business development at Coventor, who received the award, and Pete Singer, Editor-in-Chief of Solid State Technology.

Coventor’s SEMulator3D is a 3D semiconductor process modeling platform that can predictively model any fabrication process applied to any semiconductor design. Starting from a “virtual” silicon wafer, the product performs a series of unit processes like those in the fab to create highly accurate 3D computer models of the predicted structures on wafer.

“It’s a very powerful software modeling platform that has been widely adopted for advanced process development and integration for 10nm, 7nm nodes and beyond,” said Dinesh Bettadapur, vice president, business development at Coventor. Bettadapur accepted the award in the Coventor booth, presented by Solid State Technology’s Pete Singer and SEMI’s Karen Savala.

Bettadapur noted that advanced devices are increasingly becoming 3D, whether it’s finFET structures, 3D NAND or gate-all-around. “We enable you to both visualize the device you’re trying to build in advance without running a single wafer, and also accurately predict process variations,” he said.

Using unique physics-driven 3D modeling technology, the SEMulator3D modeling engine can model a wide variety of unit process steps. Each process step requires only a few geometric and physical input parameters that are easy to understand and calibrate. Just as in an actual fab, upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity, etc.) interact with each other and design data in a complex way to impact the final device structure.

“You can analyze any process variation, whether it’s film thicknesses, sidewall angles, etch depths, litho biases and so forth. You can vary any process parameter that you have entered in our process simulator and then look at the upstream and downstream process effects,” Bettadapur said.

Starting from input design data, SEMulator3D follows an integrated process flow description to create the virtual equivalent of the complex 3D structures created in the fab. Because the full integrated process sequence is modeled, SEMulator3D has the ability to predict downstream ramifications of process changes that would otherwise require build-and-test cycles in the fab.

On display at Coventor’s booth is 3D sculpture modeled on 14nm FinFET Technology (see photo). This piece received the grand prize at the Design Automation Conference (DAC) last month.

The piece was produced on a state-of-the-art 3D printer from Stratasys, using SEMulator3D to generate the data. The effort was supported by GrabCad, a digital manufacturing hub that helps designers and engineers build great products faster.

With SEMulator3D, Coventor created a large model of 14nm FinFET transistors, across a wide area of SRAM design, at high resolution, integrated from starting wafer through Metal 3, with some artistic cut-outs for visibility.   The resulting model reinforced all the key advanced capabilities of SEMulator3D, including multietch, visibility-limited deposition, selective epitaxy and many others.

As DAC grand prize winner, the 14nm FinFET 3D Sculpture will now be moved to the Computer History Museum in Mountain View, CA where it will be on display for one year.

Hear more about the SEMulator 3D and all of the Best of West finalists today at the Best of West Showcase in the Advanced Manufacturing Forum at TechXPOT South from 2:00pm-3:30pm.

SEMulator3D Viewer, showing a hypothetical 22nm FinFET SRAM cell

SEMulator3D Viewer, showing a hypothetical 22nm FinFET SRAM cell

200mm fabs reawakening


July 13, 2016

By David Lammers, Contributing Editor

Buoyed by strong investments in China, 200mm wafer production is seeing a re-awakening, with overall 200mm capacity expected to match its previous 2006 peak level by 2019 (Figure 1).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Speaking at a SEMI/Gartner market symposium at SEMICON West, SEMI senior analyst Christian Dieseldorff said over the next few years “we don’t see 200mm fabs closing, in fact we see new ones beginning operation. To me, that is just amazing.”

The numbers back up the rebound. Excluding LEDs, the installed capacity of 200mm fabs will reach about 5.3 million wafers per month (wspm) in 2018, almost matching the 2007 peak of 5.6 million wspm. As shown in Figure 1, By 2019 as new 200mm fabs start up in China, 200mm wafer production will surge beyond the previous 2007 peak, a surprising achievement for a wafer generation that began more than 25 years ago. Figure 2 shows how capacity, which held steady for years, is now on the increase.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Case in point: On the opening day of Semicon West, Beijing Yangdong Micro announced a new OLED 200mm fab that will be opening in the second half of 2018 to make OLED drivers, according to Dieseldorff.

Over the past few years, Japan-based companies have closed 10 200mm fabs, mostly outdated logic facilities, while expanding production of discrete power and analog ICs on 200mm wafers. But with China opening several new 200mm fabs and the expansions of existing 200mm fabs worldwide, SEMI sees an additional 274,000 wafer starts per month of 200mm production over the 2015-2018 period, adding expansions and additional fabs, and subtracting closed facilities.

“One message from our research is that we believe the existing 200mm fabs are full. Companies have done what they can to expand and move tools around, and that is coming to an end,” he said. SEMI reckons that 19 new 200mm fabs have been built since 2010, at least six of them in China.

SEMI’s Christian Dieseldorff.

SEMI’s Christian Dieseldorff.

Dieseldorff touched on a vexing challenge to the 200mm expansion: the availability of 200mm equipment. “People have problems getting 200mm equipment, used and even new. The (200mm) market is not well understood by some companies,” he said. With a shortage of used 200mm equipment likely to continue, the major equipment companies are building new 200mm tools, part of what Dieseldorff described as an “awakening” of 200mm manufacturing.

 

China is serious

Sam Wang, a research vice president at Gartner who focuses on the foundry sector, voiced several concerns related to 200mm production at the SEMI/Gartner symposium. While SMIC (which has a mix of 200mm and 300mm fabs) has seen consistently healthy annual growth, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

The challenge, he said, is for China’s foundries which rely largely on legacy production to grow revenues in a competitive market. And things are not getting any easier. While production of has shown overall strength in units, Wang cautioned that price pressures are growing for many of the ICs made on 200mm wafers. Fingerprint sensor ICs, for example, have dropped in price by 30 percent recently. Moreover, “the installation of legacy nodes in 300mm fabs by large foundries has caused concern to foundries who depend solely on 200 mm.”

But Wang emphasized China’s determination to expand its semiconductor production. “China is really serious. Believe it,” he said.

New markets, new demand

The smart phone revolution has energized 200mm production, adding to a growing appetite for MEMS sensors, analog, and power ICs. Going forward, the Internet of Things, new medical devices, and flexible and wearable products may drive new demand, speakers said at the symposium.

Jason Marsh, director of technology for the government and industry-backed NextFlex R&D alliance based in San Jose, Calif., said many companies see “real potential” in making products which have “an unobtrusive form factor that doesn’t alter the physical environment.” He cited one application: a monitoring device worn by hospital patients that would reduce the occurrence of bed sores. These types of devices can be made with “comparatively yesteryear (semiconductor) technology” but require new packaging and system-level expertise.

Legacy devices made on 200mm wafers could get a boost from the increasing ability to combine several chips made with different technologies into fan out chip scale packages (FO CSPs). Bill Chen, a senior advisor at ASE Group, showed several examples of FO CSPs which combine legacy ICs with processors made on leading-edge nodes. “When we started this wafer-level development around 2000 we thought it would be a niche. But now about 30 percent of the ICs used in smart phones are in wafer-level CSPs. It just took a lot of time for the market forces to come along.”

More coverage from this year’s SEMICON West can be found here.

A major theme at SEMICON West 2016 is Smart Manufacturing, a.k.a. Industry 4.0 and Industrial IoT (IIoT). One definition of smart manufacturing, said Tom Salmon, the SEMI vice president of collaborative technology platforms, is the use of production and sensor data with manufacturing technologies to enable adaptability in processing. It encompasses automation, data exchange, and the transfer of product design data and manufacturing state data.

SEMI estimates that by 2020 there will be about a billion IoT devices at work in manufacturing facilities. By 2020, global manufacturers will invest $70 billion in IoT solutions that year, compared with $29 billion in 2015.

Figure 1. What the future may look like for smart manufacturing in the semiconductor industry.

Figure 1. What the future may look like for smart manufacturing in the semiconductor industry.

Currently, these devices are used largely to track factory assets, to consolidate control rooms, and to increase analytics functionality through predictive maintenance. The goal is that product design data and manufacturing state data will travel through the manufacturing process with the product. This requires that data is communicated to product lifecycle systems at the product companies and to service providers simultaneously.

A number of SEMI standards are facilitating this shift, including Equipment Data Acquisition (EDA), to improve and facilitate communication between manufacturer’s data gathering software applications and factory equipment.

SEMI kicked off an advisory council around smart manufacturing, and will coordinate a Smart Manufacturing symposium at SEMICON West on Wednesday, July 14, and again at SEMICON Europa on Oct. 25 in Grenoble, France.

Thomas Sonderman, vice president/GM of Rudolph Technologies’ software business, said the advisory council links the fabless and the equipment OEM supplier communities. One goal, Sonderman said, is “to help understand what’s required to really take on these concepts, and turn them into something that people can use to improve their overall fab efficiency.”

At the Smart Manufacturing Symposium, Sonderman will discuss what he calls traceability: optimizing the supply chain by blending IoT technologies. How information is acquired and used for Big Data predictive analytics and machine learning is one key aspect. “How do you turn data into some kind of actionable intelligence? I think the idea is to get some consensus around what it actually is, and then what’s required to make it successful,” Sonderman said.

Data security is also important. Data that comes out of fabs is of interest to suppliers, the fabless community and IP companies, among others who create a virtual IDM. “How does a Qualcomm get access to their relevant information, and on the other side, how does a company like Tokyo Electron Ltd. (TEL) or Applied Materials or Lam Research get access to that same information so that everybody can make the right decisions and shift the paradigm from reactive to a predictive/proactive approach.

“We need to go from ‘Hey, I have this problem. What caused it? How can I go fix it,’ to ‘What kind of analysis do I need to do to run my business? What kind of business intelligence is required to run the business, and how can I create analytical scenarios so that I can make sure that I have the information relevant to me to make decisions I need to minimize my time to market, and maximize my profitability?’”

In order for smart manufacturing to succeed, companies must be able to build confidence that they can share data securely. (At Wednesday’s symposium, NextNine, an Israeli IT security company, will present its work with TEL, several U.S. security agencies, and others concerned with moving information around securely).

One opportunity, Sonderman said, is to provide information-linking capabilities to 200mm and smaller wafer manufacturers, making RF filters, sensors, and other products.

“They don’t have a lot of the traditional capabilities that you come to expect. The idea is to link their information together but do it in a way where you can adapt it into those older facilities,” he said.

Rather than use a standard SECS/GEM interface, some tool data can be acquired wirelessly.

“There are all types of information that are relevant to the products, and if you think about what goes on a lot in the fabs it is linking what goes on in the product to what’s going on inside the tools. At legacy or non-leading-edge technology fabs, some of this in itself is a challenge,” he said.

Manufacturers also seek to link metrology data, with two different threads of information coming in: one from wafer-level metrology, and another stream of information from the equipment, which collects data each time the wafer crosses that piece of equipment. Also relevant is product information, including processes that can run multiple products. Figure 1 shows how this kind of data may be collected and shared in the future.

“The concept here is that you link these together in threads and then you create what we call the thread synchronization engine, which allows taking all of this relevant information and create a tapestry of data, which is a very pure data set that’s very representative of the combination of all these different factors,” Sonderman said.

The same types of information threads are woven together in the back-end (packaging) operations, where advance analytics are becoming as essential as in front-end processes.

Analytics are multifaceted, involving everything from visualization, data mining, spatial pattern recognition, and virtual metrology information. “Ultimately what I’m doing is trying to create a wafer-level signature and a tool-level signature and combine those together to create some kind of information I can take action on. That’s the actionable Data Now concept,” he said.

The goal is to combine information, separating the signal from the noise, and then analyze the data to ascertain whether or not a given process step or combination of process steps has contributed to yield loss. By drilling down into the shared data, engineers can discover whether a tool or set of tools is causing the problems.

“This is where things get really interesting. First, you have got to link everything together across the supply chain. Then you have to start looking at how do I drill down inside the equipment?” he said.

Large fabs with literally thousands of tools in operation are collecting huge amounts of information, essentially time series-based data. Linking tool information into an analytical combination with wafer-level information (what was going on inside the tool when those wafers were processed) is a powerful way to improve efficiencies. “That’s where this combination of big data analytics and traditional real time FDC is coming together,” Sonderman said.

To make this work, companies need a Big Data architectural environment, which combines structured data (in many cases in an Oracle database) with unstructured data (often text data, such as maintenance logs). Finally, there is a third space, a combination of time series-based data, such as images and spatial patterns.

The challenge, Sonderman said, is to link all the data together, standardizing the data so that it can be matched with various machine-learning algorithms. “From that I can analyze the data and start spitting out useful information that people can take action on,” he said.

To do that, the industry must deal with the security challenge. “There are ways to solve that challenge, but if we don’t solve that as an industry — and it really is an industry challenge — then we’re going to be handcuffed in terms of being able to take this technology to its ultimate realization. I think that’s now become the priority, versus preparing for the next wafer size and all that,” Sonderman said.

The health of the semiconductor industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong semiconductor market growth without at least “good” worldwide economic growth to support it. Consequently, IC Insights expects annual global semiconductor market growth rates to continue to closely track the performance of worldwide GDP growth (Figure 1).  In its upcoming Mid-Year Update to The McClean Report 2016 (to be released at the end of July), IC Insights forecasts 2016 global GDP growth of only 2.3%, which is below the 2.5% level that is considered to be the global recession threshold.

Figure 1

Figure 1

In many areas of the world, local economies have slowed.  China, which is the leading market for personal computers, digital TVs, smartphones, new commercial aircraft, and automobiles, is forecast to continue to lose economic momentum in 2016.  Its GDP is forecast to increase 6.6% this year, which continues a slide in that country’s annual GDP growth rate that started in 2010 when growth rates exceeded 10%.

IC Insights believes that the worldwide economy will be negatively impacted, at least over the next year or two, by the Brexit vote this past June.  At this point, since the U.K. is unlikely to officially be able to leave the European Union (EU) for a couple of years, the biggest negative effect on economic growth is the uncertainty of the entire situation.  Some of the uncertainty created by the vote includes:

•    Whether the U.K. will actually leave the EU.  Since the Brexit vote is not legally binding, and still needs to be approved by the U.K. government, there is uncertainty if its departure from the EU will actually happen.

•    Whether the U.K. will come apart itself.  There are rumblings about Scotland breaking away from being a part of the U.K. in order for it to remain as part of the EU.

•    What trade deals will be made by the U.K. if it does leave the EU?  As part of its exit from the EU, the U.K. will need to establish numerous new trade deals with the EU.  There is tremendous uncertainty regarding whether these deals would have a positive or negative effect on the U.K. economy.

•    Will other countries follow the U.K. and depart from the EU?  Anxiety persists over whether the EU will fall apart as other countries attempt their own exit.  Some countries mentioned as possibly following the U.K. out of the EU include the Netherlands (Nexit), France (Frexit), Italy, Austria, and Sweden (Swexit).

The other major “culprit” dragging down semiconductor industry growth this year is the very weak DRAM market.  At $45.0 billion, the DRAM market was the largest single product category in the semiconductor industry in 2015.  IC Insights forecasts that the DRAM market will register a 19% drop of $8.5 billion this year to $36.5 billion.  The DRAM market alone is forecast to shave three percentage points off of total semiconductor market growth this year. Semiconductor market growth excluding DRAM is forecast to be +2%.

Most of the DRAM market decline expected for this year is due to a rapid decline in DRAM pricing over the past 18 months.  For 2016, the average price for a DRAM device is forecast to drop to $2.55, a steep 16% decline as compared to 2015’s DRAM ASP of $3.03. Further trends and analysis relating to semiconductor market forecasts through 2020 will be covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.