Tag Archives: letter-pulse-top

By James Hayward, Technology Analyst, IDTechEx

With hype around some of the core wearable technology sectors beginning to wane, IDTechEx have released their latest analysis of this diverse and growing industry in their brand new report Wearable Technology 2016-2026. The report finds the market to be worth over $30bn in 2016, with over $11bn of that coming from newly popular products including smartwatches and fitness trackers. However, despite the total market growing to over $150bn by 2026, IDTechEx forecast shake-ups in several prominent sectors, with commoditization hitting hard, and product form factors changing rapidly.

Global wearable technology forecast summary, including 39 forecast lines covering all prominent products today (e.g. smartwatches, fitness trackers, smart eyewear, smart clothing, medical devices and more), but also to many incumbent products (e.g. headphones, hearing aids, basic electronic watches and more). Source: IDTechEx Research report Wearable Technology 2016-2026.

Global wearable technology forecast summary, including 39 forecast lines covering all prominent products today (e.g. smartwatches, fitness trackers, smart eyewear, smart clothing, medical devices and more), but also to many incumbent products (e.g. headphones, hearing aids, basic electronic watches and more). Source: IDTechEx Research report Wearable Technology 2016-2026.

The IDTechEx report covers these trends in granular detail, including 39 separate forecast lines by product type and 60 formal company profiles and interviews compiled from primary research by IDTechEx’s expert analysts. The report also covers all of the industry megatrends that are driving innovation, demand and development, as well as describing application sectors including fitness & wellness, elite sportswear, healthcare & medical, infotainment, commercial, industrial, military, and others. For each, general sector-wide themes are described, but also detailed case studies are used to explain value propositions, end user needs and unmet problems that are driving the market forward.

Fuelled by a frenzy of hype, funding and global interest, wearable technology was catapulted to the top of the agenda for companies spanning the entire value chain and world. This investment manifested in hundreds of new products and extensive tailored R&D investigating relevant technology areas. However, the fickle nature of hype is beginning to show, and many companies are now progressing beyond discussing “wearables” to focus on the detailed and varied sub-sectors. Within this report, we include sections on each key of these key product areas, including fitness trackers, smartwatches, smart clothing, smart eyewear (including AR and VR), smart skin patches, headphones and more. For each, the key trends are discussed, the key players characterised, and qualified market forecasts provided.

IDTechEx’s expert analyst team has been covering this topic for over three years, including device level studies, but also looking to the component level at displays, sensors, batteries & power solutions, microcontrollers, e-textiles and haptics. This understanding of the entire value chain is used to qualify the market forecasts, and particularly when looking at the future of personal communication devices.

In a unique aspect of this report, IDTechEx outlines a long term case for standalone wearable communication devices as a future evolution of the smartphone. Today, most smartwatches and many fitness trackers still rely, at least partially, on a connection to a smartphone hub. The ubiquity of the smartphone as a central platform has been a key enabler for growth in wearables so far, but all of the largest manufacturers now look to a future, where the hub itself may become wearable. In the report, the authors describes the growth central, personal hub providing connectivity to peripheral devices, whether they be displays, sensor platforms or otherwise. With many smartwatches already beginning to move in this direction, we extend this case further providing a 10 year forecast for growth of devices of this type.

This is the most thorough and comprehensive report covering the entire wearable technology ecosystem. It provides detailed description of all of the hardware challenges and opportunities across the varied device types, and draws from IDTechEx’s case study database of around 1000 companies in the wearable technology value chain. The report lists around 500 companies actively making products (both hardware and software) to support this report. For full details of Wearable Technology 2016-2026, including the table of contents, please see www.IDTechEx.com/wearable.

 

According to the latest market research report by Technavio, the semiconductor chip handler market is expected to grow at a CAGR of over 4% until 2020.

In this report, Technavio covers the present scenario and growth prospects of the global semiconductor chip handler market for 2016-2020. To calculate the market size, we consider the revenue generated from the sales of automated test equipment and the contribution of chip handlers in the automated test equipment market.

“A large number of fabless semiconductor companies are increasing the net aggregate demand for semiconductor ICs, creating the demand for automated test equipment. An increase in test houses has resulted in a rising number of potential automated test equipment customers, boosting revenue sales of market vendors,” said Asif Gani, one of Technavio’s lead industry analysts for semiconductors.

Semiconductor chip handler market in APAC: largest region

The global chip handler market in APAC was valued at USD 469.8 million in 2015. Taiwan, South Korea, China, and Japan are the key countries contributing to the growth of this region. The presence of prominent semiconductor foundries, such as Taiwan Semiconductor Manufacturing Company, United Microelectronics Corporation, and Semiconductor Manufacturing International, is creating the demand for chip handlers in APAC. The increase in the demand for consumer electronics and the rollout of LTE technology have led to an expansion of LTE base station infrastructure in China, increasing the demand for semiconductor ICs. These ICs need to be tested to avoid glitches and snags, thereby creating the demand for chip handlers.

The presence of prominent mobile and consumer electronic device manufacturers such as Samsung, LG, Fujitsu, and Panasonic in APAC is supporting the demand for semiconductor devices and thereby the demand for chip handlers in the region.

Semiconductor chip handler market in the US: second largest region

The global chip handler market in the US was valued at USD 104.4 million in 2015. The sports nutrition market in Europe is growing steadily. The increase in the demand for communication devices, such as smartphones and phablets, and automobile applications has been driving the production of semiconductor ICs in the US. The presence of few prominent semiconductor manufacturers, such as GlobalFoundries and Intel that fabricate wafers of sizes 200 nm and 300 nm, will create the demand for chip handlers in the nation.

Semiconductor chip handler market in Europe

The global chip handler market in Europe was valued at USD 43.96 million in 2015. Infineon Technologies, NXP Semiconductors, and STMicroelectronics are among the semiconductor manufacturing companies that account for the majority market share in this region. However, Europe will contribute low revenue to this market during the forecast period due to small concentrations of semiconductor IC manufacturers compared to APAC and the US. In addition, the Euro crisis in 2009 compelled many manufacturers to shift their semiconductor manufacturing facilities to APAC due to the availability of cheaper resources. This is likely to reduce the demand for chip handlers in the region during the forecast period.

By Jean-Eric Michallet, Leti Vice President for Sales and Marketing

The pervasiveness of the Internet of Things (IoT) and its connections ranging from $1 objects to connected cars requires security to be reliable, simple, safe and affordable. Because the Internet of Things is made up of objects (hardware) connected to a network (software), security has to be factored in from the application or use’s conception. In short, assuring IoT security will require strategies to manage the entire value and supply chains.

Attendees at the recent Leti Innovation Day 2016 in Lyon, France, heard several variations of that message from industry experts and Leti scientists, against a backdrop of a proliferation of security and data threats.

Didier Lamouche, CEO of Oberthur Technologies, a provider of embedded security software products and services, noted industry forecasts of 10 billion connected devices shipped annually by 2020. This amounts to an exponential increase in security risks, as well. “This is the wave we have to catch,” he said.

Security is a brand problem

Recalling the 2013 data breach at Target in the U.S., in which 40 million credit and debit card numbers and 70 million items of customer personal information were compromised, Lamouche said that cybersecurity is not only a problem for security officers and CIOs. It has become a problem for CEOs and board of directors, as the 2014 resignation of Target CEO Gregg Steinhafel showed. In fact, he said, cybersecurity is becoming a brand problem, because of the severe damage fraud and data breaches can cause for a company.

Retail is not the only at-risk industry. Lamouche noted that more than 76 million Sony PlayStation user accounts were breached and 3.6 million connected vehicles in the U.S. and Europe have been hacked.

In recent years, “card not present” (CNP) transactions, primarily online purchases, accounted for approximately 65 percent of fraud in Europe, Australia and Canada, and 49 percent in the U.S., which still amounted to $6 billion in 2014.

Credits cards with continuously updated security codes

To address the growth of CNP fraud, Oberthur has developed MOTION CODE for credit card issuers. It secures online transactions by automatically and randomly updating a cryptogram security code on the back of the card. If the card is lost or stolen, it can be rendered useless quickly.

Keynoting the session on “Strengthening Security with Advanced Technologies,” Jean-Marie Saint-Paul, Europe application director for Mentor Graphics, outlined numerous security challenges involving hardware. 

Who can you trust?

Thieves looking for ways to steal money, companies looking for competitors’ vulnerabilities and even users “playing” with the system can create risks. The supply chain presents numerous risks, as well. Specific hardware challenges include:

  • A “vast space” of possible intrusions during IC, printed circuit board and embedded design and in the supply chain
  • Unknown bugs and frequent field updates that open back doors for attackers
  • The “fading of a trusted foundry” and proposed solutions that may not be viable
  • Counterfeit ICs that cause economic loss similar to yield loss discovered much later
  • For mission-critical apps, fake ICs that compromise devices risking security and safety

“Whatever structure we put in place, we have to put it in place with something we trust,” he said.

Digital disruption across the board

Borrowing information from IBM, Saint-Paul closed his presentation with a slide that highlights some of the most disruptive changes in business, industry and society at large that digital technology has enabled.

  • World’s largest taxi company owns no taxis (Uber)
  • Largest accommodation provider owns no real estate (Airbnb)
  • Largest phone company owns no telco infrastructure (Skype)
  • World’s most valuable retailer owns no inventory (Alibaba)
  • Most popular media owner creates no content (Facebook)
  • Fastest-growing banks have no actual money (SocietyOne)
  • World’s largest movie house owns no cinemas (Netflix)
  • Largest software vendors don’t write apps (Apple, Google)

The slide also asked when disruption will happen in semiconductors and electronics, when the world’s largest trusted foundry will own no fab or equipment, the top trusted contract manufacturer will own no assembly line and the leading secure electronics supplier will not purchase boards or chips. Will it be true? Maybe not, Saint-Paul said, but the industry needs some new models to reinvent itself.

Sameer Sharma, general manager of Intel’s IoT Group, said the IoT will provide pervasive, real-time intelligence from the physical world to data centers and the cloud: mobile devices via networks, and industrial and home applications via gateways. He cited a projection of 50 billion devices sharing 44 zetabytes of data.

Intel and Leti recently signed a multi-year collaboration agreement involving a variety of subjects such as making the IoT more secure, enabling 5G networks and device innovation, and driving the future of high-performance computing. 

85 percent of systems not connected

Combining revealing statistics from the past with projections about the direction the industry is headed, Sharma noted that the rapidly evolving digital era is spurring transformation across many fields, supported by a shift to open standards. Fixed-function ASICs are giving way to programmable architectures, dedicated appliances are now parts of virtualized systems, and purpose-built hardware is transforming into general-purpose hardware and software-defined functions.

Dramatically declining costs are a key driver for this transformation. In the past 10 years, the costs for sensors have fallen 2x, the cost of bandwidth has dropped 40x and the cost of processing 60x.

One of the most arresting facts Sharma shared relates to the huge potential, and need, for more hardware and software systems to keep up with the exponential growth of connected devices. Eighty-five percent of deployed systems are not connected and do not share data with each other or the cloud.

IoT threat landscape

Even so, Sharma said, attacks on IoT devices will increase rapidly due to hyper-growth in the number of connected objects, “poor security hygiene” and high value of data on those devices. A recent study of IoT devices showed that an average of “25 holes or risks of compromising the home network” were found on every device evaluated.

Sharma outlined a path to IoT security paved by infrastructure, end-to-end security, and 5G network and connectivity and standards. He said the Intel IoT Platform offers secure, scalable and interoperable building blocks for data acquisition, analytics and actions to improve business and peoples’ lives. Like other speakers, Sharma emphasized that security must be part of system concept and design.

“Security cannot be an add-on. Those days are gone,” he said.

Devices to protect biological, radiological and chemical data

Leti’s Alain Merle noted that privacy and security far outweigh other user concerns about connected devices. Integration in advanced technology, a focus of Leti R&D, is required, including use of security primitives, or low-level cryptographic algorithms. Secure IoT nodes face a complex array of potential weaknesses beyond physical attacks, such as attacks through communication interfaces, fault injection (glitches, light, laser, electromagnetism) and software, in which a single error can open the door to a hacker.

Beyond its cybersecurity programs, Leti is working with its partners to develop dedicated security devices to protect biological, radiological, chemical and weapons data. CESTI is Leti’s evaluation laboratory to determine whether security components and devices are designed and manufactured to prevent breaches and whether they are capable of withstanding attacks from terrorists, criminals or others.

The CESTI lab has evaluated products from leading companies such as SAFRAN, Samsung, ATMEL, STMicroelectronics, Gemalto, Oberthur and Inside Secure. The lab is part of Leti’s Strategic Security and Defense Programs, which promotes the development of innovative security solutions for information and communication (ICT) technologies for transfer to defense and commercial markets.

‘System approach with partners’

In her closing remarks, Leti CEO Marie Semeria noted that reliability, security and privacy are “must haves” to support the many key uses of digital technology. “Leti relies on a combination of hardware and software, so we pursue system approaches with our partners,” she said.

Focusing on micro- and nanotechnologies, architectures, tools and design methodologies, Semeria underlined that Leti is a worldwide recognized important center of competencies in developing innovations to propose efficient and reliable elements & architectures for emergent computing systems. She highlighted several recent Leti innovations for the Internet of Things and advanced computing for health, automotive and other sectors.

Leti has unique know-how and access to shielding, sensors, architectures and embedded software technologies for designing ASICs and SOCs for security applications. Moreover, its unique concentration of experts in materials, technologies integration, design and systems, even in biology and clinical domains, allows Leti to make the best trade offs possible between security, such as resistance to attacks, and application constraints, such as power, cost and performance.

Leti will celebrate its 50th anniversary next year as part of Leti Innovation Day in Grenoble.

The 2015 market for semiconductor silicon wafers fell 5.3% to $7.2B on a record 10.4 BSI Si shipped, according to a new report, “Silicon Wafers Market & Supply Chain 2016, a TECHCET Critical Materials Report.” The silicon demand outlook for 2016 is expected to increase 6.8% to 11.1 BSI, largely due to the strength of the memory market. Issues with wafer supply will likely continue, as demand for 300mm polished wafers increases beyond capacity. Certain 200mm wafers are also in a tight supply situation given strong demand growth from the discrete device fabs coupled with limited supplier capacity, as explained in TECHCET’s report. Declining ASPs are expected as competition for China’s 200mm wafer demand increases and the 300mm market continues its evolution toward polished wafer usage.

Although shipments of silicon by area recovered after 2009, prices have still not recov- ered to 2008 (pre-US housing / WW credit crisis) levels. TECHCET expects aggregate Si ASPs to fall slightly in 2016 before firming or modestly increasing in 2017.

SOI wafer price increases, which started in 2014 due to a temporary supply-demand im- balance, have stabilized as new capacity has come online. Some pricing pressure is anticipated in 2016 as new players vie for market share.

The timeline for 450mm wafer piloting has been pushed out to 2019 with a ramp in 2020. While Intel remains bullish, TSMC, Samsung and Global Foundries have not yet joined the 450mm investment track. As a result, only Shin Etsu Handotai (S.E.H.) and SUMCO have invested in 450mm wafer development to date.

The top 5 silicon wafer producers account for roughly 97% of 300mm polished and epi- taxial wafers sales (by revenue). S.E.H. and SUMCO together account for over 55% of that 300mm revenue and more than 60% of the top 5’s total sales. China has no appreciable market share in the wafer market however, although acquisitions could change this in the future.

For more information on the wafer market, including details on the SOI market, please see TECHCET’s Critical Materials Report on Wafers, at https://techcet.com/product/silicon-wafers/.

asmlThe Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced Martin van den Brink, president and chief technology officer at ASML Holding and renowned pioneer in semiconductor manufacturing technology, has been named the 2016 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the semiconductor industry in technology or public policy. Van den Brink will accept the award at the annual SIA Award Dinner on Thursday, Nov. 10 in San Jose, an event that will commemorate the 25thanniversary of the Noyce Award.

Many past award recipients will be in attendance to celebrate the anniversary, including the following semiconductor industry leaders and founders: Dr. Craig Barrett, Dr. Morris Chang, John Daane, Dr. John E. Kelly III, Stanley Mazor, Jim Morgan, Jerry Sanders, George Scalise, Mike Splinter, Ray Stata, Rich Templeton, and Pat Weber.

“Throughout his distinguished career, Martin van den Brink has been a true semiconductor industry innovator, champion, and visionary, pioneering optical lithography methods that have given rise to the smaller, faster, more efficient chips that underpin modern technology,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Martin’s myriad accomplishments over the last 30 years have strengthened our industry and fundamentally transformed semiconductor manufacturing. On behalf of the SIA board of directors, it is a pleasure to announce Martin’s selection as the 2016 Robert N. Noyce Award recipient in recognition of his outstanding achievements.”

During Van den Brink’s three decades at ASML, he has led transformative advances in optical lithography procedures used to manufacture semiconductors. Optical lithography, a microfabrication process in which light-sensitive chemicals are used to transfer circuit patterns onto chip wafers, is the primary technology used for the production of semiconductors and has allowed for the continued miniaturization of chips. Thanks in large part to Van den Brink’s technological leadership, ASML is now the world’s largest supplier of optical lithography equipment for the global semiconductor industry.

Van den Brink was one of ASML’s first employees, joining when the company was founded in 1984. He has held various engineering positions since that time, including Vice President, Technology and Executive Vice President, Marketing & Technology. He has served on ASML’s Board of Management since 1999 and was appointed President and CTO on July 1, 2013. Van den Brink earned a degree in Electrical Engineering from HTS Arnhem, and a degree in Physics from the University of Twente, the Netherlands.

“I’m extremely gratified to accept this honor and enter the company of previous Noyce Award recipients, many of whom I’m proud to call friends, colleagues, and mentors,” said Van den Brink. “Throughout my career, I have been privileged to work with some of the finest scientists, engineers, and researchers in the world, individuals who have helped strengthen the semiconductor industry, the tech sector, and the global economy. It is with them in mind that I thankfully accept this award and look forward to continuing to work alongside them to advance semiconductor innovation.”

The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel.

“I’m also pleased that we will be joined at this event by so many of the past winners of the Noyce Award who have built this industry and driven its success over the years,” Neuffer said. “This event will be a unique opportunity to celebrate the industry and the promise for the future.”

By Pete Singer, Editor-in-Chief

A new roadmap, the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS), aims to integrate fast optical communication made possible with photonic devices with the digital crunching capabilities of CMOS.

The roadmap, announced publicly for the first time at The ConFab in June, is sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI and the IEEE Electron Devices Society (EDS).

Speaking at The ConFab, Bill Bottoms, chairman and CEO of 3MT Solutions, said there were four significant issues driving change in the electronics industry that in turn drove the need for the new HITRS roadmap: 1) The approaching end of Moore’s Law scaling of CMOS, 2) Migration of data, logic and applications to the Cloud, 3) The rise of the internet of things, and 4) Consumerization of data and data access.

“CMOS scaling is reaching the end of its economic viability and, for several applications, it has already arrived. At the same time, we have migration of data, logic and applications to the cloud. That’s placing enormous pressures on the capacity of the network that can’t be met with what we’re doing today, and we have the rise of the Internet of Things,” he said. The consumerization of data and data access is something that people haven’t focused on at all, he said. “If we are not successful in doing that, the rate of growth and economic viability of our industry is going to be threatened,” Bottoms said.

These four driving forces present requirements that cannot be satisfied through scaling CMOS. “We have to have lower power, lower latency, lower cost with higher performance every time we bring out a new product or it won’t be successful,” Bottoms said. “How do we do that? The only vector that’s available to us today is to bring all of the electronics much closer together and then the distance between those system nodes has to be connected with photonics so that it operates at the speed of light and doesn’t consume much power. The only way to do this is to use heterogeneous integration and to incorporate 3D complex System-in-Package (SiP) architectures.

The HITRS is focused on exactly that, including integrating single-chip and multi­chip packaging (including substrates); integrated photonics, integrated power devices, MEMS, RF and analog mixed signal, and plasmonics. “Plasmonics have the ability to confine photonic energy to a space much smaller than wavelength,” Bottoms said. More information on the HITRS can be found at: http://cpmt.ieee.org/technology/heterogeneous-integration-roadmap.html

Bottoms said much of the technology exists today at the component level, but the challenge lies in integration. He noted today’s capabilities (Figure 1) include Interconnection (flip-chip and wire bond), antenna, molding, SMT (passives, components, connectors), passives/integrated passive devices, wafer pumping/WLP, photonics layer, embedded technology, die/package stacking and mechanical assembly (laser welding, flex bending).

Building blocks for integrated photonics.

Building blocks for integrated photonics.

“We have a large number of components, all of which have been built, proven, characterized and in no case have we yet integrated them all. We’ve integrated more and more of them, and we expect to accelerate that in the next few years,” he said.

He also said that all the components exist to make very complex photonic integrated circuits, including beam splitters, microbumps, photodetectors, optical modulators, optical buses, laser sources, active wavelength locking devices, ring modulators, waveguides, WDM (wavelength division multiplexers) filters and fiber couplers. “They all exist, they all can be built with processes that are available to us in the CMOS fab, but in no place have they been integrated into a single device. Getting that done in an effective way is one of the objectives of the HITRS roadmap,” Bottoms explained.

He also pointed to the potential of new device types (Figure 2) that are coming (or already here), including carbon nanotube memory, MEMS photonic switches, spin torque devices, plasmons in CNT waveguides, GaAs nanowire lasers (grown on silicon with waveguides embedded), and plasmonic emission sources (that employ quantum dots and plasmons).

New device types are coming.

New device types are coming.

The HITRS committee will meet for a workshop at SEMICON West in July.

FormFactor, Inc. today announced that it has completed the acquisition of Beaverton, Oregon-based Cascade Microtech, Inc.

“By completing the acquisition of Cascade Microtech, FormFactor transforms into a broader test and measurement market leader with significant scale and increased diversification,” said Mike Slessor, FormFactor’s President and Chief Executive Officer. “Against a robust demand environment for the combined company’s products and technologies, we will benefit from significant financial synergies, driving improved gross margins, profitability and earnings accretion on a non-GAAP basis in the second half of 2016 and beyond,” added Slessor.

In conjunction with this acquisition, FormFactor is appointing Mr. Ray Link to its board of directors, effective June 27, 2016. Mr. Link, formerly a member of the Cascade Microtech’s board of directors, brings his significant financial and operational management experience with publicly held companies in the technology sector. He also currently serves on the board of directors of Electro Scientific Industries, Inc., and nLight Corporation.

The former shareholders of Cascade Microtech approved of the transaction on June 23, 2016. At the effective time of the acquisition, the outstanding shares of Cascade Microtech common stock were each cancelled and converted into the right to receive $16.00 in cash, without interest, and 0.6534 of a share of FormFactor common stock. The total consideration payable on the cancelled shares consists of approximately 10.5 million shares of FormFactor common stock and approximately $255.9 million in cash to former Cascade Microtech shareholders. As a result of the acquisition, Cascade Microtech shares will cease to be traded on the NASDAQ Global Market effective today, June 24, 2016.

In connection with the acquisition, FormFactor entered into a Credit Agreement with HSBC Bank USA, National Association, as administrative agent, co-lead arranger, sole bookrunner and syndication agent, and other lenders that may from time to time be a party to the Credit Agreement. Pursuant to the Credit Agreement, the lenders have provided FormFactor with a senior secured term loan facility of $150 million to finance a portion of the cash used to complete the transaction and pay fees and expenses related to the facility.

Needham & Company, LLC, acted as financial advisor and Davis Polk & Wardwell LLP acted as legal counsel to FormFactor. Stifel, Nicolaus & Company, Incorporated, acted as financial advisor and Perkins Coie LLP acted as legal counsel to Cascade Microtech.

By Paula Doe, SEMI

With many disruptive changes occurring in the electronics supply chain, the one with the biggest impact may come from smart manufacturing and the emergence of the digital supply chain.

“The digital supply chain is the next breakthrough opportunity for the industry,” says John Kern, Cisco Systems SVP, Supply Chain, who will give the opening keynote at SEMICON West 2016 (July 12-14) at Moscone Center in San Francisco. “It’s the biggest area of investment for us now because it’s where we see the most potential.” The ability to leverage data, cloud, collaboration and mobility are making it possible to eliminate, simplify and automate processes, orchestrate activities across the supply chain in real time, and empower the workforce to focus on higher value work.

Cisco began its own journey to a digital supply chain with an update of its enterprise resource planning (ERP) system.It targeted several use cases to improve processes, such as using data to manage energy consumption within a factory to drive productivity and improve sustainability. Another was automating test processes to improve quality and reduce capital costs. But now Cisco has moved on to a broader view, of automating systems so employees don’t have to spend time gathering the information, but instead can focus on analyzing the information presented to them. “That will be the big game changer,” Kern contends.

Another example is the Cisco Supplier Collaboration Platform, which allows suppliers to see directly into their supply chain data so they can fix issues that arise, such as over or under supply directly ─ without all the usual escalations, email exchanges and delays. “There’s one single source of truth for ‘supply and demand’ that everyone can see, minimizing ‘the bull whip’ effect and enabling real-time response,” he notes.

This Supply Chain digitization is happening in concert with a disruption in business models all across the sector, as users shift from buying physical assets to buying outcomes, and paying as they receive the benefits. “The impact of the cloud and the service model is changing the way we think about supply chains,” say Kern. “We need to be able to offer any options our customers want, whether it’s hardware, software or solutions, and in any way they want to consume. Our supply chain has to adapt rapidly to enable these multiple business models.” Kern will elaborate on the topic at SEMICON West on July 12 as part of the executive events. SEMICON West also will be presenting eight business and technology forums. To register for SEMICON West 2016, visit www.semiconwest.org. For a limited time, register for only $100 (includes admission to keynotes, TechXPOTs, Silicon Innovation Forum, World of IoT Theater, 700 exhibits, and Intersolar).

SMIC acquires LFoundry


June 27, 2016

Semiconductor Manufacturing International Corporation, the largest and most advanced foundry in mainland China, jointly announces with LFoundry Europe GmbH (“LFE”) and Marsica Innovation S.p.A. (“MI”), the signing of an agreement on June 24, 2016 to purchase a 70% stake of LFoundry for a consideration of 49 million EUR.

LFoundry is an integrated circuit wafer foundry headquartered in Italy, which is owned by LFE and MI. At the closing, SMIC, LFE and MI will own 70%, 15% and 15% of the corporate capital of the target respectively. This acquisition benefits both SMIC and LFoundry, through increased combined scale, strengthened overall technology portfolios, and expanded market opportunities for both parties to gain footing in new market sectors.

This also represents the Mainland China IC foundry industry’s first successful acquisition of an overseas-based manufacturer, which marks a major step forward in internationalizing SMIC; furthermore, through this acquisition, SMIC has formally entered into the global automotive electronics market.

As the leading semiconductor foundry in Mainland China, in the first quarter of 2016, SMIC recorded profit for the 16th consecutive quarter with revenue of US$634.3 million, an increase of over 24% year-on-year. In 2015, SMIC recorded annual revenue of US$2.24 billion. In fiscal year 2015, LFoundry revenue reached 218 million EUR.

This acquisition will bring both companies additional room for business expansion. At present, SMIC’s total capacity includes 162,000 8-inch wafers per month and 62,500 12-inch wafers per month, which represents a total 8-inch equivalent capacity of 302,600 wafers per month. LFoundry’s capacity amounts to 40,000 8-inch wafers per month. Thus, by consolidating the entities, overall total capacity would increase by 13%; this combined capacity will provide increased flexibility and business opportunities for supporting both SMIC and LFoundry customers.

SMIC has a diversified technology portfolio, including applications such as radio frequency (“RF”), connectivity, power management IC’s (“PMIC”), CMOS image sensors (“CIS”), embedded memory, MEMS, and others—mainly for the communications and consumer markets. Complementarily, LFoundry’s key focus is primarily in automotive, security, and industrial related applications including CIS, smart power, touch display driver IC’s (“TDDI”), embedded memory, and others. Such consolidation of technologies will broaden the overall technology portfolios and enlarge the areas of future development for both SMIC and LFoundry.

Dr. Tzu-Yin Chiu, the CEO and Executive Director of SMIC said, “The successful completion of the LFoundry srl acquisition agreement is an important step in our global strategy. Both SMIC and LFoundry will mutually benefit from the shared technology, products, human talents and complementary markets. This will additionally expand our production scale and allows us to service the automotive IC market and for LFoundry to enter into China’s consumer electronics market, thus bolstering our overall development and growth. Through the acquisition, communication and cooperation in the semiconductor industry between China and Europe has been further enhanced, and contributes to the mutual success of the integrated circuit industry in both regions. In the future SMIC will continue to enhance, strengthen, and further expand leadership in the global semiconductor ecosystem.”

Sergio Galbiati, the Managing Director of MI and Chairman of LFoundry srl, said, “This is the beginning of a new era for LFoundry and our Italian fab. We are pleased to become part of a very strong worldwide player, SMIC. Together we can further improve LFoundry’s strength on optical sensor related technology, which is well recognized worldwide, and continue to contribute to the growth of technology in Europe, thanks to our partnerships with many relevant players. The agreement with SMIC will enable us to have a stronger level playing field in Europe.”

Günther Ernst, the Managing Director of LFE and CEO of LFoundry srl, said, “We have made significant efforts in achieving technology excellence. The agreement with SMIC will further enable us to better use our own manufacturing capacity and have access to SMIC’s extremely diverse technology offerings while taking advantage of SMIC’s commercial network and overall capacity. As part of SMIC, LFoundry will continue to pioneer technology to help our customers achieve success and drive value for our partners and employees around the world. We look forward to working closely with the SMIC team to ensure a smooth transition.”

By Douglas G. Sutherland and David W. Price

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

In the early stages of development, having more process control can help reduce both the number and duration of cycles-of-learning (the iterations required to solve a particular problem). In high volume manufacturing a well-thought-out process control strategy can increase baseline yield and, at the same time, limit yield loss due to excursions. At all stages, an effective process control strategy is required to ensure that the fab is operating at its lowest possible cost. In addition to minimizing production costs, adding process control steps can, counterintuitively, also minimize cycle time.

Figure 1 shows a conceptual plot of how cycle time would vary as a function of the number of process control steps. On the left hand side of the chart where there are no metrology and inspection (M&I) steps in place, the cycle time is effectively infinite. If a lot reaches the end of the line and has zero yield there is no way to isolate the problem. Theoretically one could isolate the problem by trial and error, but with only 100 process steps and only two parameters each, there would be 2100 (1.3 x 1030) possible combinations. Even testing one parameter per second, it would take much longer than the age of the universe to exhaust all possible combinations of the parameter space.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

Figure 1. Cycle Time (CT) versus the number of process control (metrology and inspection) steps. In zone 1, the fab is information starved and unable to find yield excursions and isolate the underlying problems. In zone 3, the fab is getting more information than it can use. In zone 2, the fab has achieved balance – with a number of process control steps that minimizes the cycle time.

As process control steps are added the cycle time comes down from an effectively infinite value to some manageable number. At some point the cycle time will reach a minimum value. Beyond this point, adding in further process control steps will actually cause the cycle time to increase linearly with the number of added steps. The optimal amount of process control will always be a trade-off between minimizing cycle time, minimizing excursion cost, and maximizing baseline yield. The latter two usually have a much greater financial impact.

Adding process control steps can reduce a fab’s cycle time, but how does that work? A full treatment of cycle time (Queuing Theory) is far beyond the scope of this article, however at a high level, it can be broken down into a few manageable components. The total cycle time (CT) is the sum of the queue time (the time a lot spends waiting for a process tool to become available) and the processing time itself. Since the processing time is fixed, the only way to reduce CT is to concentrate on the queue time (Q). From Queueing Theory it can be shown that Q can be expressed by the product of three separate functions4,

Q = f(u) f(a) f(v)                                                                                           eqn 1

where f(u), f(a) and f(v) are, respectively, functions of utilization, availability and variability. The first two functions will always be finite, therefore it becomes clear that Q = 0 only when f(v) = 0. Put another way, reducing variability in the fab reduces the queue time, and if we remove all variability from the system the queue time will drop identically to zero and the CT will be equal to just the processing time.

Figure 2 shows a plot of CT as a function of utilization for three different levels of variability: zero, medium and high. The Y-axis measures cycle time in units of total processing time called the X-factor. When the variability is zero all the lots move through the fab in lock-step; there is no increase in CT with increasing utilization and all tools could be run, theoretically, at 100 percent utilization. In this case the queue time is zero and the CT is equal to the total processing time for all the steps (CT=1). As soon as some variability is introduced, the CT starts to increase exponentially with utilization and the more variability there is, the more dramatic the increase becomes.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Figure 2. Cycle time versus Utilization for three different levels of variability: High, Medium and Zero.

Variability in the fab comes from many sources: in the lot arrival rate, in the frequency of maintenance requirements, and in the time required for that maintenance to be performed are just a few of the sources. An excursion—a lot that is out of control—affects all of the above.

Having more process control points will not immediately change the number of excursions in a fab but it will immediately improve the efficiency with which the fab reacts to them.

In fact, over time, having more process control points can also reduce the number of excursions because it increases a fab’s rate of learning.

Consider a lot that has been flagged for having a defect count that was beyond the control limit for process step N. If, as shown in figure 3a, there was another inspection point between process steps N and N-1, then the problem can be immediately isolated. Only the tool at step N (the process tool the offending lot went through) needs to be put down and only the lots that went through that tool since the last good inspection need to be put on hold for disposition.

By contrast, consider what would happen in figure 3b where the last inspection point was five steps ago at process step N-5. Practices differ from fab to fab, however in the worst case scenario, all ten tools that the lot went through would be put down and all lots that went through any of those tools would have to be put on hold. Instead of a minor disruption involving a single process tool and a few lots, entire modules and dozens of lots can be directly affected. Indirectly, it affects the entire fab.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3. (a) One process step between inspection points. (b) Five process steps between inspection points.

Figure 3 shows that implementing fewer inspection steps has a threefold impact on cycle time:

  1. More process tools are involved and must be taken offline
  2. Each process tool is down for a much longer period of time because it takes longer to isolate the problem
  3. More wafers are in the impacted section of the production line. These wafers must be dispositioned

The variability introduced by these three impacts will also propagate through the fab; they constrict the flow of work in progress (WIP) through the fab, creating a WIP bubble that affects the lot arrival rate (increased variability) at every station downstream. All of these factors contribute to fab-wide variability and because of the re-entrant nature of the process flow, they add to the cycle time of every single lot in the fab.

When an excursion occurs, the resulting disruption impacts the cycle time of every lot in the fab and it quickly becomes a vicious cycle. The more excursions that happen during a given lot’s cycle time, the longer that cycle time will be. And the longer the cycle time is, the more likely it is that that lot will be in the fab when the next excursion occurs.

Adding inspection steps will add a small, known amount of cycle time to those lots that get inspected, but due to sampling (not every lot gets inspected) it will have a much smaller impact on the average. When an excursion does occur, comparatively few process tools will have to be put down and the module owner will be able to isolate the problem much sooner. The total disruption to the fab (the variability) will be reduced and the cycle time of all lots will be improved.

This counter-intuitive concept has been borne out by several fabs that have both added inspection steps and reduced cycle time simultaneously. Adding process control steps contributes to fab efficiency on several levels: accelerating R&D and ramp phases, increasing baseline yield, limiting the duration of excursions, and reducing cycle time. In short, a better-controlled process is a more efficient process.

The next article in this series will discuss the impact of process control to cycle time on so-called “hot lots” typically run during early ramp.

References:

  • “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014.
  • “Process Watch: Time is The Enemy of Profitability,” Solid State Technology, May 2015.
  • “Economic Impact of Measurement in the Semiconductor Industry,” Planning Report 07-2, National Institute of Standards and Technology, U.S. Department of Commerce, December 2007.
  • Hopp, W. J., and Spearman, M. L. Factory Physics (2nd). (New York: Irwin, McGraw-Hill, 2001), 325.

About the Authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.