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Atomic force microscopy is essential for obtaining three-dimensional information of crystal defects.

ARDAVAN ZANDIATASHBARA, PATRICK A. TAYLORB, BYONG KIMA, YOUNG-KOOK YOOA, KEIBOCK LEEA, AHJIN JOC, JU SUK LEEC, SANG-JOON CHOC, and SANG-IL PARKC

a) Park Systems Inc., Santa Clara, CA, USA b) SunEdison Semiconductor, St Peters, MO c) Park Systems Corp., Suwon, Korea

As integrated devices continue to shrink, incoming bare silicon wafer defectivity requirements become more and more stringent. The inspection of bare silicon wafers for surface defects is predominantly accomplished by measuring the difference in laser light scattering (LLS) between the clean surface and a surface defect, where the intensity of the scattered signal is compared to the LLS of a standard latex sphere. The actual surface defectivity can originate from added particles, topological defects, and crystal imperfections. To be able to reduce the number of defects one must know the source of the defect. LLS inspection can only give defectivity counts and a relative size. Therefore, one must rely on defect review techniques such as SEM and AFM to determine the nature and origin of the defects.

SEM provides two-dimensional aerial images of the defects which lacks the information about depth or height of the defects. On the other hand, AFM can provide three- dimensional topography images of the defects with the highest vertical resolution among all techniques[1]. The shortcomings of conventional AFM systems were low throughput, limited tip life, and arduous efforts for locating the DOI on the 300 mm wafers. To address the limitations of conventional of AFM systems for defect review, ADR AFM has been introduced for 300 mm wafers recently[2].

We used ADR AFM in this study for studying the defects found by LLS inspection tool.
In this study we focus on very small crystal imperfec- tions which are not easily observed by LLS without some means to make them larger. We have used a decorative etching technique to highlight crystal imperfections to be studied by LLS, SEM, and AFM. The defect analysis can only be accomplished with accurate and reproducible defect coordinate transfer between analysis tools. Here we show how we have successfully and reliably found and characterized the decorated defects by ADR AFM.

ADR AFM procedure

The process in ADR AFM is depicted in FIGURE 1. During this process, the defects of interest are located accurately and imaged non-destructively. Two factors are essential in order to achieve these objectives. First proper linkage between ADR AFM and LLS inspection tool is required to minimize the positioning errors and locate the defects accurately. The linkage for blank wafers is achieved by sample coordinate alignment. Generally there are no alignment markers or fiducials available on blank wafers to be used for alignment. Therefore ADR AFM uses specialized vision to perform the sample alignment properly. Another important factor in AFM defect review is non-contact mode imaging which is required for non-destructive imaging of the samples while preserving AFM tip life such that the tip can last throughout the process for multiple defects.

FIGURE 1. The schematic shows ADR AFM process for this study. After completing coordinate mapping, ADR AFM will automatically perform survey scan, zoom-in scan, processing, analysis, and classification for each defect.

FIGURE 1. The schematic shows ADR AFM process for this study. After completing coordinate mapping, ADR AFM will automatically perform survey scan, zoom-in scan, processing, analysis, and classification for each defect.

Coordinate alignment

Sample coordinate alignment is needed for proper linkage between the stage coordinates of ADR AFM andLLS inspection tool. In the case of blank wafers, no fiducial or alignment marker exists on the sample to be used for sample alignment. To overcome this challenge, a coarse alignment followed by a fine alignment is performed. In the coarse alignment, three randomly selected peripheral and the notch or an angular reference are selected to correct for translational and rotational errors. This is followed by a fine alignment to eliminate positioning errors due to non-affinity between the stage coordi- nates of ADR AFM and LLS inspection tool. A few large defects with known inspection coordinates are used for performing fine alignment. Since the defects are hardly visible in a standard AFM optical image, an enhanced vision is used to locate the defects in the optics of the ADR AFM and utilize the defects as aligner markers. Upon the sample alignment, ADR AFM is able to locate additional defects accurately. More details on coordinate alignment can be found in ref [2].

Enhanced vision

Enhanced vision is utilized during fine coordinate alignment to locate the defects in the optical vision of ADR AFM. The technique is developed based on well- known differential frame averaging of the optical frames collected from the sample surface at two accurately separated locations. The sample can be moved accurately since ADR AFM uses a separated Z and XY scanners configuration. This architecture was initially developed to eliminate the crosstalk between the XY and Z scanners (which has been a common artifact in tube scanner based AFM systems)[2]. In this setup, sample is moved by XY scanner while tip is following the sample topography by Z scanner. In enhanced vision, the optical frames of the sample are collected at two precisely separated locations, and then the final frame is generated from the difference between the collected frames. The resulting frame possesses an enhanced contrast of surface details which are not easily observable in the standard vision of ADR AFM. A comparison between the frames collected by standard vision versus enhanced vision is depicted in FIGURE 2.

Screen Shot 2016-05-09 at 3.24.37 PM

Non-contact mode imaging

Non-contact mode is the standard imaging mode in ADR AFM. It is essential to maintain tip sharpness during the defect review process from the first to the last defect that is located and imaged. In addition to keeping tip costs low, well-maintained tip sharpness ensures consistent image quality and accuracy between the images of all defects during the process. It therefore enables the automated system to uninterruptedly locate and image the defects with a high throughput. In order to perform non-contact mode imaging, the AFM cantilever is oscillated at its resonance frequency. The oscillating cantilever is brought close enough to the sample that the oscillation amplitude reduces to a pre-defined set point due to the van der Waals tip sample interaction. ADR AFM maintains the oscillation amplitude to avoid tip contacting the sample. As the tip  scans the sample surface, the oscillation amplitude is maintained by moving the cantilever up and down with the Z scanner to maintain its tip sample interaction in attractive regime. More details on non-contact mode imaging can be found in reference[4]. Although ADR AFM’s functionality is based on non-contact mode imaging, it is capable of performing in other dynamic or contact imaging modes if needed.

Automatic defect search and imaging

The significant improvements in throughput of defect review are obtained by ADR AFM due to its fully automated process. Once defect coordinates from LLS inspection tool are entered into ADR AFM, coordinate alignment is performed, the defect is located and imaging starts for the list of selected defects. The process of locating and imaging the defects is fully automated. The automation includes locating the defect, tip-sample engagement, non-contact mode parameter optimization, survey scan, optimizing the scan size, final scan, processing, and defect classification. Defects can be classified into two groups of bumps and pits. Defects are typically located within ±10 μm of their LLS coordinates.

Sample preparation

Bare 300mm diameter CZ silicon wafers were treated with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to grow the crystal imperfections [3]. The size and shape of the decorated defects depends on the nature of the original defect as shown in FIGURE 3. Once decorated, the defect size is capable of being detected as LLS event. The LLS inspection tool locates and sizes the LLS events, providing the coordinates to be used by the SEM and AFM.

Screen Shot 2016-05-09 at 3.24.46 PM

Results

A wafer containing surface decorated defects was inspected by a LLS tool and 34 defects were selected to be reviewed by ADR AFM. The coordinates of the defects were entered to ADR AFM, coordinate alignment performed, and the defects were located and imaged by ADR AFM. The first 21 defects had been imaged by SEM before being studied by ADR AFM. However, SEM images only provide aerial two-dimensional view of defects without sufficient infor- mation on the defects depth and out of plane dimensions. The remaining 13 defects were not found by SEM despite the signal collected by the LLS tool. The summarized results of decorated defect study with ADR AFM and comparison with SEM results aredemonstrated in FIGURE 4. ADR AFM was able to find all the 34 defects including those that had not been found by SEM.

Screen Shot 2016-05-09 at 3.24.52 PM

The defects selected to be reviewed by ADR AFM belong to eight types according to their LLS signal. The tentative classification by the LLS tool is based on the defect’s light scattering which is dependent on morphology, depth, and presenece of a central defect. As the decorative etching process proceeds, crystal imperfections are exposed and etch at a different rate than the perfect crystal surface. Defects exposed at the initial stages of the etch are deeper and more developed than defects exposed late in the etching proccess. Defects with an inverted pyramid shape are generally deeper and posses higher LLS signal. They are classified as “Facet”. Defects with curved shape formed during the late stages of etching are shallower. These defects are classified as “Shallow”. Some defects are exposed at an intermediate point in the decorative etch and have some degree of faceted walls with curved bottom. This category is classfied as “Both”. Defects which have only started to be decorated have a very weak LLS signal and are classified as “Too shallow”. The defects are also categorized whether or not they have the center defect, hence, a total of eight defect types were identified. The defect classification is tabulated in FIGURE 5.

Screen Shot 2016-05-09 at 3.25.02 PM

As we go from left to right side of the table in figure 5, the LLS signal become weaker. This was attributed to the depth of defects and the sharpness of the defect’s edges. AFM images confirmed the depth difference between different classes of defects. Since the AFM images contain Z heights, we were able to use a banded color scale to depict the surface topography of the defects more accurately in 2D view.

Discussion

FIGURE 6 depicts a comparison between the data collected with SEM vs. AFM for the same defect. Primary SEM image provides an aerial 2D view of the defect. However, the shallow depth of the defect reaches the limitations of SEM, hence, poor contrast in the image. As indicated in Fig. 5, shallower defects were not found by SEM. A secondary electron image helps identify the center defect. Identification of center defect by secondary electron is possible only if the defect was found in primary SEM image.

Screen Shot 2016-05-09 at 3.25.07 PM

On the other hand, AFM image not only provides an aerial view of the defect, it also contains the height/depth values for each pixel. Therefore, more information can be obtained about the true topology of the defect by using a 3D repre- sentation of the AFM image or using a contoured color scale. Contoured color scales can also help understanding the topology of the defect in aerial view as shown in figure 5. As indicated before, AFM has the highest vertical resolution among all imaging techniques [1], hence, better contrast of AFM images in aerial view.

All of the 34 defects were found by ADR AFM including the 13 defects that were not found by SEM. FIGURE 7 depicts the AFM images a defect that was not found by SEM. The defect depth is below 4 nm and contains a center defect. This example indicates once again the limitation of SEM resolution in out of plane direction.

Screen Shot 2016-05-09 at 3.25.15 PM

It was indicated above that ADR AFM is a non-destructive imaging technique. It utilizes non-contact mode imaging for survey scan and final imaging scan. However, SEM beam can still modify the sample surface. FIGURE 8 indicates the sample contamination as a result of electron beam “burning” the surface during SEM imaging. These SEM burn-mark sizes are related to the SEM magnification. Figure 8 shows that several SEM magnifications were used in analyzing this defect.

Screen Shot 2016-05-09 at 3.25.30 PM

Summary

We have demonstrated the power of the ADR AFM to provide quality 3D information for defect review on bare silicon wafers. Crystal defects on surface of a 300 mm wafer are highlighted using a decorative etching technique. The surface defects are located by LLS inspection. Select defects of various classes are studies by SEM and ADR AFM. While shallow defects are not found by SEM, ADR AFM successfully found all the defects and provided high resolution three-dimensional topographical information of the defects. With the automated ADR AFM this type of analysis is simple and yet powerful.

References

1. G. T. Smith, Industrial Metrology: Surfaces and Roundness.: Springer, 2002.
2. Ardavan Zandiatashbar et al., “High-throughput automatic defect review for 300mm blank wafers with atomic force microscope,” in Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 94241X.
3. J. Libert and L. Fei, Method to Delineate Crystal Related Defects.: PCT Publication, WO2013055368(A1).
4. Ardavan Zandiatashbar, “Sub-angstrom roughness repeat- ability with tip-to-tip correlation,” NanoScientific, no. Winter, pp. 14-16, 2014.

The authors are with Park Systems Inc. (Santa Clara, CA and Suwon, Korea) and SunEdision Semiconductor in St Peters, MO. The lead author is Ardavan Zandiatashbara: [email protected]; phone 1 408 986-1110.

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $26.1 billion for the month of March 2016, a slight increase of 0.3 percent compared to the previous month’s total of $26.0 billion. Sales from the first quarter of 2016 were $78.3 billion, down 5.5 percent compared to the previous quarter and 5.8 lower than the first quarter of 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales increased in March for the first time in five months, but soft demand, market cyclicality, and macroeconomic conditions continue to impede more robust growth,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Q1 sales lagged behind last quarter across nearly all regional markets, with the Americas showing the sharpest decline.”

Regionally, month-to-month sales increased in Japan (4.8 percent), Asia Pacific/All Other (2.3 percent), and Europe (0.1 percent), but fell in China (-1.1 percent) and the Americas (-2.8 percent). Compared to the same month last year, sales in March increased in Japan (1.8 percent) and China (1.3 percent), but decreased in Asia Pacific/All Other (-6.4 percent), Europe (-9.8 percent), and the Americas (-15.8 percent).

“Eighty-three percent of U.S. semiconductor industry sales are into markets outside the U.S., so access to overseas markets is imperative to the long-term strength of our industry,” Neuffer said. “The Trans-Pacific Partnership (TPP) is a landmark trade agreement that would tear down myriad barriers to trade with countries in the Asia-Pacific. The TPP is good for the semiconductor industry, the tech sector, the American economy, and the global economy. Congress should approve it.”

March 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.03

4.89

-2.8%

Europe

2.66

2.67

0.1%

Japan

2.47

2.59

4.8%

China

8.02

7.93

-1.1%

Asia Pacific/All Other

7.83

8.01

2.3%

Total

26.02

26.09

0.3%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.81

4.89

-15.8%

Europe

2.96

2.67

-9.8%

Japan

2.55

2.59

1.8%

China

7.83

7.93

1.3%

Asia Pacific/All Other

8.57

8.01

-6.4%

Total

27.70

26.09

-5.8%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

5.75

4.89

-15.0%

Europe

2.77

2.67

-3.6%

Japan

2.57

2.59

0.8%

China

8.45

7.93

-6.1%

Asia Pacific/All Other

8.08

8.01

-0.8%

Total

27.62

26.09

-5.5%

Year-to-year percent change in world semiconductor revenues over the past 20 years.

Year-to-year percent change in world semiconductor revenues over the past 20 years.

By Lara Chamness, Industry Research and Statistics, SEMI

North America has a long and rich history of semiconductor manufacturing and innovation. As home to device manufacturers such as Intel, Texas Instruments, Micron, GLOBALFOUNDRIES, NXP (Freescale), Fairchild, Avago, Qorvo, Microchip, ON Semiconductor, significant operations of Samsung, and leading fabless companies such as Qualcomm, Broadcom, NVIDIA, AMD, Apple, Marvell, and Xilinx, North America continues to play an important role in advanced semiconductor manufacturing and in device and system design. SEMI’s Fab Forecast shows that North America accounts for 14 percent of Worldwide Installed Fab capacity (excluding discretes).

Source: SEMI (www.semi.org)

In terms of revenues, IC Insights recently announced, that companies headquartered in the United States continue to capture the bulk of IDM and Fabless IC Sales.

  • U.S. companies account for 51 percent of IDM Companies IC Sales in 2015
  • U.S. companies account for 62 percent of Fabless Companies IC Sales in 2015

Due to the presence of leading device manufacturers, North America represents a significant portion of the new equipment market, annual spending on average over the past five years has been in excess of $7 billion. Spending for new equipment is expected to be approach $6 billion this year.

Source: SEMI/SEAJ; Forecast, SEMI (www.semi.org)

With such a large installed fab base, North America also claims a significant portion of the wafer fab materials market.  Comparing global fab capacity to global wafer fab market share, North America represents 18 percent of the Wafer Fab Materials market compared to 14 percent of global fab capacity. This is due to the advanced device manufacturing that occurs in the region, which requires more process steps and advanced materials which fetch higher average selling prices.

Regional Wafer Fab Materials Markets

Source: SEMI (www.semi.org)

The equipment market is expected to increase about 10 percent in North America this year due to sizable investments by GLOBALFOUNDRIES, Intel and Samsung, while the Wafer Fab Materials Market is expected to remain flat this year relative to last year. As companies like Apple, Intel, Qualcomm continue to innovate, North America will remain an essential force in both device and systems design and in semiconductor manufacturing.

Plan to attend the SEMI/Gartner Market Symposium at SEMICON West 2016 on Monday, July 11, for an update on the semiconductor market outlook.

Revenue associated with the wireless competitive landscape continued to serve as a bright spot in the larger semiconductor market in 2015, growing almost 4 percent to over $56 billion, year over year, while total semiconductor revenue fell 2 percent to $347 billion during the same period. The wireless competitive landscape includes logic and analog semiconductors used in connectivity, mobile phones, media tablets, mobile infrastructure and other applications. However, due to slowing sales of smartphones and other wireless devices, the wireless competitive landscape faces a set of challenges that could result in similar or slower growth in 2016, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight.

wireless semiconductors

“Apple recently reported its fiscal second quarter results, and for the first time iPhone unit sales fell year over year, indicating the potential magnitude of the softness in the premium smartphone market,” said Brad Shaffer, senior analyst, mobile devices and networks, IHS Technology. “If the iPhone and other premium smartphones fail to gain enough traction to support growth in that market segment, it may be reflected in the underlying semiconductor market in 2016.”

According to the IHS Wireless Semiconductor Competitive Intelligence Service, the mobile handset integrated-circuit (IC) market is the largest segment in the wireless competitive landscape, comprising 62 percent of revenue in 2015 as the smartphone market continued to grow. “If unit shipments from Apple and other smartphone original equipment manufacturers continue to decline, the wireless competitive landscape could have a dragging effect on the larger semiconductor market in 2016. However, though currently too early in their lifecycles to make a material difference in the short term, emerging technologies like LTE-Advanced Pro or 4.5G could provide upside potential in the next 12 to 18 months,” Shaffer said.

Along with maturing growth rates in the smartphone market, Samsung, Apple, Huawei and other OEMs that are vertically integrated have varying degrees of internal semiconductor capabilities at their disposal — with the potential to supply their own smartphones and other OEMs as well. These internal design decisions tend to be cyclical in nature and can change from one product iteration to another, switching from internally-supplied components to third-party solutions.

“While this vertical integration has been especially evident in the premium smartphone tier, it helps to create a fiercely competitive environment in all market tiers, as it can limit the available market for third-party suppliers,” Shaffer said. “The increased competition resulting from a smaller market could impact core handset integrated-circuit prices in the entry-level and mid-range segments, with MediaTek, Spreadtrum and other suppliers vying for revenue share with market leader Qualcomm.”

IEEE, the world’s largest technical professional organization dedicated to advancing technology for humanity, today announced the launch of the International Roadmap for Devices and Systems (IRDS), a new IEEE Standards Association (IEEE-SA) Industry Connections (IC) program to be sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative in consultation with the IEEE Computer Society. Together, this group will ensure alignment and consensus across a range of stakeholders to identify trends and develop the roadmap for all of the related technologies in the computer industry.

The IRDS represents the next phase of work that began with the partnership between the IEEE RC Initiative and the International Technology Roadmap for Semiconductors 2.0 (ITRS 2.0). With the launch of the IRDS program, IEEE is taking the lead in building a comprehensive, end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software. The Methods of governance, reports, and strategic roadmaps developed by the ITRS and ITRS 2.0 will inform the IRDS within the IEEE-SA IC program.

“The computer industry has benefitted from roadmaps since it was first published in 1965,” said IEEE Fellow Thomas M. Conte, 2015 president, IEEE Computer Society; co-chair, IEEE Rebooting Computing Initiative; and Professor, Schools of Computer Science, and Electrical and Computer Engineering, Georgia Institute of Technology. “Bringing the IRDS under the IEEE umbrella will create a new ‘Moore’s law’ of computer performance, and accelerate bringing to market new, novel computing technologies.”

“The broad scope of IRDS spanning from base technology through systems and architecture will create an environment where known end-requirements will drive technological solutions and decrease the time to market for implementation, ultimately creating a new Moore’s law,” added IEEE Fellow and Senior Director, IEEE Future Directions, William R. Tonti. “The integration of the work of the IRDS into IEEE and governance of the semiconductor to system roadmap through the IEEE Rebooting Computing Initiative opens the door to innovative end-to-end computing solutions.”

“Over the past decade, the structure and requirements of the electronics industry have evolved well beyond the semiconductor’s industry requirements. In line with the changes in the new electronics ecosystem, the IRDS will build upon the past groundwork and move up a level to identify challenges and include recommendations on possible solutions,” said Paolo A. Gargini, IEEE Fellow and chairman, of IRDS. The IRDS will deliver a 15-year vision that encompasses systems and devices, setting a new direction for the future of the semiconductor, communications, IoE and computer industries.”

Participants in the IRDS will convene 12-13 May 2016 in Leuven, Belgium. Over the course of the two-day workshop, the group will review the roadmap activities of the Focus Teams (FT) and of the International Technology Working Groups (ITWG) and lay out plans for additional activities in 2016. Some of the fields of discussion include System Integration, Heterogeneous Integration, Connectivity, Future IC Devices and Factory Integration.

The IEEE Rebooting Computing Initiative is a program of the IEEE Future Directions Committee, designed to develop and share educational tools, events and content for emerging technologies.

IEEE-SA’s Industry Connections Program helps incubate new standards and related products and services, by facilitating collaboration among organizations and individuals as they hone and refine their thinking on rapidly changing technologies.

Nanoelectronics research center imec has announced that Dr. Gordon E. Moore, creator of the famous Moore’s law theory and co-founder of Intel, is the recipient of its lifetime of innovation award. Imec’s annual award recognizes Dr. Moore’s visionary view, unrivalled innovation, and his profound impact on the global electronics industry.

In 1965, Dr. Moore predicted that the number of components on an integrated circuit (IC) would double every year for the coming 10 years, thereby making ICs and computer processing simultaneously faster, cheaper, and more powerful. In 1975, Dr. Moore revised the forecast rate to approximately every two years. Moore’s law turned out to be incredibly accurate, growing beyond its predictive character to become an industry driver that holds true today, 50 years later. Keeping up with Moore law’s progression has required a tremendous amount of engineering and commitment from the global semiconductor industry. While its meaning has evolved over generations, it has had a profound impact in many areas of technological change and progress.

“It is truly an honor to present imec’s lifetime innovation award to Dr. Moore, on behalf of all our global partners and our researchers,” stated Luc Van den hove, president and CEO of imec. “Dr. Moore’s name is synonymous with progress, and his vision has inspired and given direction to the entire semiconductor industry, which has revolutionized the way we compute, communicate, and interact. As the industry upholds this prediction and brings forth new innovations in chip technology, the future of Moore’s law will impact such things as healthcare, a sustainable climate, and safer transport all for the better.”

Dr. Moore began his career at Johns Hopkins University. He cofounded Fairchild Semiconductor in 1957 and launched Intel in 1968 together with Robert Noyce and Andy Grove. Today, Intel is a world leader in the design and manufacturing of integrated circuits and is the largest semiconductor company. Dr. Moore served as Intel CEO from 1975-1987, and then became its chairman of the board until his retirement in 1997.

“Although Moore’s law was created more than 50 years ago, it remains extremely valid and serves as a guide to what we innovate at imec,” continued Van den hove. “Throughout our organizations’ 32-year existence, we’ve worked at enabling Moore’s law and helping our partners innovate and develop the modern technology that society has embraced and demands. Dr. Moore’s legacy continues to be our mission and we are privileged to honor him.” 

Imec’s Lifetime of Innovation award is awarded to Dr. Moore on May 24, 2016 at its annual ITF Brussels, the flagship of imec’s worldwide ITF events.

By Dieter Ernst, East-West Center, Honolulu, HI
How will China’s new role transform the global semiconductor industry?

China has become the largest and fastest growing semiconductor market in the world, absorbing 40% of the worldwide semiconductor shipments. For US semiconductor firms, nothing compares to the China market.

China however faces a fundamental dilemma. As the world’s leading exporter of electronic products, it remains heavily dependent on imports of semiconductors and technology, primarily from the US, but also from Japan, Korea, Taiwan and Europe. At least 80 percent of the semiconductors used in China’s electronics manufacturing are imported and virtually all leading-edge devices like multi-component semiconductors (MCOs). For instance, 43% of the inputs for handsets and networking equipment of China’s second largest telecom company, ZTE, are supplied by US companies (Avnet, Qualcomm, Broadcom, Jabil, Intel, Microsoft, Micron, Xilinx, Nvidia and Finisar) [1].

As a result, China’s trade deficit in semiconductors has more than doubled since 2005 and now exceeds the huge amount it spends on crude oil imports. To correct this unsustainable imbalance, China’s new strategy to upgrade its semiconductor industry seeks to move from catching up to forging ahead in semiconductors through progressive import substitution. The “National Semiconductor Industry Development Guidelines (Guidelines)” and the “Made in China 2025” (MIC 2025, 中国制造2025) plan were published by China’s State Council in June 2014 and May 2015, respectively [2]. Both policies seek to strengthen simultaneously advanced manufacturing and innovation capabilities in China’s integrated circuit (IC) design industry and its domestic IC fabrication, primarily through foundry services.

As part of the Guidelines, a CNY120 billion (US$19 billion) national industry investment fund has been set up to help local foundries finance the build-up of advanced manufacturing processes, and also to assist local IC firms to form mergers and/or make acquisitions internationally. With the MIC 2025 plan, China is aiming to improve the self-sufficiency rate for ICs in the nation to 40% in 2020, and boost the rate further to 70% in 2025. MIC 2025 specifically defines the following priorities: i) Catch up with world best practice in IC design cores and design tools; ii) move to the frontier of multicomponent semiconductors (MCOs); iii) win design-in contracts from China-based electronic equipment manufacturers (both large global MNCs and Chinese firms like Lenovo or Huawei); and iv) strengthen China’s capacity to design and produce high- density chip packages and 3D micro-package technology.

Both policies have already led to a major push in the development of the local IC industry, with investments in semiconductor memories, designs, foundries, OSATS, and equipment and materials. In addition, strategic partnerships, joint ventures and mergers and acquisitions have proliferated across China’s semiconductor industry, both among domestic firms (to increase economies of scale and scope), and with leading global semiconductor firms (to access cutting-edge technology and best-practice management techniques).

Based on a review of policy documents and interviews with China-based industry experts, this paper explores how realistic these objectives are, and how this might affect international firms and the global semiconductor industry.

How realistic are the objectives of China’s new policies?

Over the last 60 or so years, China’s semiconductor industry has come a long way from being a completely government-owned part of the defense technology production system, with state-owned enterprises (SOEs) as the only players, toward a gradually more market-led development model. The role of SOEs has dramatically declined, and a deep integration into international trade and global networks of production and innovation has transformed decisions on pricing and investment allocation, with private firms as the main drivers. Major achievements include the rapid growth of China’s IC design industry from practically zero at the turn of the century to $17.05 billion in 2014, with an almost 37% compound annual growth rate since 2003. Other achievements include the successful diversification into optical devices (especially LED-related), sensors and discrete devices; first steps to move from silicon to wide band-gap semiconductor materials; and the surge of China’s semiconductor assembly, packaging, and testing (APT) industry, which has become the global market leader.

However, China’s achievements are overshadowed by persistent weaknesses, despite massive government support. Buying decisions for advanced ICs consumed in China are mostly made in Taiwan, Korea, US (for mobile devices), Japan, and Singapore. Of particular concern is the large and growing gap between semiconductor consumption and production, which has ballooned to a record $ 120 billion in 2013, and is forecast to reach $ 151.5 billion in 2017.[3] Equally important, China continues to play second fiddle in wafer fabrication – China’s 2015 share of total worldwide semiconductor wafer fab capacity is 11.7%,but advanced technology nodes (28nm and below) account for only 5% of worldwide wafer fab capacity. Foreign IDMs dominate (Intel, Samsung, Hynix), and Chinese foundries have a long way to go to catch up in process technology and wafer size. Most importantly, China lags behind in innovation, especially for advanced semiconductors, despite all the government’s previous plans and efforts.

Will China’s policy on semiconductors this time around work better than before? Our research finds that China’s new semiconductor policy does not represent a radical break with its deeply embedded statist tradition [4]. However, there are some important changes toward a more bottom-up, market- led approach to industrial policy. If sustained, these changes may considerably improve China’s chances to succeed in its new push in semiconductors.

China’s new semiconductor policy (as defined in the Guide- lines) relies on private equity investment rather than subsidy as the tool of industrial policy. The government participates in equity investment but claims it will do so without intervening in management decisions. This is expected to reduce the cost of investment for a selected group of firms comprising a “national team” in the semiconductor industry. The underlying financial networks are complex and difficult to disentangle. Take Hua Capital Management Co., Ltd (HCM), a Chinese investment management company, which was chosen to manage the chip design and testing fund under the Beijing government’s 30-billion-yuan (HK$37.8 billion) Semiconductor Industry Development Fund.

According to industry observers, the real driving force behind HCM is Chen Datong, who is HCM’s chairman as well as co-founder and managing partner of WestSummit Capital, a leading China-based global equity firm focused on helping high-growth technology companies access the China market. Dr. Chen has more than 20 years of investment and operations experience in the technology and semiconductor industries, and he owns 34 US and European patents. [5] Another major player is Liu Yue, the deputy chairwoman of HCM, who also has a wealth of experience in China’s IC industry. Of particular interest is her role as an early investor in China’s leading foundry SMIC through Walden Capital, and her continuous involvement with SMIC. HCM’s president, Xisheng (Steven) Zhang, started out in 1994 as a post-doctorate researcher at University of California, Berkeley, worked his way into senior management positions at Agilent Technologies and Silicon Valley start-up IC design companies, and joined Beijing- based private equity investment company WestSummit Capital in 2013. Zhang has over 20 years industry experience in semiconductors, and in managing start-up companies in Silicon Valley and in Beijing.

Based on this information, one might conclude that HCM qualifies as a professional fund manager with considerable knowledge of key aspects of the semiconductor industry value chain, especially related to IC design. In the view of the United States Information Technology Office (USITO), the use of professional investment fund managers, as opposed to government subsidies or investment, “suggest a new approach to industrial policy that focuses on building a strong and sustainable investment environment in China.”[6] It remains unclear, however, how private equity fund managers, who are supposed to maximize the return to capital, can nevertheless serve as proxies for the government and support its policy to strengthen indigenous innovation. A final assessment thus has to wait until more information is available on how funds will ultimately be deployed.

MIC 2025, on the other hand, seeks to provide a new framework for coordinating industrial support policies, in order to overcome a persistent gap in technological, management and innovation capabilities. Improved policy coordination is considered to be essential for overcoming deeply entrenched disconnects between industry, academia and government. Over two and a half years, 50 experts from the China Academy of Engineering and the Chinese Academy of Sciences worked together with around 100 experts from industry and research institutes to design the MIC 2025 plan. An equally important objective is to reduce the fragmentation of decision-making across government agencies and between the Central government and local governments. As an important step in this direction, 14 state-run associations from different sectors worked together and created a voluntary quality management standard for automated and intelligent manufacturing.

In short, China’s government seems more open to experimentation with new approaches to policy formulation, investment finance and flexible, bottom-up policy implementation. Among Chinese technology planners, there seems to be a growing consensus that the closer China moves to the technology frontier, the less scope there is for imitation and low-level incremental innovation. Chinese firms now are encouraged to develop and protect their own intellectual property rights and accelerate the commercialization of new ideas, discoveries and inventions.

China’s leadership is very conscious that the United States is far ahead in advanced semiconductors and that China has a long way to go to close the gap. But at the same time, Beijing’s new semiconductor policies also convey a new sense of optimism. Global transformations in semiconductor markets and technology, including a new interest in strategic partnerships and mergers, are no longer perceived exclusively as threats. In fact, China’s technology planners now seek to identify pathways to innovation- led development that could benefit from new technologies, such as the technology convergence in mobile devices, the Internet of Things in industrial manufacturing, and “green development”, focusing on a reduction of energy consumption, water usage and pollution. Forging ahead in semiconductors is considered essential for realizing this potential.

Above all, the role of the government appears to be gradually shifting away from the selection of priority sectors and technologies toward the facilitation of an interactive learning process led by the private sector. In this new model of industrial policy, which is slowly taking hold in China’s semiconductor industry, the government role is to provide incentives and remove regulatory constraints to empower the private companies that are most capable of realizing China’s domestic innovation potential.

It is however an open question whether China’s transition to innovation-led growth in semiconductors could be derailed, for instance, by the threat of overcapacity or by the Leader- ship’s (cyber-) security objectives. As is typical for China, the implementation of the semiconductor policy is left to the local governments who have become masters in producing overcapacity due to misaligned incentives that are focused exclusively on the region’s GDP growth.

China’s policy on cyber security seeks to protect China-based information systems against perceived threats to national and public security. [7] In response to Edward Snowden’s disclosure of US National Security Agency (NSA) global surveillance practices in China and elsewhere, China’s concern with cyber- security receives prominent attention in the Guidelines. It is unclear at this stage whether the drumbeat on security is used primarily as a tactic to mobilize support for aggressive investment funding? [8] Or is this focus on security an overriding concern for China’s leadership that will cast aside many of the aforementioned economic considerations?

In the end, there is reason for cautious optimism that pragmatism will continue to shape China’s policy for semiconductors [9]. Learning from global industry leaders will play a critical role, based on a quite realistic set of expectations: “In the next ten years, there will be a large amount of M&A cases in China, but many of them will fail…But it is better than nothing. China’s enterprises will gain experience.”[10] More than before, such pragmatism will be shaped by economic constraints, such as the country’s rising debt and dwindling foreign exchange reserves due to the collapse in Chinese exports [11].

Implications for international firms and the global semiconductor industry

As U.S. and other foreign semiconductor companies heavily depend on the China market, they seem to have little choice but to adjust their strategies to China’s new semiconductor policy. Intel, for instance, now depends on China for one-fifth of its revenues, while Qualcomm relies on the China market for nearly half of its income. In fact, U.S. and other foreign firms are quite explicit that they would be willing to accede to Chinese demands to transfer technology and form joint ventures with its firms, if only they could expand or at least sustain their share of the China market.

Examples include Intel’s substantial investment in Spreadtrum, one of China’s leading IC design firms, and Qualcomm’s investment in China’s leading IC fabrication company, SMIC. As foreign firms seek to cooperate more closely with Chinese firms in exchange for continued market access, this raises the question to what degree this might amplify China’s policies. Might foreign firms in some cases actually provide more effective support than the Beijing government in expanding China’s semiconductor industry?

To conclude, both Chinese and U.S. semiconductor companies have much to gain by learning from each other as they each face their own upgrading imperatives. While they compete in global markets, they would both benefit from cooperation in advanced semiconductor manufacturing and technology to solve the challenges of economic growth, better and lower- cost health systems, and a greener environment. Given the importance of both countries in the global semiconductor industry, it is striking to see that such cooperation remains as yet quite limited.

There is however ample scope to extend such cooperation. While China is catching-up in semiconductors, the US is still way ahead in overall innovation capacity. China’s persistent innovation gap implies that Chinese firms continue to need access to American technology, whether in terms of equipment, core components, software or system integration. For America, this implies that China’s new policies for semiconductors creates new markets for American firms, provided they stay ahead on the innovation curve.

But implementing such cooperation faces many hurdles. While incumbent industry leaders seek to retain the status quo, newcomers like China seek to adjust the old rules to reflect their interests as latecomers. But progress towards greater cooperation should be possible, once China acknowledges that US semiconductor firms need safeguards against forced technology transfer through policies like compulsory licensing, information security standards and certification, and restrictive government procurement policies. The US, in turn, needs to acknowledge that Chinese firms feel disadvantaged by restrictions on Chinese foreign direct investment (through CFIUS), and by restrictions on the export of technology to China, like the recent decision of the Commerce Department to slap technology export restrictions on US suppliers of semiconductor to China’s ZTE. In the end, such policies may encourage China to shift to alternative suppliers in Korea, Taiwan, and to promote more aggressively domestic suppliers.

References

  1. China-based firms supply less than 17% of ZTE’ s most recent quarterly procurement value, see Bloomberg Supply Chain data, as reported in http://www.bloomberg.com/ gadfly/articles/2016-03-07/a-u-s-ban-on-sales-to-china-s-zte-could-backfire.
  2. See USITO, 2014, Guidelines to Promote National Integrated Circuit Industry Development (unauthorized translation of document published by the Ministry of Industry and Infor- mation Technology, the National Development and Reform Commission, the Ministry of Finance, and the Department of Science and Technology), United States Information Technology Office, Beijing, June 24. On MIC2025, see the official website http://english.cntv.cn/special/madeinchina/ index.shtml. For an unofficial translation of the MIC2025 plan, see http://www.usito.org/content/usito-made- china-2025- unofficial-translation-2015-5-29.
  3. PWC, 2016, China’s impact on the semiconductor industry: 2015 update March,http://www.pwc.com/gx/en/technology/ pdf/china-semicon-2015-report-1-5.pdf
  4. Ernst, D., 2015, From Catching Up to Forging Ahead: China’s Policies for Semiconductors, East-West Center Special Study, September, http://www.eastwestcenter. org/node/35320, http://papers.ssrn.com/sol3/papers. cfm?abstract_id=2744974
  5. Chen Datong got his BS, MS, and PhD from Tsinghua University and worked as a post-doctoral research fellow at Stanford University. He was a partner in the Northern Light Venture Capital fund where he led investments in the semiconductor industry. Dr. Chen was the co-founder and CTO of Spreadtrum Communications, and hence has deep insider knowledge of that company. Prior to Spreadtrum, Dr. Chen was the co-founder and senior VP for OmniVision, again providing him with insider knowledge about the acquisition of that company in 2015.
  6. USITO, China IC Industry Support Guidelines—Summary and Analysis, September 1, 2014: 6.
  7. The following draws on chapter 2 in D. Ernst, Indigenous Innovation and Globalization: The Challenge for China’s Standardization Strategy, 2011. See also D. Ernst and S. Martin, The Common Criteria for Information Technology Security Evaluation: Implications for China’s Policy on Information Security Standards, East-West Center Working Paper, Economics Series no. 108, January 2010.
  8. After all, security concerns as a tactic to mobilize support for public and private investment in R&D have been used in other countries before, the United States included.
  9. According to a leading China expert, “Pragmatism has been a hallmark of China’s reforms over the past 30 years, as Chinese leaders have not flinched from a realistic view of their challenges. They typically experiment with various approaches before deciding on the best ways to address major concerns.” K. Lieberthal, Managing the China Challenge: How to Achieve Corporate Success in the People’s Republic (Washington, DC: Brookings Institution Press, 2011): p.7.
  10. Chen Datong, chairman, Hua Capital Management Co., Ltd, one of China’s IC Industry Equity Development Funds, presentation at Global Leadership Summit, Global Semicon- ductor Alliance (GSA), Shanghai, http://www.gsaglobal.org/ events/2014/0320/speakers.aspx#Chen.
  11. According to Reuters, “China’s February 2016 trade perfor- mance was far worse than economists had expected, with exports tumbling the most in over six years, days after top leaders sought to reassure investors that the outlook for the world’s second-largest economy remains solid. Exports fell 25.4 percent from a year earlier, twice as much as markets had feared as demand skidded in all of China’s major markets, while imports slumped 13.8 percent, the 16th straight month of decline.” (China February exports post worst fall since May 2009, March 8, 2016, http:// www.reuters.com/article/us- china-economy-trade- idUSKCN0WA09C

By Ed Korczynski, Senior Technical Editor

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in at least one leading memory fab.

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs: Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/ hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues.

“In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran.

“We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology: ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers.

“Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints (http://cnt.canon.com/). Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm, while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high- volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.

Active matrix organic light-emitting diode (AMOLED) displays are rising fast, thanks to lowering costs, wider use in end-market consumer electronics devices and the ramp-up of new manufacturing capacities.  While liquid crystal display (LCD) technology is still the dominant technology in the display industry, AMOLED display shipments will grow 40 percent, year over year, to reach 395 million units in 2016. AMOLED display revenue is expected to increase by 25 percent, to reach $15 billion in 2016, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight.

“AMOLED is becoming the shiniest spot in the flat-panel display industry,” said David Hsieh, senior director, displays at IHS Technology. “AMOLED has a simpler structure than LCD, as well as a thinner and lighter form factor, better color saturation, greater contrast ratio, faster response time and easier integration with touch functions. In addition, AMOLED is formed on a polymer base substrate, allowing it to be flexible, bendable and even foldable. The organic electro-luminescence materials can be formed using a soluble printing process, which means AMOLED has the potential to be produced at a very low cost.”

Many of the obstacles to AMOLED development, such as production inefficiencies, yield-rate management issues, higher investment costs and a short lifetime for light emitting materials, were also resolved in 2015, improving the production. OLED has started to find its niche in many applications, especially in smartphones, smartwatches, automotive displays, home appliances, near-eye virtual reality (VR) devices and televisions. “Improvements in production and lowering costs are attracting more device makers to install AMOLED displays in their products,” Hsieh said.

For example, Samsung Electronics has been using AMOLED as an important differentiator in its proprietary Galaxy smartphones. Since the second half of 2015, more smartphone brands — especially manufacturers in China — have installed AMOLED displays in their devices, such as Google, Microsoft, Meizhu, Blackberry, Huawei, HTC, ZTE, Oppo and Coolpad. The 5-inch high-definition (HD), 5.5-inch full high definition (FHD), 5.5-inch and 6-inch wide quad high definition (WQHD) will be the major AMOLED smartphone display driving forces in 2016.

AMOLED penetration in smartphone displays is expected to rise from 17 percent in 2015 to 21 percent this year. Apple is reported to be considering AMOLED as a display source for its new iPhone in late 2017, replacing the current low-temperature polysilicon (LTPS) thin-film transistor (TFT) LCD display. “If Apple actually starts using AMOLED displays, the transition will be viewed as a milestone in flexible form factor development,” Hsieh said.

AMOLED_Chart_LG_IHS

According to the IHS OLED Display Market Tracker, OLED TV shipments will further expand in 2016, thanks to process improvements and production efficiency enhancements, as well as improvements in organic light emitting materials layers. In fact, LG Display is already expanding its AMOLED TV panels to 65 inches with ultra-high definition (UHD), which will bring AMOLED into the high-end TV segment. IHS expects OLED TV display shipments will grow 125 percent, year over year, to reach 900,000 units in 2016.

Tablet and notebook PCs is another important venue for AMOLED, for its slim and light form factor, and high resolution. We expect to see 8-inch and 9.7-inch quad extended graphics array (QXGA) displays and 12-inch AMOLED panels begin to emerge in the mobile PC arena this year. Many PC brands are planning to use AMOLED in notebook PCs and two-in-one convertible mobile PC models beginning in 2016. AMOLED mobile PC panels are expected to grow 63 percent year over year, to reach to 8.6 million units in 2016.

AMOLED is also leading other display technologies when it comes to response time and power consumption, which is extremely useful in near-eye display devices, including VR and augmented reality (AR) devices. AMOLED display and OLED on silicon projection displays, which are both used in near-eye displays are forecast to grow 119 percent, year over year, to reach 3.6 million units in 2016.

“The central information display in cars will also feature AMOLED within the next couple of years,” Hsieh said, “AMOLED displays provide features that are useful in automotive display applications, because of their high contrast ratio, flexible and curved form factors as well as better color gamut. Aside from these applications, AMOLED also presents great opportunities for industrial applications, home appliances, digital signage and broadcasting.”

AMOLED, as a rapidly emerging display technology, will be a key theme in the coming SID Display Week 2016 Business Track, which is co-organized by IHS and the Society for Information Display. For more information, visit SID Display Week.

IC Insights’ April Update to the 2016 McClean Report, to be released later this week, includes IC Insights’ final 2015 top 50 company rankings for total semiconductor and IC sales as well as rankings of the leading suppliers of DRAM, flash memory, MPUs, IC foundry services, etc.

Figure 1 ranks the top 13 IC foundries (pure-play and IDM) by foundry sales in 2015.

Apple TSMC sales

TSMC, by far, was the leader with $26.4 billion in sales last year.  In fact, TSMC’s 2015 sales were over 5x that of second-ranked GlobalFoundries (even with the addition of IBM’s chip business in the second half of 2015) and almost 12x the sales of the fifth-ranked China-based foundry SMIC.  As shown, there are only two IDM foundries in the ranking—Samsung and Fujitsu—after IBM and Magnachip fell from the list in 2015.  Despite losing a significant amount of Apple’s business, Samsung easily remained the largest IDM foundry last year, with more than 3x the sales of Fujitsu, the second-largest IDM foundry.

Illustrating the dramatic effect of exchange rate fluctuations on the IC sales numbers, TSMC’s 2015 growth rate was about half (6%) of what it was in its local currency (11%).  Thus, while the company met its stated goal of 10% or better growth in 2015 in NT dollars (840.5 billion), its growth rate in U.S. dollars was only 6%.

Driving home just how important Apple’s foundry business is, TSMC’s foundry sales increased by $1,464 million last year while its sales to Apple jumped by $1,990 million, representing more than 100% of TSMC’s total foundry sales increase in 2015.  As a result, without Apple, TSMC’s foundry sales would have declined by 2% last year, eight points less than the 6% increase it logged when including Apple.

Second ranked GlobalFoundries took over IBM’s IC business in early July of 2015.  It should be noted that besides $515 million in IDM foundry sales IBM made in 2014, the company also had about $1.0 billion of internal transfer IC revenue that year.  As a result, GlobalFoundries’ quarterly sales in 4Q15 were about $1.4 billion, an annual run-rate of $5.6 billion, about 12% greater than the company’s 2015 sales of $5.0 billion. However, without the addition of IBM’s sales in the second half of last year, GlobalFoundries’ sales would have declined by 2% in 2015.

Sales from the top 13 foundries’ shown in Figure 1 were $46.7 billion and represented 93% of the $50.3 billion in total foundry sales in 2015.  This share was two points higher than the 91% share the top 13 represented two years earlier in 2013.  With the barriers to entry (e.g., fab costs, access to leading edge technology, etc.) into the foundry business being so high and rising, IC Insights expects this “top 13” marketshare figure to continue to slowly rise in the future.