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Mentor Graphics Corp. ushered in a new era of emulation by announcing new applications for the Veloce emulation platform. The new Veloce Apps—Veloce Deterministic ICE, Veloce DFT and Veloce FastPath—overcome critical system-level verification challenges in complex SoC and system designs. They run on an upgraded Veloce OS3 operating system that significantly accelerates design compile cycles, gate-level flows, and the time it takes to review results (“time to visibility”). The combination of Veloce Apps on Veloce OS3 puts more capabilities into the hands of more engineers more quickly than hardware-centric strategies.

Each of the new Veloce Apps addresses a specific verification issue:

  • Veloce Deterministic ICE overcomes unpredictability in In-circuit Emulation (ICE) environments by adding 100% visibility and repeatability for debug, and provides access to other ‘virtual-based’ use models;
  • Veloce DFT accelerates Design for Test (DFT) verification prior to tape-out to
    minimize the risk of catastrophic failure, and significantly reduces run times when verifying designs after DFT insertion; and
  • Veloce FastPath optimizes emulation performance when verifying large multi- clock SoC designs by enabling faster model execution speed.

These new Veloce Apps join Veloce Power, Veloce Enterprise Server and other apps in an expanding arsenal of software innovations for the Veloce emulation platform. Mentor will continue to expand the library of Veloce Apps to introduce new ways to ensure designs meet their functional and performance specifications on schedule.

The new Veloce Deterministic ICE, Veloce DFT and Veloce FastPath applications expand the Veloce Apps library to put more emulation capabilities the hands of more engineers.

The new Veloce Deterministic ICE, Veloce DFT and Veloce FastPath applications expand the Veloce Apps library to put more emulation capabilities the hands of more engineers.

The Veloce OS operating system adds software programmability and resource management to the Veloce platform, making it easier to add new use models that increase the ROI of the emulator. The recent upgrade of Veloce OS3 covers several innovations:

  • Integration of new High Performance Computing platforms cuts compile time by 50%.
  • A faster gate-level flow operates as “plug-and-play”—able to accept flat or hierarchical designs. This flow reduces the amount of memory needed for compilation, which improves performance. By making it easier to load and verify gate-level designs, the new flow improves confidence in silicon fidelity.
  • The combination of software and hardware improvements spanning the run time and debug cycles achieves 200% faster time-to-visibility.

These new Veloce emulation capabilities demonstrate how innovative software, running on powerful, qualified hardware and an extensible operating system, can target design risks faster than hardware-centric strategies. As emulation enters its fourth decade and expands across mainstream markets, the Veloce emulation platform has become a powerful resource across a range of hardware, software and system verification flows.

“Mentor continues to demonstrate its technology leadership through its application-based strategy for the Veloce emulation platform,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “These latest innovations accelerate overall verification throughput performance for our customers. The focus on software apps for specific SoC and system-level challenges is driving the future of emulation.”

About the Veloce emulation platform

The Veloce emulation platform is a core technology in the Mentor Enterprise Verification Platform (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform.

Now considered among the most versatile and powerful of verification tools, project teams use emulation for hardware debugging, hardware/software co-verification or integration, system- level prototyping, low-power verification and power estimation and performance characterization.

According to IC Insights’ new 2016 edition of The McClean Report, total worldwide semiconductor industry capital spending is forecast to show low single-digit growth in 2016 after registering a 1% decline in 2015.  As discussed below, last year’s drop in semiconductor industry capital spending was a significant departure from historical patterns that go back more than 30 years.

Figure 1 shows the annual worldwide semiconductor industry capital spending changes from 1983-2015.  Over the past 33 years, there have been six periods when semiconductor industry capital spending declined by double-digits rates for one or two years (1985-1986, 1992, 1997-1998, 2001-2002, 2008-2009, and 2012-2013).  It is interesting to note that in every case except the 2012-2013 spending downturn, within two years after the period of decline in capital spending, a surge in spending of at least 45% occurred.  The second year increases in spending after the cutbacks were typically stronger than the first year after a downturn with the lone exception to this being the 2010 spending rebound after the 2008-2009 downturn.  This was because most semiconductor producers tend to act very conservatively coming out of a market slowdown and wait until they have logged about 4-6 quarters of good operating results before significantly increasing their capital spending again.

As shown in Figure 1, the streak of strong capital spending growth within two years after a spending cutback timeperiod ended in 2015, with capital spending registering a 1% decline.  IC Insights believes that this is yet another indication of a maturing semiconductor industry.

Figure 1

Figure 1

More detailed information on semiconductor industry capital spending, including 2016 capital spending forecasts by company, can be found in IC Insights’ flagship market research report, The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry. The new 478-page McClean Report provides IC market and technology trend forecasts from 2016 through 2020.

Nanoelectronics research center, imec, and digital research and incubation center, iMinds, today announced that its respective board of directors have approved the intention to merge the research centers. Using the imec name, the combined entities intend to create a high-tech research center for the digital economy. The transaction is expected to be completed by the end of 2016, with the united organization staged to bring added value to existing partners while further strengthening Flanders’ authority as a technology epicenter and region focused on creating a sustainable digital future.

iMinds will be integrated as an additional business unit within imec, resulting in a new research center that will fuse the technology and systems expertise of more than 2,500 imec researchers worldwide with the digital competencies of some 1,000 iMinds researchers representing nearly 50 nationalities. The additions of iMinds’ flagship open innovation research model -ICON- (in which academic researchers and industry partners jointly develop solutions for specific market needs), iStart entrepreneurship program (supporting start-up businesses), and Living Labs will strengthen the unique capabilities and assets of imec as a research and development center.

Imec has been a global leader in the domain of nanoelectronics for more than 30 years, and has innovated applications in smart systems for the Internet of Things (IoT), Internet of Health, and Internet of Power. It has built an extensive and worldwide partner network, as well as in Flanders, and has generated successful spin-offs. iMinds’ activities span research domains such as the IoT, digital privacy and security, and the conversion of raw data into knowledge. Its software expertise is widely renowned and its entrepreneurship activities in Flanders are first-rate.

“The proliferation of the Internet of Everything has created a need for solutions that integrate both hardware and software. Such innovative products that optimally serve tomorrow’s digital economy can only be developed through intense interaction between both worlds. There are infinite opportunities in domains such as sustainable healthcare, smart cities, smart manufacturing, smart finances, smart mobility, smart grids, or in short, smart everything. Research centers such as imec, with its widely acclaimed hardware expertise, and iMinds, an expert in software and ICT applications, are uniquely positioned to bring these concepts to life,” stated Luc Van den hove, president and CEO of imec. “Furthermore, iMinds is widely recognized for its business incubation programs and open access to SMEs, and, this merger provides us with a unique opportunity to jointly reach out to the Flemish industry and further elevate Smart Flanders on the global map.”

“Flanders faces the enormous challenge of realizing a successful transition towards tomorrow’s digital society; a transition that must happen quickly, considering the urgency to reinforce Flanders’ industrial position,” commented Danny Goderis, CEO of iMinds. “The merger between imec and iMinds is Flanders’ answer to this rapidly accelerating digitization trend. We have a clear ambition to pair more than 3,500 top researchers across 70 countries with an ecosystem of Flemish companies and start-ups, thereby significantly increasing our economic and societal impact. Together, we can help Flanders boost its competitiveness and claim a strong international position.”

Now that the intention to merge has been approved, the merger protocol will be developed and the integration process of imec and iMinds will be initiated immediately. The current iMinds activities will constitute a third pillar next to imec’s units. iMinds will remain headquartered in Ghent with its researchers spread across the Flemish universities. The ambition is to operate as one organization by the end of 2016.

Flemish Minister of Innovation Philippe Muyters welcomes the fact that iMinds and imec join forces: “Thanks to their pioneering work in their respective fields, they have put themselves on the world map. When they were founded, the line between hardware and software was still very clear. Today, and especially in the future, this line is increasingly blurring – with technology, systems and applications being developed in close conjunction. The merger anticipates this trend and creates a high-tech research center for the digital economy that keeps Flanders on the world map. The gradual integration of both research centers, and the agreement to preserve their respective strengths and uniqueness, will make for a bright future.”

Neon shortage coming


February 18, 2016

The current Neon demand is growing in “stealth mode” – hidden from the layman’s view because of significant factors only analysts fully versed in lithography, OLED/FPD and semiconductor device trends would catch. The traditional method of using historical data to predict future Neon demand will grossly underestimate future usage.

“Those who are basing their thinking on projections of historical Neon growth are in for a big surprise,” said TECHCET’s President/CEO, Lita Shon-Roy.   “Even with the recovery of the Neon supply chain, Neon conservation actions, and new sources in China, we predict that Neon demand will grow faster than Neon supply,” she added.

The largest and most rapidly growing Neon demand drivers are Lasik, OLED/FPD (displays) and DUV lithography. However, Neon gas consumed by DUV excimer laser gases is growing at a faster pace and represents more than 90% of world’s Neon consumption.

Semiconductor lithographic use of Neon is increasing more rapidly than expected for several reasons including the delay of EUVL while demand for finer line width patterning is increasing. In addition, new consumer related markets drive increased usage of legacy device processing. Each increase in the number of lithographic steps increases the need for more DUV lithography tools, and drives up the volume demand for Neon. This is true for V-NAND process flows, as well as DRAM and Logic devices dependent on multi-patterning.

Currently, the installed base of DUV lithography tools is ~ 4,400. In contrast, there have only been a dozen or so EUVL tools shipped through the end of 2015.

“The continued growth of DUV tools will push up demand for NEON beyond which supply can support,” cautioned Shon-Roy.

More details can be found from TECHCET’s latest Critical Materials Report on NEON Supply & Demand. Information will also be presented at the CMC Conference, scheduled for May 5-6, in Hillsboro, Oregon – this is the open forum portion of the Critical Materials Council meetings. For more information go to http://techcet.com/product/neon-a-supply-alert-report/ For more information on the CMC Conference please go to www.cmcfabs.org/seminars/

CMC Fabs is a membership based group that actively works to identify issues surrounding the supply, availability, and accessibility of semiconductor process materials, current and emerging, “Critical Materials.” CMC Fabs is managed by TECHCET CA LLC, a firm focused on Process Materials Supply Chains, Electronic Materials Technology Trends, and Materials Market Analysis for the Semiconductor, Display, Solar/PV, and LED Industries. The Company has been responsible for producing the SEMATECH Critical Material Reports since 2000.

Fairchild Semiconductor International, Inc. announced this week that its board of directors, after consultation with its legal and financial advisors, has determined that the unsolicited proposal received on December 28, 2015, from China Resources Microelectronics Ltd and Hua Capital Management Co., Ltd.  to acquire Fairchild does not constitute a “Superior Proposal” as defined in the Company’s Agreement and Plan of Merger with ON Semiconductor Corporation.

On January 5, 2016, Fairchild announced that the Board determined that the Acquisition Proposal would reasonably be expected to result in a Superior Proposal. The Fairchild management team, along with Fairchild’s legal and financial advisors, engaged in extensive discussions with China Resources and Hua Capital. After conducting a thorough review, and after consultation with Fairchild’s legal and financial advisors, the Board concluded that the Acquisition Proposal is not superior to Fairchild’s existing agreement with ON Semiconductor.

As previously announced on November 18, 2015, Fairchild entered into an Agreement and Plan of Merger with ON Semiconductor, under which a wholly owned subsidiary of ON Semiconductor agreed to acquire all of the outstanding shares of Fairchild common stock for $20.00 per share in cash.

Fairchild remains subject to the Agreement and Plan of Merger with ON Semiconductor, and the Board has not changed its recommendation in support of that agreement.

Goldman, Sachs & Co. is acting as financial advisor to Fairchild, and Wachtell, Lipton, Rosen & Katz is serving as its legal counsel.

The worldwide electronics industry is greatly influenced by consumer purchases of smartphones, PCs, automobiles, and many other devices and systems. The better the worldwide economy performs, the more money consumers will spend on electronic systems, which in turn creates a positive environment conducive to good IC market growth.  For 2016, IC Insights is taking a conservative approach to worldwide GDP with forecast growth of 2.7%, which is only slightly better than the 2.5% global GDP growth in 2015. Some observations regarding worldwide GDP include the following.

– Average annual worldwide GDP figures have declined every decade since the 1960s with a slight rebound registered in the first six years of the current decade (Figure 1). Worldwide annual GDP growth has averaged 2.8% since 1980.

– Worldwide annual GDP growth rarely goes negative (the last negative worldwide GDP year before 2009 was in 1946) and rarely goes above 5.0% (with the usual associated surge in oil prices acting as a strong limiting factor).

– A worldwide GDP growth rate of 2.5% or less is considered by most economists to be indicative of a global recession, which puts 2015’s growth right at the threshold.  Prior to the late 1990s, when emerging markets like China and India represented a much smaller share of the worldwide economy, a global recession was typically defined as 2.0% or less growth.  The global recession threshold has never been a “hard and fast” rule, but the guidelines discussed here are useful for this analysis.

IC Insights depicts the increasingly close correlation between worldwide GDP growth and IC market growth in Figure 2.

Figure 1

Figure 1

Figure 2

Figure 2

As seen in Figure 2, the 2010-2015 correlation coefficient between worldwide GDP growth and IC market growth was 0.92, a very strong figure given that a perfect correlation is 1.0.  In the three decades previous to this time period, the correlation coefficient ranged from a relatively weak 0.63 in the early 2000s to a negative correlation of -0.10 in the 1990s.

IC Insights believes that the growing number of mergers and acquisitions in the IC industry (discussed in detail in Section 3 of the new 2016 McClean Report) has resulted in fewer major IC manufacturers and suppliers and is just one of the major changes in the supply base that illustrates the maturing of the industry.  Other factors such as few, if any, new entry points for startup IC manufacturers, a strong movement to the fab-lite business model, and declining capex as a percent of sales ratios, are also indicative of dramatic changes to the semiconductor industry that are likely to lead to less volatile pricing and less volatile market cycles.

With forecasted annual worldwide GDP growth rates that range from 2.7% to 3.1% over the next five years, IC Insights’ IC market growth rate expectations mirror the narrow range of worldwide GDP growth.

Heterostructures formed by different three-dimensional semiconductors form the foundation for modern electronic and photonic devices. Now, University of Washington scientists have successfully combined two different ultrathin semiconductors — each just one layer of atoms thick and roughly 100,000 times thinner than a human hair — to make a new two-dimensional heterostructure with potential uses in clean energy and optically-active electronics. The team, led by Boeing Distinguished Associate Professor Xiaodong Xu, announced its findings in a paper published Feb. 12 in the journal Science.

Senior author Xu and lead authors Kyle Seyler and Pasqual Rivera, both doctoral students in the UW physics department, synthesized and investigated the optical properties of this new type of semiconductor sandwich.

“What we’re seeing here is distinct from heterostructures made of 3-D semiconductors,” said Xu, who has joint appointments in the Department of Physics and the Department of Materials Science and Engineering. “We’ve created a system to study the special properties of these atomically thin layers and their potential to answer basic questions about physics and develop new electronic and photonic technologies.”

When semiconductors absorb light, pairs of positive and negative charges can form and bind together to create so-called excitons. Scientists have long studied how these excitons behave, but when they are squeezed down to the 2-D limit in these atomically thin materials, surprising interactions can occur.

While traditional semiconductors manipulate the flow of electron charge, this device allows excitons to be preserved in “valleys,” a concept from quantum mechanics similar to the spin of electrons. This is a critical step in the development of new nanoscale technologies that integrate light with electronics.

“It was already known that these ultrathin 2-D semiconductor have these unique properties that you cannot find in other 2-D or 3-D arrangements,” said Xu. “But as we show here, when we put these two layers together — one on top of the other — the interface between these sheets becomes the site of even more new physical properties, which you don’t see in each layer on its own or in the 3-D version.”

Xu and his team wanted to create and explore the properties of a 2-D semiconductor heterostructure made up of two different layers of material, a natural expansion of their previous studies on atomically thin junctions, as well as nanoscale lasers based on atomically thin layers of semiconductors. By studying how laser light interacts with this heterostructure, they gathered information about the physical properties at the atomically sharp interface.

“Many groups have studied the optical properties of single 2-D sheets,” said Seyler. “What we do here is carefully stack one material on top of another, and then study the new properties that arise at the interface.”

The team obtained two types of semiconducting crystals, tungsten diselenide (WSe2) and molybdenum diselenide (MoSe2), from collaborators at Oak Ridge National Laboratory. They used facilities developed in-house to precisely arrange two layers, one derived from each crystal, a process that took a few years to fully develop.

“But now that we know how to do it properly, we can make new ones in one or two weeks,” said Xu.

Getting these devices to emit light posed a unique challenge, due to the properties of electrons in each layer.

“Once you have these two sheets of material, an essential question is how to position the two layers together,” said Seyler. The electrons in each layer have unique spin and valley properties, and “how you position them — their twist angle — affects how they interact with light.”

By aligning the crystal lattices, the authors could excite the heterostructure with a laser and create optically active excitons between the two layers.

“These excitons at the interface can store valley information for orders of magnitude longer than either of the layers on their own,” said Rivera. “This long lifetime allows for fascinating effects which may lead to further optical and electronic applications with valley functionality.”

Now that they can efficiently make a semiconductor heterostructure out of 2-D materials, Xu and his team would like to explore a number of fascinating physical properties, including how exciton behavior varies as they change angles between the layers, the quantum properties excitons between layers and electrically driven light emission.

“There’s a whole industry that wants to use these 2-D semiconductors to make new electronic and photonic devices,” said Xu. “So we’re trying to study the fundamental properties of these new heterostructures for things like efficient laser technology, light-emitting diodes and light-harvesting devices. These will hopefully be useful for clean energy and information technology applications. It is quite exciting but there’s a lot work to do.”

Ever smaller, ever faster, ever cheaper – since the start of the computer age the performance of processors has doubled on average every 18 months. 50 years ago already, Intel co-founder Gordon E. Moore prognosticated this astonishing growth in performance. And Moore’s law seems to hold true to this day.

But the miniaturization of electronics is now reaching its physical limits. “Today already, transistors are merely a few nanometers in size. Further reductions are horrendously expensive,” says Professor Jonathan Finley, Director of the Walter Schottky Institute at TUM. “Improving performance is achievable only by replacing electrons with photons, i.e. particles of light.”

Photonics – the silver bullet of miniaturization

Data transmission and processing with light has the potential of breaking the barriers of current electronics. In fact, the first silicon-based photonics chips already exist. However, the sources of light for the transmission of data must be attached to the silicon in complicated and elaborate manufacturing processes. Researchers around the world are thus searching for alternative approaches.

Scientists at the TU Munich have now succeeded in this endeavor: Dr. Gregor Koblmüller at the Department of Semiconductor Quantum-Nanosystems has, in collaboration with Jonathan Finley, developed a process to deposit nanolasers directly onto silicon chips. A patent for the technology is pending.

The candidate Benedikt Mayer and Masters student Lisa Janker in an experiment at the molecular beam epitaxy in the Walter Schottky Institute of the Technische Universitaet Muenchen am teaching Suhl for semiconductor nanostructures and quantum devices, with Prof. Dr. Jonathan Finley; persons depicted (from left): Benedikt Mayer, Lisa Janker; Location: Walter Schottky Institute, Am Coulombwall 4, 85748 Garching, Germany; Date: 02/10/2016; CREDIT: Uli Benz / TU Muenchen

The candidate Benedikt Mayer and Masters student Lisa Janker in an experiment at the molecular beam epitaxy in the Walter Schottky Institute of the Technische Universitaet Muenchen am teaching Suhl for semiconductor nanostructures and quantum devices, with Prof. Dr. Jonathan Finley; persons depicted (from left): Benedikt Mayer, Lisa Janker; Location: Walter Schottky Institute, Am Coulombwall 4, 85748 Garching, Germany; Date: 02/10/2016; CREDIT: Uli Benz / TU Muenchen

Growing a III-V semiconductor onto silicon requires tenacious experimentation. “The two materials have different lattice parameters and different coefficients of thermal expansion. This leads to strain,” explains Koblmüller. “For example, conventional planar growth of gallium arsenide onto a silicon surface results therefore in a large number of defects.”

The TUM team solved this problem in an ingenious way: By depositing nanowires that are freestanding on silicon their footprints are merely a few square nanometers. The scientists could thus preclude the emerging of defects in the GaAs material.

Atom by atom to a nanowire

But how do you turn a nanowire into a vertical-cavity laser? To generate coherent light, photons must be reflected at the top and bottom ends of the wire, thereby amplifying the light until it reaches the desired threshold for lasing.

To fulfil these conditions, the researchers had to develop a simple, yet sophisticated solution: “The interface between gallium arsenide and silicon does not reflect light sufficiently. We thus built in an additional mirror – a 200 nanometer thick silicon oxide layer that we evaporated onto the silicon,” explains Benedikt Mayer, doctoral candidate in the team led by Koblmüller and Finley. “Tiny holes can then be etched into the mirror layer. Using epitaxy, the semiconductor nanowires can then be grown atom for atom out of these holes.”

Only once the wires protrude beyond the mirror surface they may grow laterally – until the semiconductor is thick enough to allow photons to jet back and forth to allow stimulated emission and lasing. “This process is very elegant because it allows us to position the nanowire lasers directly also onto waveguides in the silicon chip,” says Koblmüller.

GaAs nanowires on a silicon surface - Picture: Thomas Stettner / Philipp Zimmermann / TUM

GaAs nanowires on a silicon surface – CREDIT: Thomas Stettner / Philipp Zimmermann / TUM

Basic research on the path to applications

Currently, the new gallium arsenide nanowire lasers produce infrared light at a predefined wavelength and under pulsed excitation. “In the future we want to modify the emission wavelength and other laser parameters to better control temperature stability and light propagation under continuous excitation within the silicon chips,” adds Finley.

The team has just published its first successes in this direction. And they have set their sights firmly on their next goal: “We want to create an electric interface so that we can operate the nanowires under electrical injection instead of relying on external lasers,” explains Koblmüller.

“The work is an important prerequisite for the development of high-performance optical components in future computers,” sums up Finley. “We were able to demonstrate that manufacturing silicon chips with integrated nanowire lasers is possible.”

The research was funded by the German Research Foundation (DFG) through the TUM Institute for Advanced Study, the Excellence Cluster Nanosystems Initiative Munich (NIM) and the International Graduate School of Science and Engineering (IGSSE) of the TUM, as well as by IBM through an international postgraduate program.

Worldwide silicon wafer area shipments increased 3 percent in 2015 when compared to 2014 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. However, worldwide silicon revenues decreased by 6 percent in 2015 compared to 2014.

Silicon wafer area shipments in 2015 totaled 10,434 million square inches (MSI), up from the previous market high of 10,098 million square inches shipped during 2014. Revenues totaled $7.2 billion down from $7.6 billion posted in 2014. “Semiconductor silicon shipment levels remained strong throughout most of the year, resulting in record volume shipments,” said Dr. Volker Braetsch, chairman SEMI SMG and senior vice oresident of Siltronic AG. “The strength in shipments was not enough to compensate headwinds from further price decline and some exchange rate impact; silicon revenues for the year decreased yet again and are significantly below their market high set in 2007.”

Annual Silicon* Industry Trends

2007

2008

2009

2010

2011

2012

2013

2014

2015
Area Shipments (MSI)

8,661

8,137

6,707

9,370

9,043

9,031

9,067

10,098

10,434
Revenues ($B)

12.1

11.4

6.7

9.7

9.9

8.7

7.5

7.6

7.2

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within SEMI and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

How Texas Instruments got greener, safer and saved money.

BY STEVEN BALLANCE Texas Instruments, Dallas, TX, KARL OLANDER and JOE SWEENEY, Entegris, Billerica, MA

Over the last decade, considerable efforts have been put forth by manufacturers and suppliers to help reduce costs, consumption of natural resources, and where economically viable or by mandate, to become more green in fab operations. In the early 2000s, Texas Instruments (TI) outlined an opportunity to re-think its approach around one of the largest energy and cleanroom air consumption areas in the fab—ion implant operations.

In comparison to other manufacturing tools in the fab, ion implanters require the largest exhaust volume, typically using 2500 CFM in total ventilation, split between the gas box [400+ CFM] and the containment shell enclosure [2000+ CFM]. The energy cost to replace this volume of air equates to about $8,000 per tool and, with up to 30 implanters in a typical fab, the operating costs can reach up to $240K annually. In addition, the investment needed to replace this volume of clean, highly conditioned air is substantial and requires large infrastructure expenditures (FIGURE 1).

Ion Implant 1

In the late 2000s, TI provided the industry with a glimpse of what was possible around air handling and energy reduction in its implant centers. The initial concept, implementation and projected results had been years in the making and were first published in August, 2009 by Solid State Technology, as provided by Steve Russo, then a senior member of TI’s technical staff.

In the article, Russo explained the operating protocols for handling the highly toxic materials utilized in the ion implant process, which are traditionally stored within the tool itself. Now, after years of development and modification, a bigger picture, along with intriguing data, has emerged.

Recycling the shell exhaust

The 2009 article described how TI recycled the implanter shell exhaust within the fab, reducing the make-up air requirement by 80% [2000 CFM per tool]. Fab air is drawn through the implanter shell to dissipate heat from the process and provide dilution in the event of a process leak. This volume of air is treated as general exhaust, and traditionally expelled from the fab using blowers on the roof.

The successful implementation of the first phase, led to the recycle of the shell exhaust on more than 60 ion implant tools across three fabs without incident. Whereas the initial installation included ductwork to convey shell exhaust to the roof (if needed in an emergency), subsequent facilities were built on the premise of continuously returning the shell exhaust to the fab. In practice, the reconfigured exhaust systems amounted to a $57,000 capital cost avoidance per process tool. FIGURE 2 illustrates these cost savings projections.

Ion Implant 2

Recycling the shell exhaust has resulted in avoiding $1.7 million in capital for exhaust and make-up air infrastructure, as well as, reducing annual energy cost by $470,000. The lower energy usage equates to reduced CO2 emissions of 6,500 metric tons. FIGURE 3 illustrates the new design configuration for shell exhaust recycle.

Ion Implant 3

The role of sub-atmospheric pressure gas sources

In redesigning the implant exhaust configuration, Russo and his team he relied on using only the safest gas packaging technology— sub-atmospheric gas sources, or SAGS.

These packages deliver gases below atmospheric pressure, greatly reducing the likelihood of a gas leak and providing the basis to redirect the shell exhaust back into the fab.

It is interesting to note that around the same time Russo published his first article on his new design, the National Fire Protection Agency (NFPA) adopted the SAGS classification for gas packages into the standard. The NFPA classified gas packages that store and deliver gas sub-atmospherically as SAGS Type I and packages that store gas under pressure but deliver gas sub-atmospher- ically as SAGS Type II. Both SAGS systems share a common feature—they require a process vacuum in order to deliver the toxic gas, virtually eliminating accidental gas releases (FIGURE 4).

Ion Implant 4

The initial planning for re-configuring the shell exhaust system in the new design was done to take full advantage of the safety profile of the SAGS packages. Using traditional high pressure delivery systems in the new design wouldn’t have been prudent because of the higher gas leak potential and lower safety profile. Exclusively using SAGS technologies enabled the exhaust reduction program approach. Continuous efforts and success rely on doing everything possible to see that gas delivery is always sub-atmospheric and TI has taken precautions to ensure the gas delivery systems are consistently performing in this way.

Gas box exhaust reductions

The process of lowering implanter shell exhaust began over 12 years ago, and since then most TI tools have been fitted with this design. On its continued quest for reduced energy and costs, TI identified the gas box as being the next best opportunity.

The gas box exhaust, potentially containing hazardous materials, is sent through a scrubber before being released. Scrubbed (or acid) exhausts, therefore, consume more resources than shell exhaust and contribute more to the costs of fab operations.

Over the past few years, Texas Instruments and ATMI, now Entegris, providers of SAGS technologies, have teamed up to continue to look for efficiencies and safety measures in managing exhaust gas and energy usage in ion implant operations. After evaluating the energy reduction potential of the tool gas box exhaust, TI made modifications that led to reduced gas box exhaust rates of about 200 cfm, down from over 400 cfm. This resulted in an additional $800 savings per tool per year. Additional strategies to reduce gas box exhaust rates and improve overall safety are suggested below.

Building an integrated [smart] exhaust system

Today, ion implanters utilize dopant cylinders with manual valves that had their start when “lecture bottles” were first used 30 years ago—and space in the gas box was at a premium. Small cylinders and manual valves were standard. Even as solid source vaporizers were replaced, and the use of gases in larger cylinders became prevalent, the use of manual valves continued.

Interestingly, the Type 1 and Type 2 sub-atmospheric gas delivery cylinders used worldwide to supply implant dopant gases use manual valves. The presence of the manual valve presents a continuing risk because of the possibility of human error during installation and purging sequences which could result in a gas release, albeit small. Yet, there is still room to reduce risk and continue to improve safety through the application of “smart” solutions.

Ultimately, the cornerstone to minimizing the occurrence and impact of a gas leak is all about maintaining the system under sub-atmospheric conditions at all times. Operating under sub-atmospheric pressure entails the continuous monitoring of gas pressure(s) in the delivery manifolds and the ability to respond quickly if pre-set pressure thresholds are exceeded.

The use of normally closed pneumatic valves provides the means to isolate the toxic gas within the dopant cylinder should the delivery manifold deviate from sub-atmospheric pressure protocols. The normally closed condition also removes from consideration cases where valves are either poorly closed or over-torqued. Cylinder cycle purging can then be done automatically, more efficiently and without the possibility of backfilling purge gas into the cylinder.

Varying the gas box flow rate

The ability to minimize the smallest of leaks would allow the gas box to be exhausted as a function of actual risk as opposed to continuously operating at a rate needed to mitigate projected worst-case scenarios. Controlling the gas box exhaust rate using a two position damper is one possible solution.

A two-position damper can control the gas box exhaust in either a low or high flow mode. The normal or reduced exhaust condition is allowed when all of the dopant delivery cylinders are showing a sub-atmospheric pressure condition or all of the cylinder valves are closed. Interlocks initiate the high flow rate any time the gas box door is opened, such as during cylinder changes or maintenance periods, or when triggered by events such as toxic gas detection, smoke detector alarm or detection of a super-atmospheric pressure condition in the dopant delivery manifold. It is estimated that the exhaust system would operate in the low flow mode >95% of the time.

With SAGS, a nominal rate of 40 cfm can be sufficient to satisfy regulations providing a 90% reduction in gas box exhaust requirements.

Taking the next step forward

TI justified recirculating the ion implanter shell exhaust within the fab based on a thorough risk analysis built around using SAGS technology. Over the last decade, they refined the practice and proliferated it across new fab installations, significantly reducing capital require- ments for make-up air.

Developing an integrated exhaust system can ultimately reduce implant make-up air requirements by 98%— without compromising safety. Operating costs associated with the lower exhaust have been proportionately reduced,along with carbon dioxide emissions.

Further advances in exhaust/energy reduction are possible via a partnership between toolmakers, dopant suppliers and fab designers to incorporate an integrated exhaust system for ion implanters, and possibly other tools. It begins with insuring operating gas delivery is under sub-atmospheric pressure conditions all the time.

Future changes may include:

1. Adding pneumatic valve operators to the dopant cylinders

2. Variably exhausting the gas box proportional to actual risk conditions

Outstanding economic and environmental gains can continue to be made – and new standards created – if manufacturers, equipment makers and suppliers work together to envision the possibilities. As an industry, and as responsible corporate citizens, working together to pursue these types of opportunities can reduce energy consumption and exhaust while improving overall process safety.

Based on text, graphics and data originally presented at the 26th Annual IEEE/SEMI Advanced Semiconductors Manufacturing Conference (ASMC 2015), May 3-6, 2015, Saratoga Springs, New York.

STEVEN BALLANCE, P.E., is a facilities engineer at Texas Instruments, Dallas, TX. KARL OLANDER and JOE SWEENEY are with the Electronic Materials division of Entegris, Danbury, CT.