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Inotera appoints new president


November 19, 2015

Inotera’s board of directors announced this week that they have approved the appointment of Mr. Rod Morgan as president, succeeding Dr. Scott Meikle. The change is effective January 1, 2016.

Mr. Morgan is currently Special Assistant of Inotera. Prior to joining Inotera, he was vice president of Procurement at Micron Technology, Inc. Before that, he served as co-executive officer of IM Flash Technologies, LLC. Mr. Morgan joined Micron in 1984 and held numerous leadership roles in manufacturing operations, including Fab Manager, Manufacturing Integration Manager, Key Equipment Group Director, and Site Director.

The board of directors announced that Dr. Pei-Ing Lee, currently serving as president of Nanya Technology Corporation, was elected to be the new chairman of the company. The election is effective November 10, 2015.

Inotera is a DRAM manufacturing venture between US memory giant Micron Technology Inc. and DRAM chipmaker Nanya Technology.

Inotera plans to fully convert all its production to 20nm chips by the end of the second quarter next year. At end of this year, the chipmaker plans to convert 80 percent of its 30nm chips into 20nm.

ON Semiconductor Corporation and Fairchild Semiconductor International Inc. today announced plans for ON Semiconductor to acquire Fairchild for $20.00 per share in an all cash transaction valued at approximately $2.4 billion. The acquisition creates a leader in the power semiconductor market with combined revenue of approximately $5 billion, diversified across multiple markets with a strategic focus on automotive, industrial and smartphone end markets.

“The combination of ON Semiconductor and Fairchild creates a power semiconductor leader with strong capabilities in a rapidly consolidating semiconductor industry. Our plan is to bring together two companies with complementary product lines to offer customers the full spectrum of high, medium and low voltage products,” said Keith Jackson, president and chief executive officer of ON Semiconductor. “The immediate EPS accretion and potential to significantly augment ON Semiconductor’s free cash flow, make the Fairchild acquisition an excellent opportunity for ON Semiconductor stockholders.”

“As part of ON Semiconductor, Fairchild will continue to pioneer technology and design innovation in efficient energy consumption to help our customers achieve success and drive value for our partners and employees around the world,” stated Mark Thompson, chairman and chief executive officer of Fairchild. “We look forward to working closely with the ON Semiconductor team to ensure a smooth transition.”

Following consummation, the transaction is expected to be immediately accretive to ON Semiconductor’s non-GAAP earnings per share and free cash flow, excluding any non-recurring acquisition related charges, the fair value step-up inventory amortization, and amortization of acquired intangibles. ON Semiconductor anticipates achieving annual cost savings of $150 million within 18 months after closing the transaction.

The transaction is not subject to a financing condition. ON Semiconductor intends to fund the transaction with cash from the combined companies balance sheet and $2.4 billion of new debt. The debt financing commitment also includes provisions for a $300 million revolving credit facility which will be undrawn at close. ON Semiconductor remains committed to its share repurchase program, and the agreed upon financing provides flexibility to continue share repurchases going forward.

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CEA-Leti and its partners in the European FP7 project PLAT4M today announced they have built three silicon photonics platforms. The four-year project, which launched in 2013, aims at building a European-based supply chain in silicon photonics and speeding industrialization of the technology. PLAT4M, which is funded by a European Commission grant of 10.2 million euros, includes 15 leading European R&D institutes and CMOS companies, key industrial and research organizations in design and packaging, as well as end users in different application fields, to build the complete supply chain.

Midway through the project, the consortium has developed advanced technologies and tools by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration, and developing a packaging toolkit. The supply chain is based on technology platforms of Leti, imec and STMicroelectronics, supported by a unified design environment. The high level of maturity of the technology offered by these platforms makes them readily accessible to a broad circle of users in a fabless model.

Imec’s silicon photonics platform, based on 200mm substrates, has matured thanks to the PLAT4M project. The platform is based on SOI substrates with 220nm crystalline silicon on a 2,000nm buried oxide. During this project the existing fabrication processes and integration flow have been fine tuned to have stable and repeatable performance for all photonics building blocks (couplers, waveguides, phase shifters, photodetectors). This feeds the process design kit’s robust performance specifications and guarantees quality and first-time-right designs for the platform’s fabless users for high data-rate telecom and non-telecom applications. PLAT4M partners Thales, Polytec and TNO already are using the technology.

Beyond the 200mm platform, imec has pushed the limits of silicon photonics, exploiting advanced optical lithography with its 193nm immersion lithography scanner. It also has demonstrated very low propagation loss (~0.6dB/cm) for fully etched waveguides with excellent within-wafer linewidth control (standard deviation

Using the imec platform, Thales demonstrated a coherent combination of laser beams (CBC). Ultimately, this application aims at producing high-power, high-energy laser sources for sensing, industry or fundamental physics. The CBC rationale is to push the limits of single laser emitters (typically fiber amplifiers) by using a large number of amplifiers and coherently adding the output beams. The coherent addition requires locking the phase of all the amplifying channels. With the number of channels, potentially very large (from tens to thousands), an integrated technology is a major concern in terms of possible industrial products. The first generation CBC demonstrator of PLAT4M, which was packaged by Tyndall UCC, included a one-to-16 channel splitter tree, plus 16 independent thermal phase modulators. The CBC experiment showed the successful coherent addition of 16 laser beams at 1.55µm.

cea-leti supply chain

Leti has developed a new photonic platform based on 200mm SOI wafers. This process offers multilevel silicon patterning that allows the design of various passive and active devices (e.g. modulator and photodiode) with thermal tuning capability. Two AlCu levels are available for routing. A process design kit (PDK) is available for circuit design and an MPW service will be proposed in 2016. State-of-the-art performances have been demonstrated: insertion losses are below 2dB/cm for monomode waveguide and below 0.2dB/cm for multimode devices. Germanium photodiode responsivity is > 0.75A/W for a bandwidth >30GHz. Mach-Zehnder modulator VpLp is in the 2V.cm range for 2V operation with an E/O bandwidth > 25GHz. Moreover, Leti and III-V Lab have developed integrated hybrid III-V lasers and electro-absorption modulators (EAM) on silicon using a wafer-bonding technique. The hybrid lasers operate in the single-mode regime and the EAMs exhibit an extinction ratio higher than 20 dB with a drive voltage lower than 2V. Clear eye diagram has been achieved at a bit-rate of 25 Gb/s, confirming strong potential for telecom applications.

During the project, ST developed an additional silicon-photonic platform in 300mm technology to be used as an R&D tool for proof-of-concept purposes. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is designed for evaluating new devices and subsystems for demonstration. DAPHNE is a flexible platform that perfectly fits R&D needs. While developing it, ST demonstrated wavelength-division-multiplexing solutions using arrayed waveguide gratings, echelle gratings, cascaded Mach-Zehnder interferometers and side-coupled integrated spaced sequence of resonators. Some of the configurations are designed for the 100GBase-LR4 standard, and the experimental characterization results show insertion losses below 0.5dB and channel cross-talks above 25dB for a band flatness of 2nm. Furthermore, proper operation of receiver-and-transmitter blocks to be interfaced to optical devices above them has been demonstrated at 28Gbps, making use of 65nm-node technologies.

The PLAT4M WP2 work has led to a qualitative leap of the design flow for silicon photonics, allowing the photonics community to design more complex and more robust circuits. The electronics OpenAccess standard for data sharing between design-automation tools includes an extension for silicon photonics in a beta phase today. Simulation capabilities were leveraged thanks to an extensive characterization effort from the three partner fabs and thanks to the statistical data gathered for variability prediction. Paris-Sud University has studied theoretically the behavior of different phase shifters and photodetectors for a time-efficient and precise modeling. Mentor Graphics and PhoeniX Software partners have improved phase-aware routing and tool interoperability. Verification and manufacturability have reached industry-requirement standards thanks to the development of new techniques based upon the Mentor Graphics Calibre platform that delivers layout-versus-schematic comparison (Calibre nmLVS), photonic rule checks (PRC) and curvilinear-aware design-rule checks (Calibre nmDRC). Mask preparation is also improving with better pattern-density control and mask correction.

Vacuum technology trends can be seen over the period of innovation defined by Moore’s Law, particularly in the areas of increasing shaft speed, management of pumping power, and the use computer modeling.

BY MIKE CZERNIAK, Edwards UK, Crawley, England

The sub-fab lies beneath. And down there in that thicket of pipes amidst the hum of vacuum pumps, the sentinel of gas combustors and the pulse of muscular machinery doing real work — innovation has also played a crucial role in enabling Moore’s Law. Without it the glamor boys up top with their bunny suits and FOUPS would not have achieved the marvelous feats of engineering derring-do for which they are so deservedly celebrated.

Vacuum and abatement are two of the most critical functions of the sub-fab. Many process tools require vacuum in the process chamber to permit the process to function. Vacuum pumps not only provide the required vacuum, they also remove unused process gases and by-products. Abatement systems then treat those gasses so they are safe to release or dispose. Vacuum and abatement systems in the sub-fab have had to innovate just as dramatically as the exposure, deposition and etch tools of the fab. In many cases, new processes would not have been possible without new vacuum pumps that could handle new materials and new abatement systems that could make those materials safe for release or disposal.

Moore’s Law

Moore’s Law originated in a paper published in 1965 and titled “Cramming More Components onto Integrated Circuits,” written by Gordon Moore, then director of research and engineering at Fairchild Semiconductor [1]. In it Moore observed that the economics of the integrated circuit manufacturing process defined a minimum cost at a certain number of components per circuit and that this number had been doubling every two years as the manufacturing technology evolved. He believed that the trend would continue for at least the short term, and perhaps as long as ten years. His observation became a mantra for the industry, soon to be known as Moore’s Law (FIGURE 1).

Vaccuum 1

More an astute observation than a law, Moore’s Law is remarkable in several respects. First, the rate of improvement it predicts, doubling every two years, is unheard in any other major industry. In “Moore’s Curse” (IEEE, March 2015) Vaclav Smil calculated historical rates of improvement for a variety of essential indus- tries over the last couple of centuries and found typical rates of a few percent, and order of magnitude less than Moore’s rate [2]. Second, is its longevity. Moore thought it was good for the short term, perhaps as long as ten years. This is perhaps due, at least partly, to the unique role Moore’s Law has assumed within the semicon- ductor industry where it has become both a guide to and driver of the pace of innovation. The Law has become a guiding principle – you shall introduce a new generation with double the performance every two years. It is a rule to live by, enshrined in the industry’s roadmap, and violated only at great peril. Only painfully did Intel recently admit that the doubling period for its latest generation appeared to have stretched to something more like two and a half years [3]. To an extent the Law is a self-fulfilling prophecy, which some have argued works to the detriment of the industry when it forces the release of new processes before they are fully optimized. Whatever you might think of it, the Law’s persistence is remarkable. The literature is full of dire predictions of its demise, all of which, at least so far, have proven premature.

Finally we must ask, what is meant by the names assigned to each new node? What exactly does 14nm, the current state of the art, mean? Although Moore originally described the number of components per integrated circuit, the Law was soon interpreted to apply to the density of transistors in a circuit. This was variously construed. Some measured it as the size of the smallest feature that could be created, which determined the length of the transistor gate. Others pointed to the spacing between the lines of the first layer of metal conductors connecting the transistors, the metal-1 half-pitch. These may have been a fairly accurate measures twenty years ago at the 0.35μm node, but node names have since steadily lost their connection to physical features of the device. It would be difficult to point to any physical dimension at the 14nm node that is actually 14nm. For instance, the FinFET transistor in a 22nm chip is 35nm long and the fin is 8nm wide.

What remains true is that in each successive generation the transistors are smaller and more densely packed and performance is significantly increased. Each generation seems to be named with a smaller number that is approximately 70% of the previous generation, reflecting the fact that a 70% shrink in linear dimension equates to a 50% reduction in area and therefore a nominal doubling in transistor density.

Enabling Moore’s Law in the sub-fab: A brief chronology

In the 1980s, new semiconductor processes and increasing gas flows associated with larger diameter wafers led to problems with aggressive chemicals and solids collecting in the oil used in oil-lubricated “wet” pumps, resulting in short service intervals and high cost of ownership. These were resolved by the development and introduction of oil-free “dry pumps” which have subsequently become the semiconductor industry standard.

Dry rotary pumps require extremely tight running clearances and multiple stages to achieve a practical level of vacuum. Additional cost of these machines, however was more than offset by the benefits offered to semiconductor manufacturing. Dry pumps use a variety of pumping mechanisms — roots, claw, screw and scroll (FIGURE 2).

Vaccuum 2

Many of these are new concepts, but modern machining capabilities made it possible to produce them at a realistic cost, the most notable being Edwards’ introduction of the first oil-free dry pump in the 1980’s. Each pumping mechanism has been successfully deployed and each has its own advantages and disadvantages in a given application. The scroll pump, for example, is unique in its ability to economically scale down to much smaller sizes.

In the early 1990s it became apparent that with the introduction of dry pumps, the pump oil no longer acted as a “wet scrubber” to collect process by-product gases, which therefore passed into the exhaust system. The solution was the development of the Gas Reactor Column (GRC) to chemically capture process exhaust gases in a disposable/recyclable cartridge, minimizing exhaust emissions to the atmosphere.

At about the same, new, more aggressive process gases being used in leading-edge semiconductor processes posed significant challenges for turbo molecular pumps (TMPs) due to the damage they caused to the mechanical bearings used to support their high-speed rotating shafts (typically ~40,000 rpm). Turbo pumps use rapidly spinning blades to impart direction to gas molecules, propelling them through multiple stages of increasing pressure. Early turbo pumps used oil- or grease-lubricated bearings. Similar to the problems encountered with oil sealed rotary pumps, the new process chemicals tended to degrade the oil, frequently causing pumping failures in as little as a few weeks. This problem was solved by introducing magnetic bearings to levitate the pump drive shaft and eliminate the need for lubricating oil.

In the mid-1990s the semiconductor industry started to use perfluorinated compounds (PFC’s) as a convenient source of chamber cleaning and etch gases. However, since only ~30% of the input gas was consumed in the process chamber, there were considerable PFC emissions to the atmosphere. Of particular concern was CF4 due to its half-life of 50,000 years. The solution was the Thermal Processor Unit which offered the first system with proven destruction reaction efficiency (DRE) of 90% or more for CF4.

In the 2000’s safety concerns regarding the increasing use of toxic gases led to increasing concerns about the abatement of these materials before they were released to the environment and the safety of personnel within the fab. Integrated vacuum and abatement systems, where everything is contained in a sealed and extracted enclosure, offer a significant improvement in safety. Integrated systems have since been refined with improvements such as a common control system, reduced footprint and installation costs, and shorter pipelines to reduce operating and maintenance costs.

Abatement systems have continued to evolve. New processes using new materials often require a different approach the abatement. For example, new technologies were developed for high hydrogen processes, copper interconnects and low k dielectrics.

Trends and prospects

Certain vacuum technology trends can be seen over this history of innovation, particularly in the areas of increasing shaft speed, management of pumping power, and the use computer modeling to monitor performance and predict when maintenance will be required so that it can be synchronized with other activities in the fab.

Shaft Speed

When dry pumps were first introduced, they typically operated at around 3,000 to 3,600 rpm. Today’s dry pumps use electric drives to run considerably faster, typically 6,000 rpm for claw, screw, and multi-stage roots pumps (FIGURE 3).

Vaccuum 3

Increasing a pump’s rotational speed delivers a number of advantages. It makes it possible to build more compact pumps and motors, with less internal leakage, which in turn, enables a reduction in the number of pump stages required. It also allows the speed to be reduced when wafers are not being processed, thereby saving energy. Combined, these benefits help reduce the overall pump cost.

Each type of pumping mechanism has different characteristics in the size and shape of volume to fill. A scroll mechanism, with a narrow, ported inlet and long, thin volume space, is one of the slowest pumping mechanisms to fill, so its performance does not increase in proportion to increasing shaft speed. Most scroll pumps operate at just 1500 rpm. A roots mechanism, by contrast, has a very large opening and a short volume length, enabling it to fill quickly allowing efficient use of higher shaft speeds.

The conductance ceiling for roots and screw pumps is probably ~15,000 rpm. Achieving this speed, will require incremental improvements in materials, bearings, and drives. It is likely that we will reach the conductance ceiling for most of the current primary pumping mechanisms within the next decade, although some, such as roots and screw mechanisms, may prove more durable than others.

Turbomolecular pump conductance is governed by blade speed and molecular velocities. Turbo performance has been limited primarily by the maximum speed the bearings and rotor can withstand. The industry is looking for new materials that are lighter and stronger to enable increased speed. While this pump type may be reaching its conductive limit on heavier gases, it is far from reaching it for lighter gases, such as hydrogen. This may take a much longer time to achieve.

Power management

Significant advances have been made in improving the energy efficiency of both vacuum pumps and abatement systems. Improvements in pump design have increased energy efficiency. Variable speed motors and controllers allow better matching of the motor speed to varying pump requirements. Idle mode allows both pumps and abatement systems to go into a low power mode when not in use. Improvements in burner design have reduced the fuel consumption of combustion based abatement. With the increase in concern about environmental impact and carbon foot print continued improvement in this area can be expected.

Modeling

Computer modeling has been applied extensively to all stages of pump performance. Such variables as stage size, running clearance, leakage, and conductance can all be modeled quite effectively. This allows design simulation and the optimization of performance, such as the shape of the power and speed curve. In this way, a pump can be designed for specific duties, such as load lock pumping or processing high hydrogen flows (FIGURE 4).

Vaccuum 4

Vacuum pumps of the future will be more reliable and capable of operating for longer periods of time before requiring maintenance. They will be safer to operate, will occupy less fab space, run cleaner and require less power, as well as generate less noise, vibration, and heat. They will also have improved corrosion resistance and the ability to run hotter when required.

As a result, vacuum pumps will be more environmentally friendly, running cleaner and using less power to help reduce their carbon footprint. In addition, they will likely make much greater use of recycled materials and use fewer consumables, thereby helping to reduce overall pump costs. The pumps will be easier to clean, repair, and rebuild for reuse.

Likely technical developments will also include higher shaft speeds, a growing proliferation of pump mechanisms and combinations of mechanisms to increase performance. Finally, vacuum pumps will incorporate new materials and improved modelling to further sharpen performance and reduce system and operating costs.

References

1. G. Moore, “Cramming more Components onto Integrated Circuits” in Electronics, April 19, 1965.
2. V. Smil, “Moore’s Curse” in IEEE Spectrum, March 19, 2015.
3. R. Courtland, “The Status of Moore’s Law: It’s Complicated” in IEEE Spectrum October 28, 2013.

MIKE CZERNIAK is the Environmental Solutions Business Development Manager, Edwards UK, Crawley, England.

Recent trends and future directions for wafer bonding are reviewed, with a focus on MEMS.

BY ERIC F. PABO, CHRISTOPH FLÖTGEN, BERNHARD REBHAN, PAUL LINDNER and THOMAS UHRMANN, EV Group, St. Florian, Austria

All devices and products are evaluated to varying degrees on the following factors: 1) availability or assurance of supply, 2) cooling requirements, 3) cost, 4) ease of integration, 5) ease of use, 6) performance, 7) power requirements, 8) reliability, 9) size, and 10) weight. MEMS devices are no exception and the explosive growth of MEMS devices during the last decade was driven by substantial improvements in some of the aforementioned variables. MEMS manufacturing is based on patterning, deposition and etch technologies developed over the last 50 years for the manufacturing of ICs along with the relatively new technologies of aligned wafer bonding and deep reactive ion etch (DRIE). This article will review the recent trends and future directions for wafer bonding with a focus on MEMS along with some mention of wafer bonding for RF and power devices.

The incredible growth in MEMS over the last 20 years has been enabled by the development of the DRIE process by Bosch and by aligned wafer bonding. Many MEMS devices have very small moving parts, which must be protected from the external environment. Initially, this was done using special packages at the die level, which was relatively expensive. Wafer-level capping of MEMS devices seals a wafer’s worth of MEMS devices in one operation, and these capped devices can then be packaged in a much simpler and lower-cost package. Anodic bonding and glass frit bonding were the initial bonding processes used for MEMS and are often referred to as “tried and true.” However, both of these processes have challenges, and as a result, few new MEMS products and processes are being developed using these processes.

Anodic bonding requires the presence of Na or some other alkali ion which causes several problems. The first is that Na ions are driven to the exterior of the wafer during the bonding process and will accumulate on the bonding tooling, requiring the tooling be cleaned on a periodic basis. The second is that Na can cause CMOS circuits to fail – preventing anodic bonding from being used to combine MEMS and CMOS. Almost all MEMS devices require a CMOS ASIC to process the output signal from the MEMS device. Historically, this integration has been done at the package level with wire bonding but now some high-volume products are available where the integration of the CMOS and the MEMS is done as part of the wafer-level capping process. Also, anodic bonding typically requires a maximum process temperature of over 400 ̊C and the presence of a strong electric field during bonding. The high temperature influences the throughput of the bonding process and some devices cannot tolerate the high electric field.

Even though the majority of the MEMS parts that exist today were probably bonded using glass frit, this wafer bonding process has several challenges as well. The major one is that the glass frit is applied and patterned using a silk screen process, which has a typical resolution in the 250 to 300μm range. This means that as the size of the MEMS die decreases, an ever greater percentage of the wafer surface is consumed by the bond line, which limits the number of die per wafer and increases the cost per die. FIGURE 1 shows the effect of bond line width and die size on the percentage of the wafer surface that is consumed by the bond line [1]. Also, many of the glass frits contain Pb to lower the glass transition temperature. Although the amount of Pb is very small, there is widespread concern regarding the use of Pb and being RoHS (Restriction of Hazardous Substance) compliant.

Wafer bonding 1

 

Both anodic bonding and glass frit bonds are nonconductive and therefore not suitable for the formation of connections to electrically conductive through silicon vias (TSVs) at the same time as the seal ring is formed. This means that these processes are not as suitable for the 3D integration of CMOS and MEMS.

For MEMS applications there is a strong trend toward the use of metal-based wafer bonding; in particular, liquid metal-based processes such as solder, eutectic and transient liquid phase (TLP). This trend is driven by the aforementioned challenges with anodic and glass frit bonding. Moving from glass frit to a metal-based bonding for a die size of 2mm2 can result in up to a 100% increase in the die per wafer. This doubling of the die per wafer will result in an approximately 50% decrease in the cost per MEMS die.

Some of the metal-based aligned-wafer-bonding processes that are currently used in high-volume manufacturing are: Au-Au thermo-compression bonding, which has been in volume production for over 10 years; and Al-Ge eutectic bonding, which is very popular even though it requires a very careful process setup and control and has a peak process temperature of over 400 ̊C. Cu-Sn transient liquid phase (TLP) wafer bonding, another metal-based process, is used in low-volume production of hermetically sealed devices such as micro-bolometers [2] but is not currently used in medium- or high-volume production. Cu-Sn TLP wafer bonding also requires very careful design and control of the metal stack as well as the bonding process.

The maximum process temperature that is required for a bonding process has three significant effects. The first is that the bonding process takes longer as the maximum process temperature increases due to the increased time required to heat up to the bonding temperature from the loading temperature and the time required to cool down to the unload temperature. The bonding process time determines the throughput of the wafer bonder(s) and factors into the cost of ownership (CoO) for the bonding process. The second is that the process temperature required for bonding may damage the devices on the wafers being bonded. The aluminum metallization of certain CMOS devices may be damaged at tempera- tures greater than 450 ̊C. The VOx or vanadium oxide used on the sensor pixels for micro-bolometers will be damaged by temperatures greater than 200 ̊C. The third is the internal stress that is created when wafers with mismatched coefficients of thermal expansion (CTE) are bonded together at an elevated temperature. In this case the higher the bonding temperature, the higher the internal stress at room temperature.

Unless the bonding metals are noble metals such as Au, oxides will form on the metal layer and have a negative effect on the bonding process – making an oxide management strategy necessary. This oxide management strategy can have elements that prevent the oxide from growing using special storage conditions or coatings, removing the oxide before bonding, and heating in an inert or reducing environment. In some cases, the bonding process can also be adjusted to overcome the effect of the oxides by increasing the pressure, temperature and time for the bonding process.

There is substantial interest in bonding processes and equipment that are capable of removing the native oxide from metals and other materials prior to wafer bonding and preventing the regrowth of oxide. Equipment capable of running such a process will have several substantial advantages. The first is that it will allow materials that have been previously difficult to bond to be bonded at or near room temperature. For example, Al-Al thermo-compression wafer bonding without the removal of the native oxide has previously been demonstrated, but required a process temperature of greater than 500 ̊C, which made the process unattractive for production [3]. Low temperature Al-Al thermo-compression bonding has been demonstrated by using a special surface treatment and doing all handling in a high vacuum environment (FIGURE 2). A low-temperature Al-Al thermo-compression bonding process has the advantage of using an inexpensive readily available conductive material and increased throughput due to the low process temperature. In addition to being used to form the seal ring, this low-temperature Al-Al bonding could be used for the 3D integration of MEMS and CMOS through the use of TSVs filled with Al.

Wafer bonding 2

This surface pretreatment and handling in high vacuum enables covalent bonding of two wafers at or near room temperature with no oxide in the interface. This process has several very significant advantages. The first is that the low process temperature allows the bonding of substrates with substantially different CTE such as LiNbO3 or LiTaO3 to Si or glass. This combination of materials has drawn the interest of RF filter manufacturers due to its ability to reduce the temperature sensitivity of surface acoustic wave (SAW) devices. The second is that materials with both a CTE mismatch and a lattice mismatch can be bonded together without the development of major crystalline defects that can arise when forming the material stack by growing one crystalline layer on top of another when there is a lattice mismatch. One interesting possibility is bonding GaN to diamond for applications where large amounts of heat must be removed from the GaN device. In addition, bonding a thin layer of monocrystalline SiC to a polycrystalline SiC could offer wafers with the electrical performance of monocrystalline SiC at a cost closer to the cost of polycrystalline SiC. Another application of this bonding process is to join materials such as GaInP, GaAs, GaInAsP and GaInAs for fabrication of quadruple junction concentrated solar cells with record conversion efficiency of 44.7% [4, 5].

A high-vacuum cluster tool capable of aligned wafer bonding offers significant advantages for MEMS applications where the vacuum level in the cavity after bonding is important, such as gyroscopes and micro-bolometers (FIGURE 3) [6]. Modules can be added to the base cluster tool to enable the wafers to be baked out at a controlled elevated temperature prior to alignment and bonding in high vacuum. Getter activation can also be done in the bake-out module without loading or saturating the getter, as all subsequent steps are done in high vacuum. For devices where getter activation requires a high temperature and the other wafer has thermal limits, two bake-out chambers allow a high-temperate bake-out and getter activation while the other chamber performs a lower-temperature bake out. For example, micro-bolometers that used vanadium oxide on the detector pixel have a thermal limit of about 200 ̊C, whereas the cap wafer contains a getter that should be activated around 400 ̊C. Also, the high-vacuum capability is beneficial for producing devices that are heated and use vacuum for thermal isolation because a higher vacuum reduces the heat loss, which reduces the power required to maintain the fixed temperature.

Wafer bonding 3

This high-vacuum cluster tool allows the separation of the process steps of bake out, surface treatment, alignment and bonding as well as allows the tool to be configured to the specific application needs. Also, the cluster tool base makes it possible to develop modules for specific applications without redesigning the entire tool.

The availability of reliable, highly automated, high-volume aligned wafer bonding systems and processes was one of the keys to the growth of MEMS over the past 15 years. The next 15 years are expected to be an exciting period of advancement for aligned wafer bonding as new equipment and processes are introduced, such as the tools and processes that allow separate pre-processing of the top and bottom wafer, as well as all handling, alignment, and bonding in vacuum. The cluster tools that will be used to do this will allow for further innovation by adding new modules to the cluster tool. In addition, the ability to remove surface oxides prior to bonding, prevent these oxides from reforming, bond at or near room temperature, and have a strong, oxide-free, optically transparent, conductive bond with very low metal contamination will allow many new product innovations for RF filters, power devices and even products that have not yet been thought of.

References

1. E. F. Pabo, “Metal Based Bonding – A Potential Cost Reducer?,” in MEMS MST Industry Conference, Dresden, 2011.
2. A. Lapadatu, “High Performance Long Wave Infrared Bolometer Fabricated by Wafer Bonding,” Proc. SPIE, vol. 7660, no. 766016-12.
3. E.Cakmak,“Aluminum Thermocompression Bonding Characterization,” in MRS Fall Mtg, Boston, 2009.
4. Fraunhofer ISE, Fraunhofer ISE Teams up with EVGroup to Enable Direct Semiconductor Wafer Bonds for Next-Generation Solar Cells, Freiburg: Press Release, 2013.
5. F. Dimroth, “Wafer bonded four-junction GaInP/GaAa/GaInAsP/ GaInAs,” Progress in Photonics, vol. 22, no. 3, pp. 277-282, 2014.
6. V.Dragoi,“Wafer Bonding for Vacuum Encapsulated MEMS,” Proc. SPIE9517 Smart Sensor, Actuators, and MEMS VII, 2015.

ERIC F. PABO is Business Development Manager, MEMS; CHRISTOPH FLÖTGEN, and BERNHARD REBHAN are scientists, PAUL LINDNER is Executive Technology Director and THOMAS UHRMANN is Director Of Business Development at EV Group, St. Florian, Austria

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT.

BY LAURENT PAIN, RALUCA TIRON, LUDOVIC LATTARD, STEFAN LANDIS and CYRILLE LAVIRON, CEA-Leti, Grenoble, France

The Internet of Things (IoT) is expected to fuel significant growth opportunities for the semiconductor industry, as demand increases for wireless components and more and more embedded functionalities such as memory and sensors. This growth will affect almost all integrated circuit (IC) sectors (FIGURE 1). The chip industry will continue to need advanced technologies to provide the most powerful functionalized ICs with lower power consumption for the IoT, but manufacturing costs remain a key challenge. Lithography and related patterning technologies can represent up to 50 percent of total IC production costs, and significant efforts have to be made in the coming years to slow and even reverse this trend.

Litho Fig 1

In the lithography landscape for the development of advanced technology nodes, extreme-UV (EUV) lithography technology recovered some credibility at the beginning of 2015 with the release and installation of the first 80W power sources[1]. However, its adoption by the industry remains uncertain, because its infrastructure still requires significant development. Also, the recurrent questions about the real cost of ownership associated with the ability of the 0.33NA platform to address sub-7nm technology nodes continue to dominate the debate in the semiconductor community, especially since 3D-stacking strategies are being seriously investigated. This potentially could slow demand for high-resolution and therefore delay the new advanced lithography solutions.

Meanwhile, 193nm immersion lithography, with double- or quadruple-patterning strategies, supports the industry preference for advanced-node developments, despite the tremendous effort required for process controls (alignment, mask manufacturing etc.). In this landscape, lithography alternatives maintain promise for continued R&D because they may present competitive compromises for the industry. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits for IC manufacturers. In addition, directed self-assembly (DSA) lithography with block copolymer shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies, and therefore the associated mask-set budgets. But what is the current status of these technologies? Are they really able to meet industry expectations for advanced technology nodes? Are they indeed able to reduce manufacturing costs? What are their introduction points into the production environment?

CEA-Leti is working to answer these questions and has initiated collaborative R&D programs to assess and boost the development of these alternative technologies through strategic partnerships. Three programs have been launched with the primary goals of demonstrating that these lithography options can meet industry needs, assessing industrial use of them and proposing to Leti’s IDM partners real turn-key integrated process-flow solutions.

  • IMAGINE: launched in 2009 with MAPPER Lithography, this program is pushing for the insertion of massively parallel direct-write electron-beam technology. Other participants include TSMC, STMicroelectronics, Nissan Chemical, Mentor Graphics, SCREEN, Tokyo Electron and Aselta Nanographics.
  • IDEAL: DSA lithography represents a promising solution for advanced patterning. Leti has worked with Arkema since 2011 on the qualification and demonstration of materials for insertion into industrial production flow. Other partners include ST, Tokyo Electron, SCREEN, Mentor Graphics and CNRS-LCPO.
  • INSPIRE: established in 2015 with the EV Group, this program will focus on the assessment of imprint technology on large-scale patterning.

Directed self assembly: the resolution is in polymer matrix

Since 2010, DSA has steadily attracted attention of R&D laboratories and the IDM industry. The natural high-resolution capability of the block copolymer (sub-10nm) may meet the requirements of future technology nodes. Significant work in this area is underway at R&D consortia such as imec, IBM Research in Albany, N.Y., and Leti, as well as directly in the fab[2,3]. For example, Leti and its partners put in place a full infrastructure to qualify the new material developed by the chemical company Arkema (FIGURE 2). A full 300mm line is operational at Leti using a Tokyo Electron track and a customized SCREEN DUO track able to handle the latest process possibilities. This type of infrastructure is required to validate in fab-like conditions the new materials (PS-PMMA and high chi platforms) and their associated integration flows. Those operating conditions give industry the capability to quickly evaluate the full process-flow performances with all the required classic statistical data for final validation.

Litho Fig 2

Focusing on defectivity Intel showed convincing data at 1def/cm2 on line-and-space structures, confirming the potential of DSA to reach the ITRS target and therefore to be used for manufacturing in the near future (FIGURE 3). As well, Leti results on grapho-epitaxy process are also very encouraging with zero visual-defect process flow for contact/via application measured with low statistical level[4]. Those results are the first positive key trends in the DSA technology. Evaluating the compatibility of DSA with semiconductor process flows is the next important step. The control of the iso-dense configuration focused a lot of attention on the grapho-epitaxy process, in which block copolymer film-filling uniformity is affected by the topography effects of the guide patterns. Leti developed and patented a flow allowing a proper control of CD and CDU in all density configurations. (FIGURE 4) This solution preserves the interest of DSA as it is integrated in the process flow itself and because it does not imply a need for any additional design-rule restriction[4].

Litho Fig 3

Nevertheless, some hurdles remain to be overcome before its final adoption. The control of the surface affinity is one key aspect. It can greatly affect the final defectivity level and impact the complexity of the integration flow (FIGURE 5). Any non-uniform control of the bottom residual polymer thickness in the bottom of the guide cavity may lead to post-etch opening issues and final circuit-yield drop. Moreover, to be fully adopted, DSA technology also must be aligned with the compatible design rule manuals. Insertion in the DRM is essential and it implies adding new specific constraints due to the nature of the block copolymer and to the lithography guide realization. All these R&D efforts must be pushed to value the advantages of DSA technology: the natural high resolution of this solution and its cost effectiveness from reducing multi-exposure strategy. In addition to ensuring DSA’s ability to extend 193nm immersion lithography,it also supports the use of the EUV 0.33NA tool for the development of 7nm nodes and below.

Litho Fig 4

Massively parallel electron-beam writing

Despite recurrent delays in new developments, parallel electron-beam lithography remains an attractive alternative option. The massively parallel writing solutions developed by MAPPER Lithography and IMS Nanofab-rication for wafer and mask writing, respectively, offer good compromises: a significant alliance of resolution and advantageous manufacturing costs. But this technology also benefits from additional advantages, such as writing flexibility and a significant throughput improvement due to the parallel exposure concept that can boost the throughput in the future up to 100 wafers per hour in a cluster-tool configuration. First pre-industrial units are today installed in pilot-line environments, foreshadowing their introduction into production lines in coming years.

MAPPER and Leti’s collaboration is focused on introducing this technology for direct-write application. This joint program started in 2009 around the MAPPER’s pre-alpha tool that validated the key concept of the MAPPER technology in terms of parallel writing and resolution capabilities (FIGURE 6). The partnership entered in a new phase in 2014 with the installation of the first FLX-1200 pre-production platform, (FIGURE 7), operating 1,300 beam lines for a targeted throughput of 1 wph and then scalable to 10 wph by increasing the beam line count up to 13,000.

Litho Fig 5 Litho Fig 6

This FLX-1200, which is being ramped up now, already has shown imaging performances that match its specifications. Full 300mm wafers can be printed in one hour with 32nm half-pitch resolution (FIGURE 8). In the IMAGINE program, Leti and its partners are also working to validate a complete turn-key integrated solution allowing fast and secure wafer processing from design to silicon. Such infrastructure developments around data treatment, materials, process, etch and metrology will be required to speed-up the insertion of the MAPPER technology into future production lines.

Litho Fig 7

Leti and MAPPER will demonstrate the operational capability of the FLX-1200 in its final configuration, including mix-and-match alignment performances. The achievement of this key demonstration milestone is essential to launching this technology. Then, after final ramp-up, the MAPPER platform is expected to be aligned in terms of specifications with 14nm technology (32nm hp). A wide range of potential applications based on its mask-less concept and throughput potential already have been clearly identified: CMOS prototyping and low-volume production, complementary lithography concept for high-end patterning[6], new industry segments (photonics, low-cost circuit functionalization, large field exposure, etc.).

Nano-imprint lithography

Nano-imprint lithography (NIL) stands out from the other conventional lithography processes (photo-lithography, electronic lithography, EUV lithography) because of the fundamental mechanism of creating the final structures. In the case of nano-imprint, the flow of the resist directly shapes the pattern through the stamp cavities, eliminating the need for chemical contrast, as is the case for optical lithography resists. In recent decades, significant efforts have been made to extend the distance between the photomask and the resist-coated wafer to reduce defectivity and enhance resolution. Therefore, for many scientists, NIL technology appeared to be a UFO, since the process is based on the intimate contact between the working stamp and the resist to be embossed.

In the past 20 years, significant progress has been made to make the technology more mature and ready for high-volume manufacturing. Among the several existing NIL technology alternatives, the UV-based imprint, using transparent stamp, is today the standard one. Two well-established options are now available on the market: the full-wafer imprint (the size of the stamp corresponds to the size of the wafer to be printed) and the step-and-flash imprint in which a small stamp (i.e. die size) is stepped, as in optical lithography across the wafer to be processed (FIGURE 9).

Litho Fig 8

If the step-and-flash NIL technology is better suited to address the semiconductor markets (NAND flash memory, DRAM and logic) with its high level-alignment capability and its good control of defectivity density[7], the full-wafer NIL option could quickly become the reference manufacturing option for the emerging and growing markets such as LED and photonics-based devices (FIGURE 10).

Litho Fig 9

However, this wafer-scale imprint solution still lacks quantitative data regarding its technology assessment for high-volume manufacturing. Commercial equipment[8] and resists, the cornerstones of this technology, are already available. But some links in the industrial supply chain (design rules, master manufacturing and repair, in-line defectivity and metrology controls, fully integrated process flows) still must be established and qualified to make this technology more mature.

To accelerate adoption of this technology, Leti and EV Group launched in June 2015 a new collaborative industrial program called INSPIRE, aimed at demonstrating the benefits of this full-wafer NIL technology and spreading its use for applications beyond the traditional semiconductor industry. Much more than a classic industrial partnership, the program is designed to support development of new applications from the feasibility-study stage up to the first manufacturing steps, including the prototyping phase in Leti’s clean room. INSPIRE is also designed to demonstrate the technology’s cost-of-ownership benefits for a wide range of application domains. The final objective of this program is to facilitate the transfer of the developed integrated process solutions to industrial partners. The steps should significantly lower the entry barrier for NIL technology and speed up its use in production lines.

Conclusion

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT. Besides conventional optical lithography, they offer industry new and/or complementary advantages: innovation capability and opportunities to better manage cost of ownership. But not only that! The high-resolution potential, the ability to facilitate design-innovation validation, and the complementarity of these alternatives with other patterning solutions also highlight their strengths. The step now is to finalize the evaluation of these technologies with respect to industry standards and establish them as real and credible lithography alternatives.

References

1. A. Schafgans et al, Proc SPIE, Extreme Ultraviolet Lithography VI, Vol. 9422, 2015
2. S. Sayan et al, Proc. SPIE, Advances in Patterning Materials and Processes XXXII, Vol. 9425, 2015
3. H. Tsai et al, ACS nano, vol 8 (5), pp. 5227-5232, 2014
4. R. Tiron et al, Alternative Lithographic Technologies II, Vol. 9423, 2015

By Dr. Lianfeng YangLianfeng Yang, Vice President of Marketing, ProPlus Design Solutions, Inc.

The squeaky wheel gets the grease, or so it seems in the semiconductor industry, as the high level of the design process seems to get the most attention. Meanwhile, the transistor level appears to have been largely forgotten.

With increasing complexities and scale of electronic system, design and verification have moved up the abstraction level from register transfer level (RTL) to the electronic system level (ESL) with help from high-level synthesis software and other new EDA technologies. Portable stimulus is available at ESL to test specifications and virtual platforms enable early software consideration, for example.

Throughout, transistor-level challenges are ongoing but appear to be largely forgotten. New process technologies, such as FinFET, increasingly stress transistor-level verification tools, in particular, SPICE and FastSPICE simulators, and designer needs are greater. Highly accurate and reliable verification and sign-off tools for large post-layout simulation is one of many.

When designers move to 16/14 nanometer and beyond with FinFETs, accuracy is a priority and essential for characterization, verification and signoff, due to reduced Vdd and the impact of process variations. Device characteristics and physical behavior is more complicated with these process nodes. Circuit size is increasing and design margins are shrinking. Every aspect that contributes to leakage and power must be measured and accurately modeled. The entire circuit, including all parasitic components, has to be simulated accurately.

While circuit designers may not be squeaky wheels, they do need to be confident of their designs, as they’re under the pressure from ever-increasing design and manufacturing complexities and cost. FastSPICE simulators used in final verification and signoff do not offer enough accuracy. This is true for small currents critical to low-power design and achieving sufficient noise margins. Often, FastSPICE simulations rely on special, fine-tuned options and start with non-converged DC, further challenging accuracy.

Designers use FastSPICE to verify timing and power before tapeout. Unfortunately, they can’t be sure of the results, risk expensive respins and missing market windows, for applications sensitive to small current or noise elements, such as advanced memory designs. This is an all-too-familiar scenario where wheels should be squeaking.

What sends the situation out of control is FastSPICE’s lack of a golden to refer. FastSPICE provides many options for designer to tune to trade-off accuracy and speed, which worked in past generations. Such an option tuning strategy, however, becomes unreliable for advanced designs where designers have much less design margin than before. Designers now see more and more failure or inaccurate cases due to fundamental accuracy limitations of FastSPICE.

Traditional SPICE simulators were the “golden” simulator to validate FastSPICE, but only for small blocks as no commercially available SPICE simulator can offer simulation capacity for verification and signoff that FastSPICE used. And such validation can’t automatically scale up. The circuit size continues to increase and giga-scale designs are common. At 16nm and beyond, 3D device structures add greater capacity and accuracy challenges. FastSPICE simply doesn’t offer enough confidence and may introduce unpredictably inaccurate or wrong verification results, which designers don’t want to risk for tapeout.

Well, circuit designers may not be squeaking, but help is on the way nevertheless. A new type of SPICE simulator known as giga-scale SPICE simulators or GigaSpice, is able to support giga-scale circuit simulation and verification with a pure SPICE engine. It features SPICE accuracy and FastSPICE-like capacity and performance through advanced parallelization technology. It does not require option tuning and always converges on DC, making it easy for designers to adopt and offering accurate and reliable results for designers. GigaSpice can be a golden reference for FastSPICE and a replacement for memory characterization, large block simulation and full-chip verification.

The squeaky wheel may be noisy, but a few clever developers have been paying attention to the new developments for transistor-level verification and signoff and are responding.Giga-scale SPICE simulators are fast becoming part of circuit-level design flows for squeaky wheel results.

Dr. Lianfeng Yang currently serves as the ProPlus Design Solutions’ vice president of marketing and general manager of Beijing R&D Center. Previously, he was a senior product engineer leading the efforts on product engineering and technical support for the modeling product line to Asian customers at Cadence Design Systems, Inc. Dr. Yang holds a Ph.D. degree in Electrical Engineering from the University of Glasgow, UK.

Gartner, Inc. forecasts that 6.4 billion connected things will be in use worldwide in 2016, up 30 percent from 2015, and will reach 20.8 billion by 2020. In 2016, 5.5 million new things will get connected every day.

Gartner estimates that the Internet of Things (IoT) will support total services spending of $235 billion in 2016, up 22 percent from 2015. Services are dominated by the professional category (in which businesses contract with external providers in order to design, install and operate IoT systems), however connectivity services (through communications service providers) and consumer services will grow at a faster pace.

“IoT services are the real driver of value in IoT, and increasing attention is being focused on new services by end-user organizations and vendors,” said Jim Tully, vice president and distinguished analyst at Gartner.

Enterprises to Bolster IoT Revenue

“Aside from connected cars, consumer uses will continue to account for the greatest number of connected things, while enterprise will account for the largest spending,” said Mr. Tully. Gartner estimates that 4 billion connected things will be in use in the consumer sector in 2016, and will reach 13.5 billion in 2020 (see Table 1).

Table 1: Internet of Things Units Installed Base by Category (Millions of Units)

Category 2014 2015 2016 2020
Consumer 2,277 3,023 4,024 13,509
Business: Cross-Industry 632 815 1,092 4,408
Business: Vertical-Specific 898 1,065 1,276 2,880
Grand Total 3,807 4,902 6,392 20,797

Source: Gartner (November 2015)

In terms of hardware spending, consumer applications will amount to $546 billion in 2016, while the use of connected things in the enterprise will drive $868 billion in 2016 (see Table 2).

Table 2: Internet of Things Endpoint Spending by Category (Billions of Dollars)

Category 2014 2015 2016 2020
Consumer 257 416 546 1,534
Business: Cross-Industry 115 155 201 566
Business: Vertical-Specific 567 612 667 911
Grand Total 939 1,183 1,414 3,010

Source: Gartner (November 2015)

In the enterprise, Gartner considers two classes of connected things. The first class consists of generic or cross-industry devices that are used in multiple industries, and vertical-specific devices that are found in particular industries.

Cross-industry devices include connected light bulbs, HVAC and building management systems that are mainly deployed for purposes of cost saving. The second class includes vertical-specific devices, such as specialized equipment used in hospital operating theatres, tracking devices in container ships, and many others.

“Connected things for specialized use are currently the largest category, however, this is quickly changing with the increased use of generic devices. By 2020, cross-industry devices will dominate the number of connected things used in the enterprise,” said Mr. Tully.

 

By Dr. Dan Tracy, Senior Director, Industry Research and Statistics, SEMI

With the recent release of Apple’s 6s and the form factors of internet enabled mobile devices and the emergence of the IoT (Internet of Things), advanced packaging is clearly the enabling technology providing solutions for mobile applications and for semiconductor devices fabricated at 16 nm and below process nodes. These packages are forecasted to grow at a compound annual growth rate (CAGR) of over 15% through 2019.  In addition, the packaging technologies have evolved and continue to evolve so to meet the growing integration requirements needed in newer generations of mobile electronics. Materials are a key enabler to increasing the functionality of thinner and smaller package designs and for increasing the functionality of system-in-package solutions.

Figure 1: Packaging Technology Evolution – Great Complexity in Smaller, Thinner Form Factors, courtesy of TechSearch International, Inc.

Figure 1: Packaging Technology Evolution – Great Complexity in Smaller, Thinner Form Factors, courtesy of TechSearch International, Inc.

The observations related to mobile products include:

  • New package form factors to satisfy high-performance, high-bandwidth, and low power consumption requirements in a thinner and smaller package.
  • Packaging solutions to deliver systems-in-package capabilities while satisfying low-cost requirements.
  • Shorter lifetimes and differing reliability requirements. For example, high-end smartphones and tablets, the key high reliability requirement is to pass the drop test; and packaging material solutions are essential to delivering such reliability.
  • Shorter production ramp times to meet time-to-market demands of end product. This is becoming critical and causes redundancy in capacity to be required, capacity that is underutilized for part of the year

Packaging must provide a low-cost solution and have an infrastructure in place to meet steep ramps in electronic production. The move towards bumping and flip chip has only accelerated with the growth in mobile electronics, though leadframe and wirebond technologies remain as important low-cost alternatives for many devices. Wafer bumping has been a major packaging market driver for over a decade, and with the growth in mobile the move towards wafer bumping and flip chip has only accelerated with finer pitch copper pillar bump technology ramping up. Mobile also drives wafer-level packaging (WLP) and Fan-Out (FO) WLP. New wafer level dielectric materials and substrate designs are required for these emerging package form factors.

Going forward, the wearable and IoT markets will have varying packaging requirements depending on the application, the end use environment, and reliability needs. Thin and small are a must though like other applications cost versus performance will determine what package type is adopted for a given wearable product, so once more leadframe and wirebonded packages could be the preferred solution. And in many wearable applications, materials solutions must provide a lightweight and flexible package.

Such packaging solutions will remain the driver for materials consumption and new materials development, and the outlook for these packages remain strong. Materials will make possible even smaller and thinner packages with more integration and functionality.  Low cost substrates, matrix leadframe designs, new underfill, and die attach materials are just some solutions to reduce material usage and to improve manufacturing throughput and efficiencies.

SEMI and TechSearch International are once again partnering to prepare a comprehensive market analysis of how the current packaging technology trend will impact the packaging manufacturing materials demand and market.  The new edition of “Global Semiconductor Packaging Materials Outlook” (GSPMO) report is a detailed market research study in the industry that quantifies and highlights opportunities in the packaging material market. This new SEMI report is an essential business tool for anyone interested in the plastic packaging materials arena. It will benefit readers to better understand the latest industry and economic trends, the packaging material market size and trend, and the respective market drivers in relation to a forecast out to 2019. For example, FO-WLP is a disruptive technology that impacts the packaging materials segment and the GSPMO addresses this impact.

 

November 2, 2015 — Tsinghua Unigroup Ltd., a Chinese government-owned chipmaker will make a $600 million investment in Powertech Technology of Taiwan, according to multiple reports. Powertech Technology, which specializes in chip packaging and testing, will hand over 25% of the company in exchange, after new shares are issued.

According to the Wall Street Journal, Powertech will use the funds to “help it expand its assembly capacity in Taiwan, develop advanced production processes and recruit talent. It would also become Tsinghua Unigroup’s major chip assembly and testing partner.”

Tsinghua is the largest chip design company in China, and earlier this year attempted to acquire Micron Technology with a $23 billion bid. That bid ultimately failed, but it hasn’t stopped Tsinghua from investing in other US companies in the industry, including Western Digital ($3.78 billion for 15%) and Hewlett-Packard’s data-networking business (51%, $2.3 billion).

This continues the unprecedented consolidation that has come to the semiconductor industry in 2015. A trend that has shown no signs of slowing as we enter 2016.

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To help readers follow this constantly changing situation, Solid State Technology is keeping a running scorecard of all the significant transactions in the semiconductor market here: Historic era of consolidation for chipmakers.