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When University of Oregon associate professor Ramesh Jasti began making tiny organic circular structures using carbon atoms, the idea was to improve carbon nanotubes being developed for use in electronics or optical devices. He quickly realized, however, that his technique might also roll solo.

In a new paper, Jasti and five University of Oregon colleagues show that his nanohoops — known chemically as cycloparaphenylenes — can be made using a variety of atoms, not just those from carbon. They envision these circular structures, which efficiently absorb and distribute energy, finding a place in solar cells, organic light-emitting diodes, or as new sensors or probes for medicine.

Though barely one-nanometer, nanohoops offer a new class of structures for use in energy or light devices. (Courtesy of Ramesh Jasti)

Though barely one-nanometer, nanohoops offer a new class of structures for use in energy or light devices. (Courtesy of Ramesh Jasti)

The research, led by Jasti’s doctoral student Evan R. Darzi, was described in a paper placed online ahead of print in ACS Central Science, a journal of the American Chemical Society. The paper is a proof-of-principle for the process, which will have to wait for additional research to be completed before the full impact of these new nanohoops can be realized, Jasti said.

These barely one-nanometer nanohoops offer a new class of structures — sized between those made with long-chained polymers and small, low-weight molecules — for use in energy or light devices, said Jasti, who was the first scientist to synthesize these types of molecules in 2008 as a postdoctoral fellow at the Molecular Foundry at the Lawrence Berkeley National Laboratory.

“These structures add to the toolbox and provide a new way to make organic electronic materials,” Jasti said. “Cyclic compounds can behave like they are hundreds of units long, like polymers, but be only six to eight units around. We show that by adding non-carbon atoms, we are able to move the optical and electronic properties around.”

Nanohoops help solve challenges related to materials with controllable band gaps — the energies that lie between valance and conduction bands and is vital for designing organic semiconductors. Currently long materials such as those based on polymers work best.

“If you can control the band gap, then you can control the color of light that is emitted, for example,” Jasti said. “In an electronic device, you also need to match the energy levels to the electrodes. In photovoltaics, the sunlight you want to capture has to match that gap to increase efficiency and enhance the ability to line up various components in optimal ways. These things all rely on the energy levels of the molecules. We found that the smaller we make nanohoops, the smaller the gap.”

To prove their approach could work, Darzi synthesized a variety of nanohoops using both carbon and nitrogen atoms to explore their behavior. “What we show is that the charged nitrogen makes a nanohoop an acceptor of electrons, and the other part becomes a donator of electrons,” Jasti said.

“The addition of other elements like nitrogen gives us another way to manipulate the energy levels, in addition to the nanohoop size. We’ve now shown that the nanohoop properties can be easily manipulated and, therefore, these molecules represent a new class of organic semiconductors — similar to conductive polymers that won the Nobel Prize in 2000,” he said. “With nanohoops, you can bind other things in the middle of the hoop, essentially doping them to change properties or perhaps sense an analyte that allows on-off switching.”

His early work making nanohoop compounds was carbon-based, with the idea of making them different diameters and then combining them, but his group kept seeing unique and unexpected electronic and optical properties.

Jasti, winner of a National Science Foundation Career Award in 2013, brought his research from Boston University to the UO’s Department of Chemistry and Biochemistry in 2014. He said the solar cell research being done by his colleagues in the Materials Science Institute, of which he is a member, was an important factor in his decision to move to the UO.

“We haven’t gotten very far into the application of this,” he said. “We’re looking at that now. What we were able to see is that we can easily manipulate the energy levels of the structure, and now we know how to exchange any atom at any position along the loop. That is the key discovery, and it could be useful for all kinds of semiconductor applications.”

Co-authors with Darzi and Jasti were: former BU doctoral student Elizabeth S. Hirst, who now is a postdoctoral fellow at the U.S. Army Natick Soldier Research, Development and Engineering Center; UO doctoral student Christopher D. Weber; Lev N. Zakharov, director of X-ray crystallography in the UO’s Advanced Materials Characterization in Oregon center; and Mark C. Lonergan, a professor in the Department of Chemistry and Biochemistry.

The NSF (grant CHE-1255219), Department of Energy (DE-SC0012363), Sloan Foundation and Camille and Henry Dreyfus Foundation supported the research.

The Centre of Process Innovation (CPI) has announced that it is part of a UK based collaboration to develop the next generation of ultra-barrier materials using graphene for the production of flexible transparent plastic electronic based displays such as those required for the next generation of smartphones, tablets and wearable electronics.

The UK is a world leader in the field of graphene innovation and the market is predicted to be worth more than £800m by 2023. The graphene market could transform the manufacturing landscape in the UK if new materials, processes, equipment and metrology can be developed effectively in concert. The project combines the skills from each of the partners (University of Cambridge, FlexEnable Ltd, the National Physical Laboratory, and the Centre for Process Innovation) and expects to deliver a feasible material and process system. It builds upon significant existing investments by InnovateUK and the EPSRC in this area. The resulting ultra-barrier material can be potentially used in a wide range of novel applications by the lead business partner, FlexEnable.

The twelve month project titled “Gravia” funded under the Innovate UK “realising the graphene revolution” call will investigate the feasibility of producing graphene-based barrier films for next generation flexible OLED lighting and display products. However current commercially available barrier layers used to protect the electronics in display screens have limitations with regards to flexibility. In order to realize the commercialization of such applications, display manufacturers have to be able to source flexible barrier platforms such as graphene on which they can fabricate their displays.

The incorporation of graphene interlayers offers great potential for flexible displays. Its gas blocking properties will enable barrier materials that are not only flexible, but also transparent, robust, and very impervious to many molecules. Gravia will seek to accelerate product development, improving upon current ultra barrier performance and lifetimes by producing consistent barrier materials and processes on large area substrates by utilizing specialist growth techniques. The key challenge will be to develop large-area poly-crystalline graphene films which maximize performance whilst mitigating process imperfections. In this way, solutions can be produced at scale and economically viable in the future.

The demonstration of feasible working prototypes will represent a significant achievement in the race to bring wearable electronics and plastic displays to the mass market. The project is exploring the necessary industrial process parameters to ensure that the barriers produced are not only of high performance but also at a price point that allows market adoption. Measuring barriers at very low levels of permeability requires sensitive and accurate tests. Collaborating with the National Physical Laboratory (NPL) will ensure that the data claims are correct and meaningful comparisons can be made in the future with the very latest and most sensitive equipment. Future development work will focus on transferring the technology from proof of concept to pilot production scale.

James Johnstone, Business Development Manager at CPI, said: “The collaboration brings together world class supply chain expertise across the UK to bridge the gap from Graphene research to the manufacturing of commercial flexible display screens. The Hofmann group at the Department of Engineering in Cambridge is a key innovator in the growth and processing of graphene films. NPL are experts in the traceable measurement of water transfer characteristics and FlexEnable brings an industrial focus to the project with their extensive expertise in the manufacture of flexible electronics and flexible display screens in particular. CPI’s role in the project is to use roll-to-roll atomic layer deposition technologies to scale up, test and fabricate the ultra barrier materials.”

Chuck Milligan, CEO FlexEnable adds: “Graphene and other 2D materials are extremely relevant for the flexible electronics industry, with the potential for broad usage from conductors to semiconductors, insulators and even barriers. Building on FlexEnable’s previous leading-edge work with graphene, our involvement will enable the accelerated integration of these game-changing materials in a new generation of ultra-flexible end-user applications with innovative form factors.”

Research reported in the Japanese Journal of Applied Physics by researchers at Mitsubishi Electric Corporation describes the development of a new power module made from a SiC metal-oxide-semiconductor field-effect transistor and a SiC Schottky barrier diode. The team successfully trialed the module in a train traction inverter — a device used to convert the direct current from the power source to three-phase alternating current suitable for driving the propulsion motors — with promising results.

Power electronics: Silicon carbide gains traction
Next-generation power electronics capable of reducing energy consumption are in high demand, particularly in the transportation industries. A key way of saving energy in electronics is by reducing the losses inherent in switching processes and power conversion. Much attention is now being given to a compound form of silicon and carbon called silicon carbide (SiC) for electronic components, a material whose properties outperform conventional silicon in terms of thermal conductivity, loss reduction and the ability to withstand high voltages.

Researchers in Japan have developed new power modules comprising all silicon carbide (SiC) MOSFETs (a) and SBDs (b). The power modules show great promise in improving the performance and efficiency of traction inverters for trains, reducing switching losses by 55% compared with conventional inverters.

Researchers in Japan have developed new power modules comprising all silicon carbide (SiC) MOSFETs (a) and SBDs (b). The power modules show great promise in improving the performance and efficiency of traction inverters for trains, reducing switching losses by 55% compared with conventional inverters.

Satoshi Yamakawa and co-workers at Mitsubishi Electric Corporation have developed a new power module made from a SiC metal-oxide-semiconductor field-effect transistor (MOSFET) and a SiC Schottky barrier diode (SBD). The team successfully trialed the module in a train traction inverter – a device used to convert the direct current from the power source to three-phase alternating current suitable for driving the propulsion motors — with promising results.

For a power module in a traction inverter, low power loss, miniaturization, high voltage rating, and high temperature environmental resistance are required.

Yamakawa and his team prepared the SiC MOSFET for the power module by n-type doping the junction field-effect transistor region: this reduced on-resistance of the device at high temperatures. By combining the SiC MOSFET with a SiC SBD — a diode which allows for fast and efficient switching — the team created a power module for a traction inverter rated at 3.3kV/1500A.

A new traction inverter system equipped with their power module is stable, highly efficient and reduces switching losses by 55% compared with conventional silicon-based inverters.

Reference and affiliation
Kenji Hamada1, Shiro Hino1,2, Naruhisa Miura1,2, Hiroshi Watanabe1,2, Shuhei Nakata1,2, Eisuke Suekawa3, Yuji Ebiike3, Masayuki Imaizumi3, Isao Umezaki3, and Satoshi Yamakawa1,2. 3.3kV/1500A power modules for the world’s first all-SiC traction inverter. Japanese Journal of Applied Physics  54 04DP07 (2015) http://dx.doi.org/10.7567/JJAP.54.04DP07

1. Advanced Technology R&D Center, Mitsubishi Electric Corporation, Amagasaki, Hyogo 661-8661, Japan
2. R&D Partnership for Future Power Electronics Technology (FUPET), Minato, Tokyo 105-0001, Japan
3. Power Device Works, Mitsubishi Electric Corporation, Fukuoka 819-0192, Japan

This research is featured in the September 2015 issue of the JSAP Bulletin.

IEEE S3S 2015 could be the turning point for monolithic 3D. From October 4-7 we will have the option to get a short course, invited and selected presentations from a broad range of the industry representatives. They include major vendors such as Qualcomm, Global Foundries, and Applied Materials; leading research organization like CEA Leti, Taiwan National Applied Research Labs, German IMS Chips, and NASA; leading Universities like Berkeley and Stanford; and start-ups like SiGen and MonolithIC 3D.

In its tutorial session, Qualcomm will explain why it is investing in and promoting 3D VLSI (3DV) as an alternative scaling technology, as is illustrated by the following two slides:

GameChang2-0_Fig1GameChange2-0_Fig2

Yet many people still have doubts, as reflected by the title of the panel we were invited to participate in — “Monolithic 3D: Will it Happen and if so…” — at the IEEE 3D-Test Workshop on October 9, 2015.

The doubts likely relate to the technology challenge that is illustrated in the following slide:

GameChange2-0_Fig3

The question, in short, is how we can add more transistors monolithically interconnected to the underlying transistors without exceeding the thermal budget for the underlying transistors and interconnect.

The current paths to monolithic 3D involve major changes to the front line process flow and require the development of a new logic transistors. The big concern is that leading edge vendors are too busy with dimensional scaling and if anything else could be done it seems that FD-SOI would be it, while trailing edge fabs are, in most cases, avoiding any major transistor process development. The recent failure of Suvolta could be an indication of this reality.

Hence the importance of Game-Changing 2.0, a major technology innovation to be unveiled on Wednesday by MonolithIC 3D in a paper titled: “Modified ELTRAN (R) – A Game Changer for Monolithic 3D”. The paper will present a novel use of the ELTRAN process developed by Canon about 20 years ago, primarily for SOI applications. Using ELTRAN (Epi. Layer Transfer) techniques, a substrate could be prepared enabling any fab to simply integrate a monolithic 3D device without the need to change its current front-line fab process. This flow is further simplified and could be integrated with the monolithic 3D flow introduced last year that leverages the emerging precision bonders, such as EVG’s Gemini (R) XT FB. This flow provides a natural path for product innovation and an unparalleled competitive edge to its adopters. In addition, this game-changing breakthrough offers a very cost-competitive flow. The following chart illustrates the original use of ELTRAN process for the fabrication of SOI wafers:

GameChange2-0_Fig4

In the “Invited Talks on M3DI” at the conference we will have an opportunity to learn from the inventor of the ELTRAN process, Dr. Takao Yonehara, currently with Applied Materials, in his “Epitaxial Layer Transfer Technology and Application” talk. Prior to Applied Materials, Dr. Yonehara worked with Solexel, a Silicon Valley startup, to deploy the ELTRAN process for low cost solar cell fabrication. Yonehara’s talk will be followed by Prof. Joachin Burghartz of Institute for Microelectronics in Stuttgart, discussing “Ultra-thin Chips for Flexible Electronics and 3D ICs” that uses a variation of such flow in small scale production.

The semiconductor industry is bifurcating these days into a segment that follows aggressive scaling for few super-value applications supported by very few vendors, while the bulk of the industry is enhancing old fabs targeting mainstream applications and the emerging IoT opportunities. Further enhancing these older fabs with monolithic 3D offers a most effective return on investment. Game-Changing 2.0 means that without a need for major process R&D efforts or new equipment, the path for 3D scaling is now open with enormous advantages for IoT. Accordingly, my answer to the original question above is summarized by the title of our invited talk at the IEEE 3D-Test Workshop: “Monolithic 3D is Already Here — the 3D NAND — and Now it would be Easy to Adapt it for Logic.”

In addition the other division, SOI and SubVt provide good complementing technology updates for the power-performance objectives that are so important for these emerging markets.

So, come to the S3S and enjoy unique key technologies update with the great wine and country pleasures of Sonoma Valley.

IBM Research today announced an engineering breakthrough that could accelerate carbon nanotubes replacing silicon transistors to power future computing technologies.

IBM scientists demonstrated a new way to shrink transistor contacts without reducing performance of carbon nanotube devices, opening a pathway to dramatically faster, smaller and more powerful computer chips beyond the capabilities of traditional semiconductors. The results will be reported in the October 2 issue of Science.

IBM’s breakthrough overcomes a major hurdle that silicon and any semiconductor transistor technologies face when scaling down. In any transistor, two things scale: the channel and its two contacts. As devices become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now. These results could overcome contact resistance challenges all the way to the 1.8 nanometer node — four technology generations away.

Carbon nanotube chips could greatly improve the capabilities of high performance computers, enabling Big Data to be analyzed faster, increasing the power and battery life of mobile devices and the Internet of Things, and allowing cloud data centers to deliver services more efficiently and economically.

Silicon transistors, tiny switches that carry information on a chip, have been made smaller year after year, but they are approaching a point of physical limitation. With Moore’s Law running out of steam, shrinking the size of the transistor — including the channels and contacts — without compromising performance has been a vexing challenge troubling researchers for decades.

IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers — the equivalent of 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology. IBM’s new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip, pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry. By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is eyeing a post-silicon future, and delivering on its $3 billion chip R&D investment announced in July 2014.

“These chip innovations are necessary to meet the emerging demands of cloud computing, Internet of Things and Big Data systems,” said Dario Gil, vice president of Science & Technology at IBM Research. “As silicon technology nears its physical limits, new materials, devices and circuit architectures must be ready to deliver the advanced technologies that will be required by the Cognitive Computing era. This breakthrough shows that computer chips made of carbon nanotubes will be able to power systems of the future sooner than the industry expected.”

A New Contact for Carbon Nanotubes

Carbon nanotubes represent a new class of semiconductor materials that consist of single atomic sheets of carbon rolled up into a tube. The carbon nanotubes form the core of a transistor device whose superior electrical properties promise several generations of technology scaling beyond the physical limits of silicon.

Electrons in carbon transistors can move more easily than in silicon-based devices, and the ultra-thin body of carbon nanotubes provide additional advantages at the atomic scale. Inside a chip, contacts are the valves that control the flow of electrons from metal into the channels of a semiconductor. As transistors shrink in size, electrical resistance increases within the contacts, which impedes performance. Until now, decreasing the size of the contacts on a device caused a commensurate drop in performance — a challenge facing both silicon and carbon nanotube transistor technologies.

IBM researchers had to forego traditional contact schemes and invented a metallurgical process akin to microscopic welding that chemically binds the metal atoms to the carbon atoms at the ends of nanotubes. This “end-bonded contact scheme” allows the contacts to be shrunk down to below 10 nanometers without deteriorating performance of the carbon nanotube devices.

“For any advanced transistor technology, the increase in contact resistance due to the decrease in the size of transistors becomes a major performance bottleneck,” Gil added. “Our novel approach is to make the contact from the end of the carbon nanotube, which we show does not degrade device performance. This brings us a step closer to the goal of a carbon nanotube technology within the decade.”

ASML Holding NV (ASML) today announced the first shipment of its new TWINSCAN (TM) NXT:1980Di immersion lithography system to support increasingly demanding multiple-patterning performance requirements. Demonstrating 1.2 nanometer (nm) dedicated chuck overlay and better than 10 nm focus uniformity, the NXT:1980Di features new grid calibrations and hardware that enables chipmakers to achieve tighter process windows for next-generation process nodes. The NXT:1980Di also improves throughput by 10% to 275 wafers per hour.

ASML_Twinscan_NXT_1980Di_Left_Open_print_37731“Whether our customers face increased process complexity due to multiple patterning or plan to add Extreme Ultraviolet lithography, an improved level of immersion patterning is required in all leading-edge semiconductor manufacturing environments,” Bert Koek, Senior Vice President of DUV Product Marketing at ASML said. “The NXT:1980Di is a major leap forward in overlay, focus control and productivity, providing a cost-effective solution for chipmakers to further extend immersion lithography, and ultimately Moore’s Law.”

In future nodes, chipmakers are expected to use both immersion lithography and next-generation Extreme Ultraviolet (EUV) lithography, creating additional overlay requirements beyond the standard node-to-node improvements. The NXT:1980Di is specifically designed to accommodate the mix-and-match use with EUV, achieving about 2 nm matched-machine overlay.

The NXT:1980Di is currently available to customers. All TWINSCAN NXT:1970Ci systems can be upgraded in the field to the performance level of an NXT:1980Di. ASML also provides an upgrade path for previous TWINSCAN NXT models to further extend chipmakers’ capital investment. Additionally, as part of a rich portfolio of upgrade options, ASML offers add-on capabilities with the NXT:1980Di to address unique application needs, like a contrast enhancing alignment sensor to further improve overlay.

When the world’s leading scientists and engineers in micro/nanoelectronics convene in Washington, D.C. this December for the 61st annual IEEE International Electron Devices Meeting (IEDM), the subjects under discussion will encompass a range of topics critical to the continuing progress of the industry:

  • how to make transistors that are vanishingly small
  • a growing emphasis on low-power devices for mobile & Internet of Things (IoT)
  • alternatives to silicon transistors
  • 3D IC technology
  • a broad range of papers that address some of the fastest-growing specialized areas in micro/nanoelectronics, including silicon photonics, physically flexible circuits and brain-inspired computing.

The 2015 IEDM will take place at the Washington D.C. Hilton Hotel from December 7-9, 2015, preceded by day-long short courses on Sunday, Dec. 6 and a program of 90-minute tutorials on Saturday, Dec. 5. In addition to a technical program of some 220 papers, other events will take place during the meeting, including evening panels, special focus sessions, IEEE awards, and an entrepreneurial luncheon sponsored by IEDM and IEEE Women in Engineering.

Back for the third year, the 2015 IEDM will feature a slate of designated focus sessions on topics of special interest. This year’s topics are:

  • Neural-Inspired Architectures: From Ultra-Low Power Devices To Applications
  • 2D Layered Materials And Applications
  • Power Devices And Their Reliability On Non-Native Substrates
  • Flexible Hybrid Electronics
  • Silicon-Based Nano-Devices For Detection Of Biomolecules And Cell Functions

“From its inaugural meeting until today, the IEDM conference has been the place where breakthroughs that drive the electronics industry forward are unveiled,” said Mariko Takayanagi, IEDM 2015 Publicity Chair and Senior Manager at Toshiba. “For example, at the IEDM in 1975 Intel’s Gordon Moore gave a talk that refined his earlier prediction of transistor scaling into what has since become known as Moore’s Law. That tradition of attracting the best speakers and a large, diverse audience from around the world continues, with a focus this year on devices intended to support the Internet of Things and other emerging areas of importance that depend upon advances in semiconductor technology.”

To the growing list of two-dimensional semiconductors, such as graphene, boron nitride, and molybdenum disulfide, whose unique electronic properties make them potential successors to silicon in future devices, you can now add hybrid organic-inorganic perovskites. However, unlike the other contenders, which are covalent semiconductors, these 2D hybrid perovskites are ionic materials, which gives them special properties of their own.

Researchers at the U.S. Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) have successfully grown atomically thin 2D sheets of organic-inorganic hybrid perovskites from solution. The ultrathin sheets are of high quality, large in area, and square-shaped. They also exhibited efficient photoluminescence, color-tunability, and a unique structural relaxation not found in covalent semiconductor sheets.

“We believe this is the first example of 2D atomically thin nanostructures made from ionic materials,” says Peidong Yang, a chemist with Berkeley Lab’s Materials Sciences Division and world authority on nanostructures, who first came up with the idea for this research some 20 years ago. “The results of our study open up opportunities for fundamental research on the synthesis and characterization of atomically thin 2D hybrid perovskites and introduces a new family of 2D solution-processed semiconductors for nanoscale optoelectronic devices, such as field effect transistors and photodetectors.”

Yang, who also holds appointments with the University of California (UC) Berkeley and is a co-director of the Kavli Energy NanoScience Institute (Kavli-ENSI), is the corresponding author of a paper describing this research in the journal Science. The paper is titled “Atomically thin two-dimensional organic-inorganic hybrid perovskites.” The lead authors are Letian Dou, Andrew Wong and Yi Yu, all members of Yang’s research group. Other authors are Minliang Lai, Nikolay Kornienko, Samuel Eaton, Anthony Fu, Connor Bischak, Jie Ma, Tina Ding, Naomi Ginsberg, Lin-Wang Wang and Paul Alivisatos.

Traditional perovskites are typically metal-oxide materials that display a wide range of fascinating electromagnetic properties, including ferroelectricity and piezoelectricity, superconductivity and colossal magnetoresistance. In the past couple of years, organic-inorganic hybrid perovskites have been solution-processed into thin films or bulk crystals for photovoltaic devices that have reached a 20 percent power conversion efficiency. Separating these hybrid materials into individual, free-standing 2D sheets through such techniques as spin-coating, chemical vapor deposition, and mechanical exfoliation has met with limited success.

In 1994, while a PhD student at Harvard University, Yang proposed a method for preparing 2D hybrid perovskite nanostructures and tuning their electronic properties but never acted upon it. This past year, while preparing to move his office, he came upon the proposal and passed it on to co-lead author Dou, a post-doctoral student in his research group. Dou, working mainly with the other lead authors Wong and Yu, used Yang’s proposal to synthesize free-standing 2D sheets of CH3NH3PbI3, a hybrid perovskite made from a blend of lead, bromine, nitrogen, carbon and hydrogen atoms.

“Unlike exfoliation and chemical vapor deposition methods, which normally produce relatively thick perovskite plates, we were able to grow uniform square-shaped 2D crystals on a flat substrate with high yield and excellent reproducibility,” says Dou. “We characterized the structure and composition of individual 2D crystals using a variety of techniques and found they have a slightly shifted band-edge emission that could be attributed to structural relaxation. A preliminary photoluminescence study indicates a band-edge emission at 453 nanometers, which is red-shifted slightly as compared to bulk crystals. This suggests that color-tuning could be achieved in these 2D hybrid perovskites by changing sheet thickness as well as composition via the synthesis of related materials.”

The well-defined geometry of these square-shaped 2D crystals is the mark of high quality crystallinity, and their large size should facilitate their integration into future devices.

“With our technique, vertical and lateral heterostructures can also be achieved,” Yang says. “This opens up new possibilities for the design of materials/devices on an atomic/molecular scale with distinctive new properties.”

The research was supported by DOE’s Office of Science. The characterization work was carried out at the Molecular Foundry’s National Center for Electron Microscopy, and at beamline 7.3.3 of the Advanced Light Source. The Molecular Foundry and the Advanced Light Source are DOE Office of Science User Facilities hosted at Berkeley Lab.

Rectennas in Baratunde A. Cola's NEST (NanoEngineered Systems and Transport) lab

Rectennas in Baratunde A. Cola’s NEST (NanoEngineered Systems and Transport) lab

Using nanometer-scale components, researchers have demonstrated the first optical rectenna, a device that combines the functions of an antenna and a rectifier diode to convert light directly into DC current.

Based on multiwall carbon nanotubes and tiny rectifiers fabricated onto them, the optical rectennas could provide a new technology for photodetectors that would operate without the need for cooling, energy harvesters that would convert waste heat to electricity–and ultimately for a new way to efficiently capture solar energy.

In the new devices, developed by engineers at the Georgia Institute of Technology, the carbon nanotubes act as antennas to capture light from the sun or other sources. As the waves of light hit the nanotube antennas, they create an oscillating charge that moves through rectifier devices attached to them. The rectifiers switch on and off at record high petahertz speeds, creating a small direct current.

Billions of rectennas in an array can produce significant current, though the efficiency of the devices demonstrated so far remains below one percent. The researchers hope to boost that output through optimization techniques, and believe that a rectenna with commercial potential may be available within a year.

“We could ultimately make solar cells that are twice as efficient at a cost that is ten times lower, and that is to me an opportunity to change the world in a very big way” said Baratunde Cola, an associate professor in the George W. Woodruff School of Mechanical Engineering at Georgia Tech. “As a robust, high-temperature detector, these rectennas could be a completely disruptive technology if we can get to one percent efficiency. If we can get to higher efficiencies, we could apply it to energy conversion technologies and solar energy capture.”

The research, supported by the Defense Advanced Research Projects Agency (DARPA), the Space and Naval Warfare (SPAWAR) Systems Center and the Army Research Office (ARO), is reported September 28 in the journal Nature Nanotechnology.

Developed in the 1960s and 1970s, rectennas have operated at wavelengths as short as ten microns, but for more than 40 years researchers have been attempting to make devices at optical wavelengths. There were many challenges: making the antennas small enough to couple optical wavelengths, and fabricating a matching rectifier diode small enough and able to operate fast enough to capture the electromagnetic wave oscillations. But the potential of high efficiency and low cost kept scientists working on the technology.

“The physics and the scientific concepts have been out there,” said Cola. “Now was the perfect time to try some new things and make a device work, thanks to advances in fabrication technology.”

Using metallic multiwall carbon nanotubes and nanoscale fabrication techniques, Cola and collaborators Asha Sharma, Virendra Singh and Thomas Bougher constructed devices that utilize the wave nature of light rather than its particle nature. They also used a long series of tests–and more than a thousand devices–to verify measurements of both current and voltage to confirm the existence of rectenna functions that had been predicted theoretically. The devices operated at a range of temperatures from 5 to 77 degrees Celsius.

Adobe Photoshop PDF

Fabricating the rectennas begins with growing forests of vertically-aligned carbon nanotubes on a conductive substrate. Using atomic layer chemical vapor deposition, the nanotubes are coated with an aluminum oxide material to insulate them. Finally, physical vapor deposition is used to deposit optically-transparent thin layers of calcium then aluminum metals atop the nanotube forest. The difference of work functions between the nanotubes and the calcium provides a potential of about two electron volts, enough to drive electrons out of the carbon nanotube antennas when they are excited by light.

In operation, oscillating waves of light pass through the transparent calcium-aluminum electrode and interact with the nanotubes. The metal-insulator-metal junctions at the nanotube tips serve as rectifiers switching on and off at femtosecond intervals, allowing electrons generated by the antenna to flow one way into the top electrode. Ultra-low capacitance, on the order of a few attofarads, enables the 10-nanometer diameter diode to operate at these exceptional frequencies.

“A rectenna is basically an antenna coupled to a diode, but when you move into the optical spectrum, that usually means a nanoscale antenna coupled to a metal-insulator-metal diode,” Cola explained. “The closer you can get the antenna to the diode, the more efficient it is. So the ideal structure uses the antenna as one of the metals in the diode–which is the structure we made.”

The rectennas fabricated by Cola’s group are grown on rigid substrates, but the goal is to grow them on a foil or other material that would produce flexible solar cells or photodetectors.

Cola sees the rectennas built so far as simple proof of principle. He has ideas for how to improve the efficiency by changing the materials, opening the carbon nanotubes to allow multiple conduction channels, and reducing resistance in the structures.

“We think we can reduce the resistance by several orders of magnitude just by improving the fabrication of our device structures,” he said. “Based on what others have done and what the theory is showing us, I believe that these devices could get to greater than 40 percent efficiency.”

Notes:

This work was supported by the Defense Advanced Research Projects Agency (DARPA), the Space and Naval Warfare (SPAWAR) Systems Center, Pacific under YFA grant N66001-09-1-2091, and by the Army Research Office (ARO), through the Young Investigator Program (YIP), under agreement W911NF-13-1-0491. The statements in this release are those of the authors and do not necessarily reflect the official views of DARPA, SPAWAR or ARO. Georgia Tech has filed international patent applications related to this work under PCT/US2013/065918 in the United States (U.S.S.N. 14/434,118), Europe (No. 13847632.0), Japan (No. 2015-538110) and China (No. 201380060639.2)

CITATION: Asha Sharma, Virendra Singh, Thomas L. Bougher and Baratunde A. Cola, “A carbon nanotube optical rectenna,” (Nature Nanotechnology, 2015). http://dx.doi.org/10.1038/nnano.2015.220

Samsung Electronics, a global producer of semiconductor and display solutions, formally opened the doors to its new Device Solutions America headquarters in San Jose, Calif., setting the stage for a new wave of innovation across the digital landscape.

Located on the same corner in San Jose’s tech corridor where Samsung’s original campus was first built more than 30 years ago, the new headquarters symbolizes both Samsung’s long heritage in Silicon Valley and the company’s focus on innovation and growth.

Samsung Electronics’ semiconductor operations’ has long been innovating and with the new America headquarters for its components business, Samsung’s R&D efforts will be bolstered substantially. Innovation and advanced technologies for next-generation devices generated at the new facility will help make a contribution to providing the critical competitive advantage that the company’s U.S. and global customers seek.

Speaking before an audience of more than 800 at the site’s grand opening ceremony, Oh-Hyun Kwon, Vice Chairman and CEO of Samsung Electronics, said “We are transforming Samsung into a world-class example of a truly market-focused technology company.” He further said that the company is “laying the groundwork for a more aggressive pace of growth over the next several decades.”

While Samsung Electronics’ Device Solutions Division has experienced growth since its arrival in Silicon Valley in 1983, it has created multiple organizations dispersed throughout the region. The move brings more than 700 employees together in one location, enhancing efficiency that is crucial in creating technologies and products at the cutting edge of technology. The 1.1-million-square-foot building will house various research labs dedicated to semiconductors, LEDs and displays, as well as staff in sales, marketing and other support areas.

Complete with gardens and open air space within the building, its new design increases collaboration by encouraging more spontaneous encounters between staff, while also bringing nature closer to the workplace to increase employees’ contentment and creativity.

Samsung’s President of its Device Solutions America operations, Jaesoo Han, said, “Today represents a major milestone as we open our most strategically important Samsung facility in the U.S. and also our biggest investment in Silicon Valley.” He went on to say that “Samsung’s goal is nothing less than to develop the best next-generation technologies for device solutions.”

Dignitaries in attendance at the grand opening for Samsung’s new headquarters included the current mayor of San Jose, the Honorable Sam Liccardo; former San Jose mayor, the Honorable Chuck Reed; State Senator Bob Wieckowski; San Jose State University President Susan Martin; and San Francisco Korean Consul General Dongman Han.

In keeping with the company’s corporate social responsibility (CSR) initiatives, Samsung announced a number of contributions to the Silicon Valley community. The company donated $100,000 to the Family Giving Tree and another $100,000 to the Second Harvest Food Bank.

Samsung Electronics has also established a $1 million STEM College Education Scholarship Fund to celebrate its latest expansion. Deserving university students who are currently enrolled in STEM-focused programs at a California State or University of California school will benefit from this program, beginning with a $50,000 gift to San Jose State University this year. Each scholarship will cover tuition and living expenses for one year.