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The first all-optical permanent on-chip memory has been developed by scientists of Karlsruhe Institute of Technology (KIT) and the universities of Münster, Oxford, and Exeter. This is an important step on the way towards optical computers. Phase change materials that change their optical properties depending on the arrangement of the atoms allow for the storage of several bits in a single cell. The researchers present their development in the journal Nature Photonics.

Light determines the future of information and communication technology: With optical elements, computers can work more rapidly and more efficiently. Optical fibers have long since been used for the transmission of data with light. But on a computer, data are still processed and stored electronically. Electronic exchange of data between processors and the memory limits the speed of modern computers. To overcome this so-called von Neumann bottleneck, it is not sufficient to optically connect memory and processor, as the optical signals have to be converted into electric signals again. Scientists, hence, look for methods to carry out calculations and data storage in a purely optical manner.

Scientists of KIT, the University of Münster, Oxford University, and Exeter University have now developed the first all-optical, non-volatile on-chip memory. “Optical bits can be written at frequencies of up to a gigahertz. This allows for extremely quick data storage by our all-photonic memory,” Professor Wolfram Pernice explains. Pernice headed a working group of the KIT Institute of Nanotechnology (INT) and recently moved to the University of Münster. “The memory is compatible not only with conventional optical fiber data transmission, but also with latest processors,” Professor Harish Bhaskaran of Oxford University adds.

The new memory can store data for decades even when the power is removed. Its capacity to store many bits in a single cell of a billionth of a meter in size (multi-level memory) also is highly attractive. Instead of the usual information values of 0 and 1, several states can be stored in an element and even autonomous calculations can be made. This is due to so-called phase change materials, novel materials that change their optical properties depending on the arrangement of the atoms: Within shortest periods of time, they can change between crystalline (regular) and amorphous (irregular) states. For the memory, the scientists used the phase change material Ge2Sb2Te5 (GST). The change from crystalline to amorphous (storing data) and from amorphous to crystalline (erasing data) is initiated by ultrashort light pulses. For reading out the data, weak light pulses are used.

Permanent all-optical on-chip memories might considerably increase future performance of computers and reduce their energy consumption. Together with all-optical connections, they might reduce latencies. Energy-intensive conversion of optical signals into electronic signals and vice versa would no longer be required.

By Girolamo Di Francia, ENEA & EU-PVTP expert, Italy

Introduction

The photovoltaic (PV) sector has now reached a good maturity characterized by a worldwide installed capacity of 180 GWp, increasing at a constant rate of about 35 GWp/yr during the last three years and by an annual turnover of about 45 B$, a trend that also seems confirmed for the current year. More than 85% of all the PV plants are realized by means of PV modules based on crystalline and polycrystalline silicon (cSi solar cell technology), an industrial sector dominated by Chinese companies with a 60% of the market share. In comparison, less than 20% of the photovoltaic modules are produced in the European Union (EU) and the United States (US). Vice versa EU and US are the most relevant markets for photovoltaic products with almost 70% of the installed capacity being located in those areas (EPIA 2013, Eurobarometer 2015).

On the history and the development of such a strongly unbalanced situation, several papers have been published (see for instance: de la Tour, 2011). As a matter of fact, the question is not a minor one. Photovoltaic is indeed an important product segment of the semiconductor industry, accounting, in 2014, for about a 5% of the whole 300 B$ sales of this sector and, by now, rapidly becoming comparable to other more confirmed electronic device markets, such as those related to memories or analog devices. A very intense debate is, therefore, in progress focused on the possible strategies the US and EU should undertake in order to revitalize their photovoltaic industries so that a more suitable equilibrium between China and EU/US production is set. In this respect, it seems natural to try to learn from the historical development of the electronic industry, if similar problems have occurred in that case, and if the solutions they implemented could be transferred to the photovoltaic case.

Table 1. 2014 world leading photovoltaic manufacturers

Company Country Location of production lines
Trina Solar China China
Yingli Green Energy China China
Canadian Solar Canada, China Canada, China
Jinko Solar China China
JA Solar China China
Renesola China Poland, South Africa, India, Malaysia, South Korea, Turkey, Japan
Sharp Corporation Japan Japan, US
Motech Taiwan Taiwan, China, Japan, USA
First Solar US Malaysia, US
Sun Power US US, Philippines

Indeed, a similar situation occurred in the US semiconductor industry in the late 1980s, when it had become evident that the competition with Asian electronic chips manufacturers (memories and analog devices) was going to be lost. Most of the US electronic companies decided then to shift their production from that class of chips to new products (mainly microprocessors), also through the support of national governments initiatives. This change of approach was sustained by a growing demand for the new products that, in turn, supported the creation of a local industry of production equipment specialized for those kinds of applications (Pillai 2014). Product innovation was, therefore, in that situation, the solution to cope with the asian competition, at least temporarily.

Discussion

Whether this approach can be applied to the PV industry, as well, and innovation in solar cell technology be used to revitalize the US and EU photovoltaic industries is, however, a matter of debate. Before that paradigm can be adopted, it is important to understand the extent that the photovoltaic and the electronic sectors are similar and, in this respect, a few issues need to be more deeply discussed.

1. Technological issues

Although the basic material and processing technologies are similar, the actual fabrication processes for a cSi solar cell and an electronic chip are very different, as shown in Table 2. In the case of a solar cell, a single device is obtained out of the processing of a single silicon wafer (true large area devices) while in electronics, thousands of chips are fabricated on a single substrate (high volume production). Of course, device processing resolution requirements are also very different. For a solar cell, the minimum line to be processed is, at most, in the hundreds of microns range, while for a memory chip even less than 20 nm could be required. Both resolution and number of devices to be processed per single wafer change, in turn, the basic Fabrication Yield (FY) requirements for the two devices: for a solar cell, the FY is mainly limited by wafer handling failure, with less concern with the fabrication environment.

Table 2. A comparison of the main features of a solar cell and an electronic device

Photovoltaic Electronic
Basic Fab. Proc. = =
Large Area True large area High volume
Resolution 0.1 mm 20 nm
Reliability 25 yr/80% 5 yr (Memory card)
Operating Conditions -40 °C/+80 °C -10 °C/+50 °C
Fab. Yield Limit. Handling Wafer processing

For an electronic device, particle contamination control is critical, perhaps even more than wafer handling, and highly controlled environments (clean rooms ISO 1 and ISO 2) are mandatory. But it is, perhaps, in terms of device reliability that the two classes of devices mainly differentiate. A solar cell has to continuously work for at least 25 years in an operating temperature range that can change from – 40°C up to + 80°C, and with an end life efficiency that has to not be less than 80% of its starting one. On the contrary, an electronic device, a memory card for instance, is warranted to operate for about five years and in much less stringent operating conditions (-10 °C up to + 50 °C). It is worth noting, in this respect, that for many other electronic devices (mobile phones for instance) the full functionalities are assured for not more than two years.

2. Product innovation issues

In the electronic sector, the capacity a new product has to enter the market is, first of all, connected to its innovative performance, perhaps even more than to its cost. Let us, for instance, consider again the case of memory cards, one of the most reliable devices, as stated above. As shown in Figure 1, in the last 12 years the average product has increased its performance by a factor of 1,000, increasing its capacity from an average of 128 Mb in the year 2003, to today’s 128 GB.

Figure 1. The increase in size for an average memory card and the corresponding decrease of its cost/Mb, 2003-2014.

Figure 1. The increase in size for an average memory card and the corresponding decrease of its cost/Mb, 2003-2014.

Correspondingly, a twofold decrease in the cost/Mb has been observed, although in this same period a more limited decrease in the average product cost is actually observed (McCallum 2015).

On the contrary PV solar modules have experienced in the same period a one fold decrease (from 6 $/Wp to 0.6 $/Wp) in their average cost, but the conversion efficiency, the main technological characteristic fingerprint of the innovation for this sector, has only observed a modest 30% increase (see Figure 2).

Figure 2. The increase of the average cSi solar module conversion efficiency and the decrease of the cost/Wp, 2003-2014.

Figure 2. The increase of the average cSi solar module conversion efficiency and the decrease of the cost/Wp, 2003-2014.

Innovation, therefore, does not seem to have played a key role in the development of the photovoltaic sector and, effectively, it has been reported that the major role in PV cost reduction is due to economies of scale (ISE 2013, Goodrich 2012).

Conclusions

Sic reris stantibus, it is questionable to what extent innovation in the PV sector can effectively support the further diffusion of this form of energy and help the EU and US industries cope with the Chinese competition. Recently, for instance, it has been observed that while a certain level of product innovation can be necessary, excessive innovative technological scenarios could even be detrimental (Goodrich 2012) with respect to a more capillar photovoltaic diffusion.

The point that is important to keep in mind is that the end user of a PV module is an energy producer, and since the fuel (the solar radiation) is available at no cost, once the system used for the conversion is such that the cost of the electricity produced becomes competitive with that of other energy sources, as it is now effectively observed in several countries, the only other issue to be considered is the long-term system reliability. As the solar modules actually on the market have shown in the last 40 years, to fully comply with this requirement, it is difficult to conceive an innovative product capable of revitalizing the US or EU photovoltaic industries that is, at the same time, truly different from that classical, very sound, product. Finally, it is worth noting that it has also been demonstrated that there is no practical economical advantage in setting up a PV industry in China with respect to any other US or EU region (Goodrich 2013). This suggests that revitalizing the US or EU industries could be more a question of further supporting the diffusion of photovoltaic energy than of pushing too hard on the innovative character of the PV productions. In this respect, it is perhaps more urgent to find innovative financial schemes, sustainable from the point of view of public spending, and also capable of supporting the expansion of a sector that has become relevant for EU and US industrial and environmental policies, than to pay too much attention to the innovative characteristics of a product that seems, at present, to fully satisfy most market expectations.

References

de la Tour A., Glachant M., and Ménière Y. 2011. Innovation and international technology transfer: The case of the Chinese photovoltaic industry, Energy Policy 39 (2): 761-770.

EPIA Global market outlook for photovoltaics 2013-2017. Available at: http://www.epia.org/fileadmin/user_upload/Publications/GMO_2013_-_Final_PDF.pdf

Eurobarometer 2015. Barometre photovoltaique Eurobserver Avril 2015. Available at : http://eurobserv-er.info/photovoltaic-barometer-2015/

Goodrich A., Hacke P., Wang Q., Sopori B., Margolis R., James T.L., and Woodhouse M. , (2012) A wafer-based monocrystalline silicon photovoltaics road map: Utilizing known technology improvement opportunities for further reductions in manufacturing costs. Solar Energy Materials & Solar Cells 114: 110–135

Goodrich A., Powell D. M., James T. L., Woodhouse M. and Buonassisi T., (2013) Assessing the drivers of regional trends in solar photovoltaic manufacturing. Energy Environ. Sci., 6 : 2811-2821

ISE-Photovoltaic Report, Photovoltaic Report 2014, Ise Fraunhofer, 2014.

McCallum J.C. 2015 Flash Memory Prices (2003-2014). http://www.jcmit.com/index.htm (last accessed june 2015)

Pillai U., Querques N., and Haldar P. 2014 The U.S. Photovoltaic Manufacturing Consortium: Lessons from the Semiconductor Industry. InterPV.net – Global PhotoVoltaic Business Magazine. Available at: http://www.interpv.net/market/market_print.asp?idx=666&part_code=03

 

 

London, UK and San Jose, California – Dialog Semiconductor and Atmel Corporation announced today that Dialog has agreed to acquire Atmel in a cash and stock transaction for total consideration of approximately $4.6 billion. The acquisition creates a global leader in both Power Management (defined as power management solutions for mobile platforms including smartphones, tablets, portable PCs and wearable-type devices) and Embedded Processing solutions. The transaction results in a company that supports Mobile Power, IoT and Automotive customers. The combined company will address a market opportunity of approximately $20 billion by 2019.

Dialog will complement its position in Power Management ICs with a portfolio of proprietary and ARM (R) based Microcontrollers in addition to high performance ICs for Connectivity, Touch and Security. Dialog will also leverage Atmel’s established sales channels to diversify its customer base. Through realized synergies, the combination could deliver an improved operating model and enable new revenue growth opportunities.

“The rationale for the transaction we are proposing today is clear – and the potential this combination holds is exciting. By bringing together our technologies, world-class talent and broad distribution channels we will create a new, powerful force in the semiconductor space. Our new, enlarged company will be a diversified, high-growth market leader in Mobile Power, IoT and Automotive. We firmly believe that by combining Power Management, Microcontrollers, Connectivity and Security technologies, we will create a strong platform for innovation and growth in the large and attractive market segments we serve. This is an important and proud milestone in the evolution of our Dialog story,” said Jalal Bagherli, Dialog Chief Executive Officer.

“This transaction combines two successful companies and will create significant value for Atmel and Dialog shareholders, customers and employees. Adding Dialog’s world-class capabilities in Power Management with Atmel’s keen focus on Microcontrollers, Connectivity and Security will enable Dialog to more effectively target high-growth applications within the Mobile, IoT and Automotive markets,” said Steven Laub, Atmel President and Chief Executive Officer.

The transaction is expected to close in the first quarter of the 2016 calendar year. In 2017, the first full year following closing, the transaction is expected to be accretive to Dialog’s underlying earnings. Dialog anticipates achieving projected annual cost savings of $150 million within two years. The purchase price implies a total equity value for Atmel of approximately $4.6 billion and a total enterprise value of approximately $4.4 billion after deduction of Atmel’s net cash. Dialog expects to continue to have a strong cash flow generation profile and have the ability to substantially pay down the transaction debt approximately three years after closing.

The transaction has been unanimously approved by the boards of directors of both companies and is subject to regulatory approvals in various jurisdictions and customary closing conditions, as well as the approval of Dialog and Atmel shareholders. Jalal Bagherli will continue to be the Chief Executive Officer and Executive Board Director of Dialog. Two members of Atmel’s existing Board will join Dialog’s Board following closing. The transaction is not subject to a financing condition.

Process Watch: Risky business


September 18, 2015

By Douglas G. Sutherland and David W. Price

Authors’ Note: This is the ninth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications. Within this paper we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Previous installments have discussed many aspects of process control from general concepts to specific issues related to risk management (see below for links to previous Process Watch articles). In this article we will focus on strategies for managing risk associated with the most difficult steps in the process.

The ninth fundamental truth of process control for the semiconductor IC industry is:

High-Stakes Problems Require a Layered Process Control Strategy

In the IC manufacturing process there are a bewildering number of things that can go wrong and there is a tremendous amount of money at risk. As the margins of error steadily decrease with each new design node, the number of parameters that can wreak havoc on the process continues to rise. The increasing complexity of multiple patterning, pitch splitting and other advanced patterning techniques does nothing to mitigate this problem.

This increased process complexity drives the need for new process control strategies. For example, higher order overlay corrections that were largely unheard of above 45nm are now considered mandatory at 2Xnm and below. Similarly, wafer topography, something that historically was only measured during the manufacture of bare wafers, is now becoming a requirement in IC fabs to accommodate the shallower depth of focus in today’s scanners. For the same reasons, wafer backside and edge inspection are also becoming common practices. The difficulty of some process steps necessitates that they have more than just a single line of defense.

Figure 1 below shows the severity of a potential problem increasing in the horizontal direction and the probability of that problem actually occurring increasing in the vertical direction. In this figure the term “risk” can be thought of as the product of these two attributes – the amount of material impacted (severity) multiplied by the probability of it happening. The severity could increase for a number of reasons: the next inspection point could be many steps downstream from the current step, the process tools at the current step may have very high throughput so that by the time the problem is identified many lots have been exposed to it, or both.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Figure 1. Risk exposure chart with higher severity to the right and higher probability to the top. The problems that require a layered approach to risk management are those in the upper right hand corner where the probability of having a problem is high and the amount of material exposed to that problem is large.

Clearly the safest place to operate is in the lower left corner where both probability and severity are low. However, for process steps that are inherently closer to the upper right hand corner of the chart—high probability and high severity—it often makes sense to have a layered approach to process control in which there is a well thought out back-up plan if the problem is not immediately identified with the first inspection step. Sometimes there are aspects of the problem that are easier to detect later in the process than immediately after the problem step.

Consider the case of forming the first metal layer that wires together the individual transistors. This can be particularly difficult for a number of reasons. The CDs and pitches are aggressive—often at design rules similar to the gate layer. Also, the opportunity for built-in redundancy (multiple vias) is low because there is only one point of contact for each of the transistor connections (source, drain and gate), so every connection has to work.

In such a case it makes sense to have multiple layers of protection, each of which has unique capabilities. For instance, you might perform macro inspection after the photo step to discover any gross defects in the lithography process. There should also be inspection steps after oxide etch, barrier deposition and copper CMP. Having multiple inspection steps ensures the quality of the process throughout the formation of this layer and also helps ensure that you catch problems that originate at one step but may not become apparent until later in the process.

Simply waiting to do a final inspection at copper CMP is usually not sufficient. Doing so will pick up problems in the CMP process but may not allow for distinguishing these from issues that may have originated at an earlier step. Only by inspecting the same wafer at multiple steps are you able to subtract out previous-layer defects and isolate the problem.

Having multiple inspection points has several benefits. It helps identify problems early in the process flow, which significantly reduces the amount of material exposed. A device with 50,000 wafer starts per month has about 1,600 wafer starts per day. Identifying a problem one day sooner can save millions of dollars (depending on the yield loss and wafer cost). Multiple inspection points also help diagnose where the problem occurred and expedite the recovery procedure. Over time, they provide more information about the process allowing for continuous improvement plans that can help reduce not only the severity but also the frequency of problems.

Previous Process Watches:

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

By Zvi Or-Bach, Contributor

The upcoming IEEE S3S Conference 2015 in Sonoma, CA, on October 5-8, will focus on key technologies for the IoT era. It is now accepted that the needs for the emerging IoT market are different from those that drive the high-volume PC and smart-phone market. The Gartner slide below illustrates this industry bifurcation where traditional mass products follow the ever more expensive scaling curve, while IoT devices, with their focus on cost, power, flexibility and accessibility, will seek a place near its minimum.

S3S_Gartner

The current high-volume market is focused on a few foundries and SoC vendors driving a handful of designs at extremely high development cost each, processed at the most advanced nodes, with minimal processing options. In contrast, the emerging IoT market is looking for older nodes with lower development costs and a broad range of process options, and has many more players both at the foundry side and the design side.

The key enabling technologies for the IoT market are extremely low power as enabled by SOI and sub-threshold design, integrated with multiple sensor and communication technologies that are both enabled by 3D integration. All of these combine in forming the IEEE S3S unified conference.

This year’s conference includes many exciting papers and invited talks. It starts with three plenary talks:

  • Gary Patton – CTO of Global Foundries: New Game Changing Product Applications Enabled by SOI
  • Geoffrey Yeap – VP at Qualcomm.: The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology
  • Tsu-Jae King Liu – Chair of EE Division, Berkeley University: Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration

The following forecast from BI Intelligence suggest that the semiconductor technologies that are a good fit for the future market of IoT should be of prime interest for the semiconductors professional.

S3S_BI

Jim Walker, Research VP at Gartner, argued at the “Foundry vs. SATS: The Battle for 3D Wafer Level Supremacy” market symposium that 3D ICs are the key enabler of performance and small form factor of products required for IoT.

The upcoming IEEE S3S conference provides an important opportunity to catch up and learn about these technologies.

Let me share with you some nuggets from the monolithic 3D integration part of the conference:

Prof. Joachin Burghartz of the Institute for Microelectronics Stuttgart will deliver an invited talk on “Ultra‐thin Chips for Flexible Electronics and 3D ICs” which will present a process technology to fabricate flexible devices 6-20 microns thin. This process flow is currently in manufacturing in their Stuttgart fab, as depicted below:

S3S_Fig3

Another interesting discussion will be presented by NASA scientist Dr. Jin-Woo Han who will describe “Vacuum as New Element of Transistor”. These transistors are made of “nothing” and could be constructed within the metal stack, forming monolithic 3D integration with silicon-based fabric underneath.

In his invited talk “Emerging 3DVLSI: Opportunities and Challenges” Dr. Yang Du will share  Qualcomm’s views on monolithic 3D IC, which they term 3DVLSI and illustrate below, which seems very fitting for IoT applications.

S3S_Fig2

Globalfoundries will present joint work with Georgia Tech on “Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”. This work again shows that monolithic 3D can provide a compelling alternative to dimensional scaling as illustrated by the following chart.

S3S_Fig4

Monolithic 3D will present “Modified ELTRAN (R) – A Game Changer for Monolithic 3D” that shows a practical flow for existing fabs to process monolithic 3D devices using their exiting transistor process and equipment. This flow leverages the work done by Canon about 20 years back called ELTRAN, for Epitaxial Layer Transfer. The following slide illustrates the original ELTRAN flow.

S3S_Final

By deploying the elements of this proven process, a multilayer device could be built first by processing a multilayer transistors fabric at the front end of line, and then process the metal stacks from both top and bottom sides.

The conference includes many more interesting invited talks and papers covering the full spectrum of IoT enabling technologies. In addition, the conference offers short courses on SOI application and monolithic 3D integration, and a fundamental class on low voltage logic.

New technologies are an important part of the future of semiconductor industry, and a conference like the S3S would be a golden opportunity to step away for a moment from the silicon valley, and learn about non-silicon and silicon options that promise to shape the future.

To advance research in nanoscale science, engineering and technology, the National Science Foundation (NSF) will provide a total of $81 million over five years to support 16 sites and a coordinating office as part of a new National Nanotechnology Coordinated Infrastructure (NNCI).

The NNCI sites will provide researchers from academia, government, and companies large and small with access to university user facilities with leading-edge fabrication and characterization tools, instrumentation, and expertise within all disciplines of nanoscale science, engineering and technology.

The NNCI framework builds on the National Nanotechnology Infrastructure Network (NNIN), which enabled major discoveries, innovations, and contributions to education and commerce for more than 10 years.

“NSF’s long-standing investments in nanotechnology infrastructure have helped the research community to make great progress by making research facilities available,” said Pramod Khargonekar, assistant director for engineering. “NNCI will serve as a nationwide backbone for nanoscale research, which will lead to continuing innovations and economic and societal benefits.”

The awards are up to five years and range from $500,000 to $1.6 million each per year. Nine of the sites have at least one regional partner institution. These 16 sites are located in 15 states and involve 27 universities across the nation.

Through a fiscal year 2016 competition, one of the newly awarded sites will be chosen to coordinate the facilities. This coordinating office will enhance the sites’ impact as a national nanotechnology infrastructure and establish a web portal to link the individual facilities’ websites to provide a unified entry point to the user community of overall capabilities, tools and instrumentation. The office will also help to coordinate and disseminate best practices for national-level education and outreach programs across sites.

Funding for the NNCI program is provided by all NSF directorates and the Office of International Science and Engineering.

OMRON Corporation, which is in the field of automation based on its core sensing and control technology, and Adept Technology, Inc., a provider of intelligent robots, autonomous mobile robot solutions and services, today announced that the two companies have entered into an agreement whereby OMRON will acquire Adept.

OMRON plans to acquire 100% of the outstanding shares of Adept common stock through an all-cash tender offer followed by a second-step merger. OMRON will offer Adept investors $13.00 per share of Adept common stock, which represents a 63% premium over the closing price for Adept’s common stock on September 15, 2015. This values Adept at approximately $200 million. OMRON will fund the tender offer through cash on hand.

The tender offer is expected to commence on or about September 23, 2015, and the transaction is expected to close on or about October 23, 2015. The closing of the transaction is subject to customary closing conditions, including at least a majority of shares of Adept common stock being tendered in the offer, expiration of the applicable waiting period under the Hart-Scott-Rodino Antitrust Improvements Act of 1976 and receipt of required foreign antitrust approvals. The transaction has been unanimously approved by the Boards of Directors of both companies.

Commenting on the acquisition, Yutaka Miyanaga, OMRON Industrial Automation Business Company President, said, “We are delighted Adept Technology, a world leader in robotics, has agreed to join OMRON. This acquisition is part of our strategy to enhance our automation technology and position us for long term growth. Robotics will elevate our offering of advanced automation.”

Rob Cain, President and Chief Executive Officer of Adept, added, “We are excited about the opportunity to join OMRON, a global leader in automation. Together, our products will offer new innovative solutions to customers all around the globe.”

Following the transaction, Rob Cain will continue to lead Adept and will report to Nigel Blakeway, Chairman, Chief Executive Officer and President of Omron Management Center of America, Inc., OMRON’s wholly owned United States subsidiary.

As global manufacturing comes under even more pressure to cut costs, shorten supply cycles and operate across global environments, production sites around the world strive to improve productivity. Increased use of labor-saving robots is one of the solutions. By adding the robotics technology of Adept to its current offering, OMRON will be positioned to provide manufacturers in the automotive, digital device, food and beverage, packaging, and other industries with solutions to these challenges, as well as engineering support.

Founded in 1983, Adept is listed on NASDAQ under the ticker symbol ADEP. The company recorded annual sales of $54.2 million and gross margin of 42.0% in the fiscal year ended June 30, 2015. The company is a U.S. based manufacturer of industrial robots. Adept’s product lines include autonomous mobile robots, industrial robots, configurable linear modules, machine controllers for robot mechanisms and other flexible automation equipment, as well as machine vision systems and software. Adept’s strategy is to provide a broad range of highly reliable integrated products along with world-class service to allow manufacturers to maximize productivity, safety, flexibility and product quality. This acquisition is a part of the acceleration of OMRON’s “ILO+S” (Input, Logic, Output and Safety) strategy for its Industrial Automation Business, which provides automation solutions for the manufacturing industries.

Soitec (Euronext), which generates and manufactures semiconductor materials for the electronics and energy industries, and Shanghai Simgui Technology Co., Ltd. (Simgui), a Chinese silicon-based semiconductor materials company, jointly announced today that the first 200-mm silicon-on-insulator (SOI) wafers have been produced at Simgui’s manufacturing facility in Shanghai using Soitec’s proprietary Smart Cut (TM) technology, and will be shipped within the next weeks for customers’ qualification. This major milestone in the companies’ licensing and technology transfer agreement, signed in May 2014, demonstrates that the process has been successfully implemented at Simgui and that the technology transfer is proceeding as planned to produce Soitec’s SOI products in order to increase SOI wafer capacity to serve the growing RF and power markets.

“We are very pleased to have reached this major milestone with Simgui, which now has the capability to manufacture Soitec’s SOI products using our Smart Cut technology. This represents a key step in our commitment to increase capacity in response to the needs of our customers who serve the fast-growing RF and power markets, both in China and worldwide,” said Paul Boudre, CEO and chairman of the board of Soitec.

“China is a hot spot for the IC industry today. The fast growth of China’s mobile devices demands a large number of SOI wafers. Through the collaboration with Soitec, Simgui has successfully demonstrated a strong technical ability and expanded capacity to meet our customers’ needs. In addition to the planned high-volume manufacturing of SOI wafers, we will continue to promote the SOI ecosystem in China and build a globally influential Chinese silicon industry,” said Dr. Xi Wang, chairman of the board of directors of Simgui.

The two companies formed their international partnership last year to address both China’s growing demand and to increase worldwide production capacity for 200-mm SOI wafers used in fabricating semiconductors for RF and power applications. When completed, the partners’ first wafer production line in China will boost the industrial manufacturing capacity of SOI wafers to meet increasing worldwide usage and will also be a key element in establishing an SOI ecosystem in China.

Simgui is a high-technology company in Shanghai focused on supplying SOI wafers and providing foundry services for epitaxial (epi) wafers used in key sectors of the semiconductor industry. Soitec designs and manufactures high-performance semiconductor materials.

Until now, transparent electrode materials for OLEDs have mainly consisted of indium tin oxide (ITO), which is expected to become economically challenging for the industry due to the shrinking abundance of indium. Therefore, scientists are intensively looking for alternatives. One promising candidate is graphene, whose application fields are more closely investigated in the project GLADIATOR (“Graphene Layers: Production, Characterization and Integration”).

The project GLADIATOR, which is funded by the European Commission, has reached its midterm and has already achieved some successes. The aim of the project is the cost-effective production of high quality graphene at large area, which can then be used for numerous electrode applications. The usability of such applications will be demonstrated at the Fraunhofer FEP by integrating this graphene in OLEDs.

With graphene as an electrode, the researchers at the Fraunhofer FEP hope for flexible devices with higher stability. Beatrice Beyer, project coordinator, says: “Graphene is a very interesting material with many possibilities. Because of its opto-electrical properties and its excellent mechanical stability, we expect that the reliability of flexible electronics will be improved many times over.”

Graphene is a rediscovered modification of carbon with two-dimensional structure, which has gained enormously in popularity since its successful isolation in 2004. Such so-called “monolayer” graphene is synthesized on a metal catalyst via a chemical vapor deposition (CVD) process and transferred by a further process step to a target substrate, such as thin glass or plastic film. Here, it is very important that no defects are added which might reduce the quality of the electrode. In order to compete with the reference material ITO, the transparency and conductivity of graphene must be very high. Therefore, not only is the process of electrode manufacturing being optimized, but also different ways of doping graphene to improve its properties are being examined.

At the same time, the developed process steps must be easily scalable for later industrial use. These many challenges are faced by a project consortium consisting of 16 partners from six EU member states and Switzerland.

The Fraunhofer FEP is coordinating the GLADIATOR project and acts as an end-user of the graphene electrode. Scientists examine the integration of graphene and compare it to the reference material ITO. The sophisticated material properties of graphene must be maintained during the integration in organic devices. To this end, several methods for cleaning and structuring the graphene must be modified. In addition, the processes for different target substrates such as glass or flexible foil must be adapted and optimized. The first hurdles have been overcome thanks to a close cooperation between the consortium partners and the first defect-free OLEDs on transparent graphene electrodes have been realized on small areas. The target of the next one and a half years is to successfully illuminate large area OLEDs.

The GLADIATOR project will run until April 2017. By this time several types of OLED will have been made using graphene electrodes: a white OLED with an area of about 42 cm2 to demonstrate the high conductivity, and a fully-flexible, transparent OLED with an area of 3 cm2 to confirm the mechanical reliability.

Marking an industry first for emerging electronics devices, Semiconductor Research Corporation (SRC) today announced a significant expansion of its benchmarking research — a unique program that evaluates the relative capabilities of new and emerging computing devices.

SRC, the world’s leading university-research consortium for semiconductor technologies, is managing the initiative through its Nanoelectronics Research Initiative (SRC-NRI) and STARnet Research programs. The research will be led by the Georgia Institute of Technology’s Azad Naeemi, associate professor, Georgia Tech School of Electrical and Computer Engineering.

“Benchmarking guides university research funded through SRC — enabling concise communication of research outcomes, focusing researchers’ attention on key technical challenges and sparking invention,” said Tom Theis, executive director of SRC-NRI. “Professor Naeemi’s research is expected to take benchmarking of emerging devices to a new level of sophistication.”

Evaluating the performance of devices in representative “benchmark” circuits is a well-established engineering practice in the semiconductor industry. However, this new program is the first to develop a comparable methodology for evaluating the relative capabilities of emerging devices.

These emerging devices include, for example, transistor-like “steep slope” devices that can operate at very low voltage and, therefore, very low power, and non-volatile magnetic devices that combine the functions of logic and memory. The new devices operate by a variety of principles fundamentally different from those governing the operation of established silicon field-effect transistor technology.

In recent years, benchmarking of these devices has steadily increased in rigor. The Georgia Tech team — selected by a group of SRC member companies supporting the initiative including IBM, Intel Corporation, Micron Technology and Texas Instruments — will build on this foundation.

“This research will also enable selection of the most promising emerging devices for technology transfer to SRC member companies and for continued development in future SRC research programs,” said Gilroy Vandentop, executive director of STARnet Research.

Besides maintaining and improving the established benchmarking methodology, the Georgia Tech team is tasked with developing and evaluating benchmark circuits to better understand the potential of new devices for memory arrays, to explore and quantify the value of non-volatility and to measure the impact of various ways of implementing device-to-device connections. Perhaps most challenging, Prof. Naeemi will lead the development of a rigorous benchmarking methodology for non-Boolean (analog) computational circuits being explored for future applications such as artificial neural networks.

“Our team is chartered with maintaining and improving the established benchmarking methodology for emerging devices, evaluating the potential performance of the various SRC-NRI and STARnet devices in the established benchmark circuits,” said Naeemi. “We will incorporate additional device concepts as they emerge through ongoing research, and we will develop additional benchmark circuits to better understand the capabilities of these devices.”

The SRC benchmark program is a two-and-a-half year effort that funds research from July 1, 2015 through the close of 2017.