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In 2020, flexible barrier manufacturing for flexible electronic devices such as displays will be a market worth more than US$184 million, according to IDTechEx Research. That equates to 3.8 million square meters of flexible barrier films for electronics.

Although multilayer approaches – usually organic and inorganic layers – have been the most popular solution for flexible encapsulation so far, there is significant development work with solutions based on single layer approaches such as flexible glass or atomic layer deposition (ALD) which could, in later years, capture part of the market. The table below, compiled by IDTechEx analysts shows some of the characteristics of flexible glass and ALD films as developers are looking to bring them to market.

Table 1. ALD and flexible glass metrics and commercialization status for Beneq, Lotus and Corning

Company Name  WVTR (gr/sq.m./day Deposition Technique Material Commercialization Status – Strategy
Beneq Can reach
10-6 		 Batch ALD. Also developing roll 2 Roll ALD. Proprietary Aluminium Oxide/Titanium Oxide nanolaminate Beneq supplies coating equipment
Lotus Can reach
10-6 		 Roll 2 Roll ALD Proprietary homogeneous mixture” of Aluminium Oxide/Titanium Oxide layers Lotus follows a licensing business model and is patenting Plasma Enabled Oxygen Radical Decomposition process so as to enable faster deposition rates
Corning Perfect sealing from water vapour/oxygen Down drawing Thin glass (less than 100 μm) Available in rolls and sheets, in sample volumes

Source: IDTechEx report “Barrier Layers for Flexible Electronics 2015-2025” www.IDTechEx.com/barrier

Flexible glass: current status, outlook and challenges

Flexible glass is a significant technical achievement, yet IDTechEx Research believes that it will not be the solution of choice for encapsulation of flexible electronics in the short to medium term, for multiple reasons.

In spite of the marketing spin given by the manufacturers, glass is inherently a fragile material and requires specialized handling and processing. While plastic materials can also be damaged, there is an important difference between the two: damage of barriers on plastic can lead to the failure of a specific part, however, shattering of glass, even if protective sheets are used, leads to particle contamination on the defect line able to affect multiple parts.

Inherent fragility of flexible glass makes sheet edges critical. All suppliers propose protective tabs to reduce the problem. However, any other particle on the processing equipment could also become a focal point of stress and lead to shattering of the glass sheet or web.

A strong point of traditional glass encapsulation (especially for top emission devices) has been its ability to form truly hermetic packaging by using glass frit and laser sealing. This advantage may not be transferable to flexible glass where glass-to-glass sealing may be very problematic and difficult because points of stress and relative twisting of the two sheets must be avoided in the laser firing of the frit. It may be that flexible glass has to be used in combination with adhesives (and desiccants).

Flexibility is another issue. Although glass is very flexible if flexed along a well-defined axis, it can be poor at tolerating any stress out of axis, so much so that twisting the sheet may lead to fracture. This is true with or without protective film applied to the glass. Extreme flexibility (r< 2-3 mm) may also be a problem. Data that has been shown would put the flexibility limit around r= 2.5 cm. Consequently, flexible glass as an encapsulant superstrate or substrate may be good for conformal applications, but for truly flexible applications there seem to be several challenges to be overcome.

Flexible glass makers are also waiting for equipment providers to make appropriate equipment to handle the flexible glass in manufacturing, another bottle neck.

Future opportunities for flexible glass

The thermal stability of flexible glass makes it the best choice as substrate for back-planes of high-resolution high-end large displays. Glass enables improved resolution and good registration between layers during processing compared to plastic substrates like PET, PEN, and PI. However, IDTechEx analysts and other affiliate experts have only seen results with metal oxide backplanes only so far (Tprocess < 350 C), none with LTPS backplanes (Tprocess < 450 C). If processability up to 450C is indeed possible, flexible glass would be a very good choice as a substrate for flexible AMOLED TV. Those devices are bottom emission (BE) AMOLED, normally have a metal foil as back encapsulant, a higher cost tolerance. Regarding R2R processing of flexible glass, it has demonstrated possible. Manufacturing by R2R will require specialized tools not differently than fabrication of barrier in R2R.

The multi-layer approach if correctly implemented on dedicated tools may have the potential to be low cost but an open question remains as to how low the defect density of barrier on foil can be. Consequently, it is an open question what the maximum size of displays that can be encapsulated with compatible yield can be. As it transpires from the discussion above, plastic engineered superstrate (=encapsulant foil) may be better for smaller devices (wearable, phone, tablets), while flexible glass may be better for TVs and in general larger displays.

Additionally, the smoothness of plastic films, even with smoothing layers, is not as good as glass (0.2 nm). This may be a problem for organic TFT backplanes. Finally optical transmission below 400nm require glass as substrate since PET and PEN have a cut off around 400 nm (PEN). IDTechEx does not see this as a critical limitation for general display applications (it may be for OPV).

Atomic layer deposition (ALD) present and future outlook/market share 

ALD is another flexible encapsulation technology receiving a lot of attention with several players currently developing solutions based on it. It seems like it is not a short-term solution, if it will ever be one as a stand-alone layer but ALD may be a solution in a multi-layer stack in combination with a sputtered or PECVD layer if it would be possible to find a good cost structure. Regarding the intrinsic properties of the material, ALD film deposited at low temperature (T<80 C) have a superior quality when tested at room temperature. A single ALD layer less-than 50 nm thick can perform better than thicker layers deposited by sputtering or PECVD.

However, the inherent stability of the films at higher temperature/humidity (e.g. 85C/85%RH) is a problem. If PE-CVD is used, ALD film stability improves, as well as for mixed oxides, but it is still an issue. A second problem comes with particles and substrates non-uniformity. Any defect may lead at an initial non-uniform nucleation that propagates into the growing film. Furthermore, loose particles on substrates may be partially covered, but because of the extreme thinness, the thin film does not have the mechanical strength to keep them in place under mechanical stress. Any mechanical stress leads to film fracture with consequent creation of an ingress path for moisture. That is why multilayer structures are necessary.

Deposition tools are in development from Lotus, Beneq, Encapsulix and others. Exploration at Samsung SDC with ALD films for TFE was very much advertised by Synos, but resulted in failure and any further evaluation was halted. ALD for barrier on foil has better results although there are doubts and hurdles in scaling up and reaching the deposition speed required for a cost effective process.

This is also one of the sessions at the Printed Electronics USA event, to be held on November 18-19 at Santa Clara, CA. See www.PrintedElectronicsUSA.com for full details.

Startups and small electronics companies spent $78.3 billion on semiconductors in 2014, representing 23 percent of the total market, compelling semiconductor companies to revisit their sales strategy to focus on the large number of smaller organizations than relying on big deals from large customers, research firm Gartner said.

Gartner estimates that there are more than 165,000 companies that buy semiconductor chips around the world: The top 10 spend nearly 40 percent of the total semiconductor revenue; the top 11 to 100 spend about 30 percent; and the remainder spend 30 percent.

Despite the top 10 accounting for such a large percentage of the market, some of the largest customers have decreased orders in the past five years, challenging the semiconductor vendors that mainly supplied to them.

While Samsung and Apple have significantly increased orders in the same period due to success in the smartphone market, semiconductor vendors are concerned about the risk of relying on large customers such as these.

“The industry has seen some fairly significant disruption in recent years, which has highlighted the risks associated with semiconductor vendors putting all of their focus on a limited number of large customers, when small companies offer highly profitable and stable growth,” said Masatsune Yamaji, Principal Research Analyst at Gartner. “To overcome the risk, some semiconductor vendors have tried to increase their business with small customers, while others are also realizing that they should adjust their strategies to do this.”

China is the fastest-growing among the major small-customer regions, with spending by these organizations on semiconductors growing from US$7.5 billion in 2007 to US$14.9 billion in 2014; growth in the smartphone and media tablet markets has been strong. In the Americas, EMEA and Japan, revenue from each customer is small, but the total market size of small customers is big due to the large number of such customers.

Gartner maintains that the number of customers will significantly increase after 2017, due to future growth of the electronics market and the increase in the number of Internet of Things solutions. It is anticipated that the maker movement, which creates and markets products that are recreated and assembled using unused, discarded or broken products from computer-related devices, will drive the foundation of startups and growth of small customers.

According to Gartner, big deals are not confined to large organizations, with many successful vendors having success in the small-customer market by leveraging distributors. Limited sales resources can be compensated for by aligning with good sales partners. Strong adherence to direct sales restricts the opportunities with small customers, especially among general-purpose semiconductor vendors. In fact, semiconductor distributors earn a large part of their revenue from general-purpose semiconductors.

“Semiconductor vendors should focus more on the high-tier customers and outsource sales activities with small customers to distributors,” said Yamaji. “Distributors can bring various products to market at the same time, so this outsourcing will reduce the load, not just for semiconductor vendors, but also for customers. Some distributors offer end-of-life product delivery services, so vendors should partner with these distributors to help small customers avoid having to order excessive loads.”

Gartner recommends that vendors need to evaluate how much revenue can be expected, compared with the large customers. The importance of the small customers for each vendor differs by its product type and its target sales region, so vendors need to have their own unique goals in the small-customer market.

“Before jumping in, semiconductor vendors also need to be aware of the risks associated with the small-company market, which is prone to shrinking when the macro economy weakens,” said Yamaji. “Revenue can also shrink even faster than large customers in many cases, so it is important to be aware of risk levels regarding any revenue decline. Vendors can reduce the risks by diversifying their customer base, which can spread the liability to allow for lost orders.”

North America-based manufacturers of semiconductor equipment posted $1.59 billion in orders worldwide in July 2015 (three-month average basis) and a book-to-bill ratio of 1.02, according to the July EMDS Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.02 means that $102 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in July 2015 was $1.59 billion. The bookings figure is 5.1 percent higher than the final June 2015 level of $1.52 billion, and is 12.5 percent higher than the July 2014 order level of $1.42 billion.

The three-month average of worldwide billings in July 2015 was $1.56 billion. The billings figure is 0.3 percent higher than the final June 2015 level of $1.55 billion, and is 18.2 percent higher than the July 2014 billings level of $1.32 billion.

“Year-to-date, the bookings and billings reported in the SEMI North American equipment book-to-bill report indicate a solid year for the industry,” said SEMI president and CEO Denny McGuirk. “The outlook for the remainder of the year is somewhat clouded, but we see investments in 3D NAND and advanced packaging as drivers.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
February 2015 

$1,280.1

$1,313.7

1.03
March 2015 

$1,265.6

$1,392.7

1.10
April 2015 

$1,515.3

$1,573.7

1.04
May 2015 

$1,557.3

$1,546.2

0.99
June 2015 (final)

$1,554.9

$1,517.4

0.98
July 2015 (prelim)

$1,559.3

$1,594.3

1.02

Source: SEMI (www.semi.org), August 2015

Microcontrollers are in the middle of an incredible wave of unit growth, but unprecedented price erosion is keeping a lid on the increase of revenues, according to IC Insights’ Mid-Year Update to its 2015 McClean Report on the integrated circuit industry.  The mid-year forecast shows microcontroller shipments rising 33 percent in 2015 to 25.4 billion MCUs worldwide as a result of a tremendous upsurge in units for smartcards and 32-bit applications—many of which are aimed at the Internet of Things (IoT) market.

Despite the blistering pace of unit growth, dollar-volume sales of MCUs are now expected to rise by just 4 percent in 2015, reaching a new record high of $16.6 billion from about $15.9 billion in 2014, when total MCU revenues also increased 4 percent.  As seen in Figure 1, average selling prices for microcontrollers are expected to continue plunging with ASPs nose-diving 21 percent in 2015 to $0.65 compared to $0.83 in 2014, when the ASP for MCUs fell 12 percent.  IC Insights’ Mid-Year Update forecasts a 14 percent drop in MCU ASPs in 2016 with microcontroller revenue growing 7 percent to $17.7 billion and unit shipments climbing 25 percent to 31.6 billion worldwide.

Starting in 2014, microcontroller unit growth accelerated, driven by rocketing shipments of low-cost MCUs used in smartcards for protection in electronic banking and credit-card transactions, mass-transit fares, government IDs (such as electronic passports), medical records, and security applications.  After a 26 percent increase in 2014, smartcard MCU shipments are now expected to surge by 41 percent in 2015 to 12.9 billion units worldwide, followed by 25 percent growth in 2016 to 16.1 billion.

The mid-year forecast significantly raises the projection for smartcard MCU shipments through 2019 as U.S. credit card companies, banks, retailers, government agencies, and other industry sectors begin to broadly adopt secure “chip-card” technology, much like Europe and other country markets have done since the 1990s. In the U.S., massive data breaches in credit card transactions at retail stores and growing concerns about identity theft have finally resulted a major move to smartcards for higher levels of security, anti-fraud encryption, and greater protection of lost or stolen debit and credit cards.

mcu unit shipments

While price erosion weighs on total MCU sales growth, total microcontroller shipments are also accelerating because of strong demand for 32-bit designs and other single-chip solutions that can serve the explosion of sensors in wireless systems and connection to the Internet of Things. IoT-related MCU sales are forecast to grow 16 percent in 2015 to $405 million with unit shipments climbing 40 percent to 431 million.

The global market for semiconductors used in smart meters that provide two-way communications between meters and utilities will continue to expand in the coming years, providing significant growth opportunities semiconductor manufacturers. Shipments of communicating meters are forecast to reach 132 million units in 2015 and 150 million units in 2019, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight.

Global revenues for semiconductors used in water, gas and electric meters reached $1.2 billion in 2014, with a year-over-year growth of 11 percent and a five-year compound annual growth rate of 8 percent. The average semiconductor cost in two-way meters was approximately $11 in 2014. Average selling prices (ASPs) are expected to increase over time, as industry needs increase for 32-bit micro-controller units (MCUs), memory chips, single system-on-chip (SoC) solutions and other components used in secured communications and other applications.

Based on the latest information from the IHS Industrial Semiconductor Market Tracker, the demand for precise energy measurement and communication has increased the penetration of micro-component integrated circuits (ICs), along with analog ICs. In fact, two thirds of meter semiconductor revenue comes from microcontroller and analog components.

“The semiconductor industry for electric meters is moving toward a single-chip solution for measuring and communicating with the grid station, which is an important industry trend to watch,” said Robbie Galoso, associate director, semiconductor market shares and industrial electronics for IHS Technology. “Water and gas meters require fewer semiconductor components; however, they need extra semiconductors for sensing and battery management.”

Meters installed in the latter half of this decade will require greater application complexity, better security, improved communication ability, enhanced remote control ability and higher resolution. That means increased need for memory and system-on-chip (SoC) solutions with greater capabilities in a smaller package than in the past.

Meters are evolving from those that merely register end-user usage, into complicated machines that can be queried for on-demand data, upgraded remotely, shut off in case of emergency or non-payment and used for variable pricing. “The movement from 8-bit MCUs to higher margin 32-bit MCUs is a key industry trend,” said Noman Akhtar, analyst for IHS Technology. “The integration of these higher function microcontroller units also requires additional capabilities, such as increased memory, which further increases manufacturing costs.”

Smart_Semis_Chart

By Jeongdong Choe, PhD., TechInsights

A few years ago, some of the semiconductor process and device analysts thought 2D planar NAND Flash would soon be coming to an end due to the scaling limits, especially around the 20nm or sub-20nm generation. Do we still think the 2D NAND Flash technologies have hit the scaling wall? According to TechInsights’ deep-dive analysis on current and future NAND Flash technologies, although 3D V-NAND architecture could help with the scaling limit, we believe the 2D MLC and TLC NAND Flash technologies remain strong and cost effective for 14nm, 12nm and even for single-digit nanometer node.

When it comes to 3D NAND technology, Samsung has been developing and mass-producing 32-tier V-NAND architecture (for technical analysis related to the Samsung 3D V-NAND click here) with MLC and TLC for their 850 PRO and 850 EVO since 2014, although, this is not the final goal for Samsung due to a relatively low yield, process complexity and bit-cost viewpoints. More 3D Flash products may appear at the end of this year, or early in 2016, as major NAND players such as Toshiba, SanDisk, Micron, Intel, and SK-Hynix bring out their 3D products with 24-tier, 32-tier or 48-tier FG (floating gate)/CTF (charge-trap-flash) architecture (Figure 1).

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

However, the ultimate target for 3D NAND is 128-tier or at least 64-tier structure from the bit-cost viewpoints. In that case, the aspect ratio of Si-channel and common source contacts would be over 80:1, which is a strong burden for process integration engineers. In addition, the uniformity of the 64-tier or 128-tier NAND cell characteristics in a NAND string and their endurance/retention/reliability properties during program/erase operation would be another big challenge for the vertical NAND string architecture.

The scaling limits for 10 nm-class and sub-10 nm 2D planar NAND structures include patterning technology including QPT (Quadruple Patterning Technology), cell-to-cell interference such as cross-talk, poly-Si gap-filling process for control gate (CG), self-aligned STI (SA-STI) for isolation patterning, self-aligned process (SAP) for CG/FG, interconnection methodology including pad layout/design, inter-poly dielectric (IPD) layer engineering, and cell transistor channel/source-drain (S/D) engineering. According to TechInsights’ detailed structural analysis and comparison of 15nm and 16nm NAND flash devices (so called 1Y NAND technology node) such as Samsung 16nm, Toshiba 15nm, Micron 16nm and SK-Hynix 16nm products, we may expect that at least two more next generation 2D planar NAND products having 12nm and less than 12 nm technology would be developed and released from major players near future. As for NAND memory density and die size, Toshiba/SanDisk 15nm TLC products have 1.28 Gb/mm2 which is double from other MLC products although Samsung 32-tier 3D V-NAND TLC products have 1.87 Gb/mm2 (Figure 2).

Fig 2

Figure 2. Comparison of NAND memory density for each product (Source: TechInsights)

For patterning the three finest lines of the NAND cell structure such as active/STI, gate/wordline (CG/FG) and bitline (usually, metal-2 lines), a quadruple patterning technology (QPT) seems to be very mature for each of the major NAND players. They use their own QPT integration on three critical layers with three or four masks, SOH etching and two-step self-align reverse patterning (SARP) process. Although the critical dimensions have a little skew on every four patterns, they have successfully developed QPT integration with less than 1nm CD (Critical Dimension) and it could be extended into 10nm and even single-digit nanometer NAND products. Fortunately and thanks to state-of-the-art anisotropic plasma etching and ALD/CVD technology, uniformly repeated 8nm patterns would be possible for NAND cell array. Figure 3 shows a comparison of DPT/QPT patterns for each product.

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Micron uses a 3.3nm thin-FG poly-Si storage node to decrease cell-to-cell interference, while other manufacturers introduce an air-gap process for active, gate wordline (FG/CG) and bitline (metal-2) for thick-FG structure. Especially, the air-gap process has been developed and applied on the channel region of active patterns and FG/CG pillars help decrease the cross-talk.

For an IPD (Inter-Poly Dielectric) or a barrier layer between CG and FG, a multi-layer stacked with thin oxide (O) and nitride (N) layers such as ONO or NONON structure has been used for mid-10 nm class NAND devices, while Micron uses a high-k dielectrics such as HfO/SiO/HfO/Nitrided-SiO which is the same as their 20 nm NAND products. Micron successfully integrated IPD/FG/Tunnel-oxide and decreased FG thickness from 5 nm to 3.3 nm with high-k IPD. It might be further reduced to 10ish nm NAND products by optimizing IPD/FG quantum well structure for their unique thin-FG architecture. A 6 nm tunnel oxide (SiO) is used on Micron, Toshiba/SanDisk and SK-Hynix, while Samsung uses nitrogen-doped oxide in its top and bottom portion.

Triple-row staggered bitline contacts (BC) are used on Toshiba/SanDisk for the first time which is an excellent choice to make things smooth for cell layout and process integration although NAND string overhead is increased from 13% to 19%. Other players still use double-row staggered BC layouts on their 15nm/16nm NAND products (Figure 4).

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Other barriers to extend 2D planar NAND to 10nm such as CG poly fill-ability, anisotropic etching for SA-FG/STI and CG/FG, cell transistor S/D engineering and leaning effect during the process integration are still there. Nevertheless, major players and their equipment vendors will successfully develop and integrate the 10 nm 2D NAND architecture in a few years.

I believe most of the major NAND players have their own matured process integration capability with assistance from ECC and circuit/layout optimization. 2D NAND technology will be further scaled down to 12nm, 10nm, or even 8ish nm which is more cost-effective than 3D V-NAND for near future NAND products.

HeadshotJeongdong Choe has more than 20 years of experience on semiconductor process and device integration including NAND Flash, DRAM, logic and advanced memory devices at Samsung and SK-Hynix. He works at TechInsights as a consulting engineer especially focusing on memory and logic process integration.

Starting in the second half of 2015, the overall consumption of active-matrix organic light-emitting diode (AMOLED) materials will surge, as LG Display increases the production of white organic light-emitting diode (WOLED) TV panels. In the first half of 2015, the WOLED organic materials market reached $58 million; however, in the second half of the year the market will increase nearly threefold, reaching $165 million. The WOLED organic materials market is forecast to grow at a compound annual growth rate (CAGR) of 79 percent from 2014 to 2019, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight.

“Although the WOLED organic materials market is still at a fledgling state, it will grow considerably in tandem with a rise in WOLED panel production, beginning in the second half of 2015,” said Kihyun Kim, senior analyst for display chemical and materials at IHS Technology. “Since WOLED technology is mainly used for large-area AMOLED displays, particularly TVs, this rapid growth in the WOLED market will lead the continued growth in the overall AMOLED materials market.”

LG Display, the leader in the WOLED panel market, began manufacturing WOLED TV panels in their E3 line in Paju, South Korea, in the fourth quarter (Q4) of 2012. To mass produce WOLED panels, the company installed 8th generation mother glass processing in its E4 line in February 2014. While the line became operational in Q4 2014, the line yield has been low to date; however, full operation is set to begin in earnest in the second quarter (Q2) 2015. “Most AMOLED TV panel makers, especially in China, are focusing on WOLED technology, which supports future WOLED material market growth,” Kim said.

AMOLED_Materials_WOLED_Chart2

The total AMOLED materials market, including both the fine-metal mask red-green-blue (FMM RGB) and WOLED types, will grow 54 percent year over year to reach $658 million in 2015, according to the latest IHS OLED Materials Market Tracker forecast. The AMOLED materials market is expected to reach $2.0 billion in 2019, growing at a CAGR of 37 percent from 2014 to 2019.

Global consumers have lately become less interested in acquiring conventional notebooks with 15-inch displays, and they are instead shifting their spending to smaller product segments. In the first half of 2015, panel shipments in the 15-inch range (i.e., 15.0 inches to 15.9 inches) dropped 14 percent year over year, from 44.5 million to 38.4 million units, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight. At the same time, driven by the popularity of Chromebook, notebook display shipments in the 11-inch range have grown from 8 million units to 11 million units.

Notebook_Displays_Chart

“Thanks to affordable prices, and a completed ecosystem with a host of hardware and app choices and a user-friendly cloud environment, Chromebook has expanded its customer base from small and medium-sized businesses and the education market to general users,” said Jason Hsu, supply chain senior analyst for IHS Technology. “The Chromebook sales region has also expanded from the United States to emerging countries, where more local brands are launching Chromebook product offerings. There are also more products set to debut in the 12-inch range, thanks to the success of the Microsoft Surface Pro 3 and rumors of Apple’s upcoming 12.9-inch tablets.”

According to the most recent IHS Notebook and Tablet Display Supply Chain Tracker, total notebook panel shipments to Lenovo and Hewlett-Packard fell 27 percent month over month from 6.4 million units in May to 4.7 million units in June, while overall set production increased by 13 percent from 5.4 million units to 6.1 million units. These two leading notebook PC brands have recently taken steps to regulate panel inventory, in order to guard against excess product pre-stocking.

“The currency depreciation in Euro zone and emerging counties earlier this year jeopardized consumer confidence and slowed the purchase of consumer electronics, including notebooks,” Hsu said. “Moreover, in April, Microsoft leaked the announcement of its new Windows 10 operating system. Despite Microsoft’s claims that a free upgrade to the new operating system would be available to Windows 8 users, many consumers still deferred purchases, which increased the brands’ set inventory. Notebook manufacturers could decide to lower set production in the third quarter, after the end market becomes sluggish in May and June.”

With notebook panel prices remaining very low, profitability has become an issue, and many panel makers are facing pressure to maintain fab loading and gain market share. “Panel cost structure has become crucial in the struggle to stay competitive,” Hsu said. “Continuous panel over-supply not only hurts profitability, but could also confuse the real panel market demand in the fourth quarter of 2015 and the first quarter of 2016. It’s time for panel makers to revise their production numbers, and curb capacity utilization, to keep pace with actual market demand.”

After leveling off in the second half of the last decade, CMOS image sensors are in the midst of a strong new wave of growth, which is being driven by a broad range of applications and promises to lift worldwide sales to record-high levels each year through 2019, according to the 2015 edition of IC Insights’ O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes. The O-S-D Report’s forecast shows CMOS image sensor sales climbing 15 percent in 2015 to reach an all-time high of $10.1 billion after a strong 19 percent increase in 2014 and subpar 4 percent growth in 2013 that primarily resulted from steep price erosion and inventory corrections in camera phones.  CMOS image sensor unit shipments are now projected to grow 19 percent in 2015 to a record-high 3.7 billion after rising 20 percent in 2014 and 2013 (Figure 1).

Figure 1

Figure 1

For about 15 years, digital cameras in cellphone handsets have been the dominant system application in CMOS image sensors and that will continue to be the case in the second half of this decade, but growth rates in this optoelectronics semiconductor category are expected to be pushed higher by new automotive and machine-vision applications, security and surveillance systems (including body cameras), medical imaging, and a wide assortment of optical-sensing nodes tied to the Internet of Things (IoT).  In 2014, about 70 percent of CMOS image sensor sales ($6.2 billion) were for embedded cameras in cellphones, but that percentage is expected to fall to 49 percent in 2019 ($7.3 billion), which represents a compound annual growth rate (CAGR) of just 3.4 percent, based on the forecast presented in the 2015 O-S-D Report.  In comparison, total CMOS image sensor sales are projected to grow by a CAGR of 11.1 percent in the five-year forecast period to reach $15.0 billion in 2019.

The 2015 O-S-D Report forecasts sales of CMOS image sensor sales for automotive safety systems will climb by a CAGR of 57.4 percent to $2.1 billion in 2019 and represent 14 percent of the market’s total dollar volume that year compared to just 3 percent in 2014.  CMOS image sensor sales for security systems and surveillance applications are expected to grow by a CAGR of 38.4 percent in the five-year forecast period to $899 million in 2019, which will represent 6 percent of the market’s total sales that year versus 2 percent in 2014. The O-S-D Reportshows medical and scientific instrument applications driving up CMOS image sensors sales by a CAGR of 36.0 percent to $824 million in 2019 or about 6 percent of the total market compared to about 2 percent in 2014. Toys and video game applications are expected to increase sales of CMOS image sensors by a CAGR of 32.7 percent to $255 million by 2019, which will represent 2 percent of the market’s total revenue compared to 1 percent in 2014.

Major suppliers of CMOS image sensors are responding to the shift in what’s driving sales growth.  For instance, CMOS image sensor leader Sony now aims to become the largest supplier of imaging solutions for automotive systems by the middle of the next decade after it accomplished its goal of taking the top spot in camera phones in the past few years. Sony’s CMOS image sensor sales grew 31 percent in 2014 to about $2.8 billion, which represented a 32 percent share of the market’s total revenues, based on the supplier ranking in the 2015 O-S-D Report.  After Sony, U.S.-based OmniVision was second in CMOS image sensor sales ($1.4 billion in 2014) followed by Samsung ($1.2 billion), Sharp ($720 million), SK Hynix ($488 million), and China’s GalaxyCore ($360 million), according to IC Insights’ supplier ranking.

Worldwide silicon wafer area shipments increased during the second quarter 2015 when compared to first quarter area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,702 million square inches during the most recent quarter, a 2.5 percent increase from the 2,637 million square inches shipped during the previous quarter resulting in a new quarterly volume shipment record. New quarterly total area shipments are 4.4 percent higher than second quarter 2014 shipments. First half 2015 shipments are 7.8 percent higher than the first half of 2014.

“For two consecutive quarters, strong silicon shipment growth has been recorded by the Silicon Manufacturers Group,” said Ginji Yada, chairman of SEMI SMG and general manager, International Sales & Marketing Department of SUMCO Corporation. “Continued growth off of the record level shipped in the first quarter, produced another record level of shipments in the most recent quarter.”

Quarterly Silicon* Area Shipment Trends

 Million Square Inches

 
 Q2-2014

 

  Q1-2015  Q2-2015  1H-2014  1H-2015
Total

 

 2,587 2,637 2,702 4,951 5,339

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.  For more information on SEMI, visit www.semi.org.