Semiconductors, metals and insulators must be integrated to make the transistors that are the electronic building blocks of your smartphone, computer and other microchip-enabled devices. Today’s transistors are miniscule–a mere 10 nanometers wide–and formed from three-dimensional (3D) crystals.

But a disruptive new technology looms that uses two-dimensional (2D) crystals, just 1 nanometer thick, to enable ultrathin electronics. Scientists worldwide are investigating 2D crystals made from common layered materials to constrain electron transport within just two dimensions. Researchers had previously found ways to lithographically pattern single layers of carbon atoms called graphene into ribbon-like “wires” complete with insulation provided by a similar layer of boron nitride. But until now they have lacked synthesis and processing methods to lithographically pattern junctions between two different semiconductors within a single nanometer-thick layer to form transistors, the building blocks of ultrathin electronic devices.

Now for the first time, researchers at the Department of Energy’s Oak Ridge National Laboratory have combined a novel synthesis process with commercial electron-beam lithography techniques to produce arrays of semiconductor junctions in arbitrary patterns within a single, nanometer-thick semiconductor crystal. The process relies upon transforming patterned regions of one existing, single-layer crystal into another. The researchers first grew single, nanometer-thick layers of molybdenum diselenide crystals on substrates and then deposited protective patterns of silicon oxide using standard lithography techniques. Then they bombarded the exposed regions of the crystals with a laser-generated beam of sulfur atoms. The sulfur atoms replaced the selenium atoms in the crystals to form molybdenum disulfide, which has a nearly identical crystal structure. The two semiconductor crystals formed sharp junctions, the desired building blocks of electronics. Nature Communications reports the accomplishment.

“We can literally make any kind of pattern that we want,” said Masoud Mahjouri-Samani, who co-led the study with David Geohegan. Geohegan, head of ORNL’s Nanomaterials Synthesis and Functional Assembly Group at the Center for Nanophase Materials Sciences, is the principal investigator of a Department of Energy basic science project focusing on the growth mechanisms and controlled synthesis of nanomaterials. Millions of 2D building blocks with numerous patterns may be made concurrently, Mahjouri-Samani added. In the future, it might be possible to produce different patterns on the top and bottom of a sheet. Further complexity could be introduced by layering sheets with different patterns.

Added Geohegan, “The development of a scalable, easily implemented process to lithographically pattern and easily form lateral semiconducting heterojunctions within two-dimensional crystals fulfills a critical need for ‘building blocks’ to enable next-generation ultrathin devices for applications ranging from flexible consumer electronics to solar energy.”

Tuning the bandgap

“We chose pulsed laser deposition of sulfur because of the digital control it gives you over the flux of the material that comes to the surface,” said Mahjouri-Samani. “You can basically make any kind of intermediate alloy. You can just replace, say, 20 percent of the selenium with sulfur, or 30 percent, or 50 percent.” Added Geohegan, “Pulsed laser deposition also lets the kinetic energy of the sulfur atoms be tuned, allowing you to explore a wider range of processing conditions.”

It is important that by controlling the ratio of sulfur to selenium within the crystal, the researchers can tune the bandgap of the semiconductors, an attribute that determines electronic and optical properties. To make optoelectronic devices such as electroluminescent displays, microchip fabricators integrate semiconductors with different bandgaps. For example, molybdenum disulfide’s bandgap is greater than molybdenum diselenide’s. Applying voltage to a crystal containing both semiconductors causes electrons and “holes” (positive charges created when electrons vacate) to move from molybdenum disulfide into molybdenum diselenide and recombine to emit light at the bandgap of molybdenum diselenide. For that reason, engineering the bandgaps of monolayer systems can allow the generation of light with many different colors, as well as enable other applications such as transistors and sensors, Mahjouri-Samani said.

Next the researchers will see if their pulsed laser vaporization and conversion method will work with atoms other than sulfur and selenium. “We’re trying to make more complex systems in a 2D plane–integrate more ingredients, put in different building blocks–because at the end of the day, a complete working device needs different semiconductors and metals and insulators,” Mahjouri-Samani said.

To understand the process of converting one nanometer-thick crystal into another, the researchers used powerful electron microscopy capabilities available at ORNL, notably atomic-resolution Z-contrast scanning transmission electron microscopy, which was developed at the lab and is now available to scientists worldwide using the Center for Nanophase Materials Sciences. Employing this technique, electron microscopists Andrew Lupini and visiting scientist Leonardo Basile imaged hexagonal networks of individual columns of atoms in the nanometer-thick molybdenum diselenide and molybdenum disulfide crystals.

“We could directly distinguish between sulfur and selenium atoms by their intensities in the image,” Lupini said. “These images and electron energy loss spectroscopy allowed the team to characterize the semiconductor heterojunction with atomic precision.”

Because it can achieve extreme deformation, Equal Channel Angular Extrusion (ECAE) can deliver submicron, high strength and uniform microstructures. The resulting improvements in strength allow for monolithic targets with a longer target life of 20-100%.

BY STEPHANE FERRASSE, SUSAN STROTHERS and CHRISTIE HAUSMAN, Honeywell Electronic Materials, Sunnyvale, CA

First observed in 1852, cathodic sputtering is a form of physical vapor deposition (PVD) that involves the bombardment of a target material by positive ions to physically remove atoms from the surface, forming a vapor for substrate coating. It wasn’t until the 1960s and the growth of the electronics industry, however, that sputtering received significant attention.

Since then, sputtering has become entrenched in many integrated circuit (IC) production processes. While sputtering performance has benefited from advanced sputtering system designs and target material improvements, more is needed to meet future demands as device features shrink and thin film specifications become tighter.

The physical and chemical properties of sputtering targets play an integral role in thin film performance and device yield since they impact thin film composition, uniformity, consistency, defects (particulate), and step coverage. In addition, target utilization and lifetime is a factor in cost of ownership (CoO) as it correlates to chamber throughput and uptime.

This article explores how the microstructure of sputtering targets can be engineered to improve strength, life and thin film quality. It also compares conventional thermo-mechanical processing (TMP) to the breakthrough TMP of Equal Channel Angular Extrusion (ECAE) technology from Honeywell.

Key sputtering target properties

A great deal of research has been directed toward improving the microstructure of sputtering targets. Key target properties and challenges that impact thin film functionality and device yield include:

Chemical purity: Elemental impurities in sputtering targets are undesirable as they transfer to the thin film and adversely impact performance. However, higher purity metals are weaker and less able to withstand the stresses induced in the sputtering chamber. This poses unique manufacturing and end-use challenges unlike most other uses of metallic products.

Metallurgical defects: Thin film particulate contamination has been an ongoing and growing challenge with each successive technology node. Porosity, inclusions, inconsistent grain structures, and large second phases present in the target material can — through arcing — cause direct or indirect particulate contamination on the wafer.

Thermal stability: High thermal stability in the target material is needed to withstand high-power sputtering applications.

Target grain size: Fine grain size provides higher strength and contributes to superior film uniformity. Consistent grain structure throughout the target provides stable uniformity through target life.

Target strength: Sufficient yield strength is required to prevent target warping, which can contribute to film non-uniformity and arcing.

Key solutions to those challenges include:

Alloying or doping is an extremely common way to add strength, increase thermal stability and promote grain refinement in all metals. Unfortunately, in semiconductor applications it is usually not desirable for alloys or doping elements to become part of the thin film itself, so it is rarely an option. The exception is when the alloying element improves the thin film properties.

The use of high strength backing plates bonded to high purity targets to add strength to the entire target assembly. This is a very common and acceptable practice, but it introduces several risks and manufacturing challenges, such as a failed bond, arcing at the bond line and deflection in the assembly. Coefficient of thermal expansion (CTE) mismatches between the target and the backing plate can also pose serious challenges to target manufacturing, especially for brittle materials. Furthermore, the use of high-temper- ature bonding methods can cause grain growth and destroy desirable target metallurgical properties. This necessitates trade-offs between grain size, bond type and bond strength.

Improvements in TMP to improve the micro- structure, as described in the next section.

TMP fabrication overview

The choice of fabrication method has an impact on sputtering performance because the more defor- mation applied to the metal, the smaller the grain size. Two types of TMP, shown schematically in FIGURE 1, are described below.

Conventional TMP. This uses a combination of forging, rolling and heat treatment steps to obtain finer microstructures. It delivers good results and has been the industry standard. It is, however, restricted in terms of the amount of strain and deformation it can impart on the material. The amount of deformation, often expressed as a percent reduction of billet height, is limited to about 90% (equivalent strain of 2.3) in practice for targets. Higher reductions of greater than 90% require excessive tonnage and initial billet height, and impose severe requirements on conventional TMP equipment (stroke, daylight and tonnage capability). The maximum attainable strain of approximately 2.3 is not optimal for refinement of grain size. This, combined with the need for a backing plate to add strength, may not meet the needs of high-performance IC applications.

ECAE. This is a state-of-the-art extrusion process that is specifically designed to deliver the next level of microstructure performance. A billet is extruded through two intersecting channels of equal cross-sections – allowing attainable strains of 4.6-7, equivalent to greater than 99.9% reduction. As shown in FIGURE 1, the channels meet at a 90-degree angle and severe plastic deformation is realized uniformly by simple shear, in multiple passes, without changing the size or shape of the starting material. ECAE also has the flexibility to manipulate the metal in multiple directions. Together, these features enable submicron and homogenous microstructures.

Performance comparisons

Finer grain structures result in improved yield strength and ultimate tensile strength, as described below:

Grain Sizes The attainable grain sizes for ECAE versus conventional TMP methods are shown in TABLE 1. As shown, the extreme deformation of ECAE results in finer microstructures, and thus improved strength. Grain sizes from 0.2-0.8 m can be achieved for monolithic targets, a refinement in grain size by a factor of up to 100 times depending on the material.

Strength The ability of ECAE grain refinement to improve yield strength (YS) and ultimate tensile strength (UTS) is dramatic. YS, in particular, is critical for target applications because it governs the onset of permanent plastic deformation that leads to target warping. As shown in FIGURE 2, the yield strength of several ECAE submicron grained, high purity materials – including Al-0.5 wt% Cu, Cu, Cu-0.11 wt% Al, and Cu-1% Mn – is four to six times higher than a conventional TMP material.

Thermal Stability Thermal stability in terms of a material’s resistance to grain growth during sputtering is critical for consistent thin-film uniformity. The grain structures in Table 1 for both ECAE and conventional TMP materials are stable under high power sputtering conditions.

Metallurgical Defects Any heat treatment can be performed prior to ECAE because the level of grain refinement during ECAE does not depend on initial grain size. Therefore, traditional heat treatment such as solutionizing used in conven- tional TMP can be completely replaced or combined optimally with ECAE to remove or refine second phase precipitates. For example, as shown in FIGURE 3 in the optical micrograph, a conventional TMP Al0.5Cu exhibits 1-7 m (AlCu) second phases. However, during the multi-pass ECAE process at room temperature, repetitive shearing, elongation, breakage and homogenization of second phases leads to their refinement to less than 100 nm as displayed in the TEM image of submicron ECAE Al0.5Cu. This is a dramatic refinement of second phases by a factor of over 100 compared to conventional TMP targets. ECAE has a similar effect on refinement and reduction of other material defects such as voids, inclusions or dendrites.

ECAE cost-performance benefits

The properties of ECAE targets described above provide important cost-performance benefits over conventional TMP techniques, allowing users to lower their total CoO. A few key examples are described below.

Monolithic Design Improves Target Life and Productivity

With ECAE, previously bonded planar Al and Cu alloy targets can be designed as single-piece, monolithic targets. This translates into a longer target life versus their bonded counterparts produced via conventional TMP. As shown in FIGURE 4, sputtering is not limited by the bond line and therefore, the erosion groove can extend much deeper for optimum material utilization. In fact, monolithic ECAE submicron Al and Cu alloy targets (200 mm and 300 mm) show a 20-100% increase in target life.

This longer target life equates to cost savings by:

• Reducing downtime associated with target changes for greater tool utilization.
• Reducing the cost per kWh of the sputtering target.
• Eliminating risks associated with backing plates such as de-bonding or deflection.

Improved Wafer Yield Due To Improved

Performance An even greater cost savings for users is the increase in wafer yield associated with better performing sputtering targets. Second- phase precipitates, inclusions and voids all contribute to arcing and subsequent wafer-killing defects. Minimizing these defects drastically reduces potential sources for arcing. Additionally, submicron microstructures are more resistive, which increases the threshold voltage for arcing and enhances plasma stability. Put simply, when arcing is reduced, wafer particles are reduced and wafer yield is increased. Increasing wafer yield has the single most dramatic impact on device cost.

Summary

Sputtering targets produced via TMP – both conventional and ECAE – are designed to meet thin film deposition needs. ECAE, however, has the added ability to meet more challenging IC geometries and performance. Because it can achieve extreme deformation, ECAE can deliver submicron, high strength and uniform microstructures.

The resulting improvements in strength allow for monolithic targets with a longer target life of 20-100%, depending on design. Added to this is the ability of ECAE to minimize arcing, and to reduce the size of precipitates and inclusions and other metallurgical defects, while meeting needs for chemical purity and thermal stability.

Manufacturers can reduce their CoO through improvements in thin film uniformity, greater productivity, higher wafer yield, lower production costs and less downtime.

STEPHANE FERRASSE, SUSAN STROTHERS and CHRISTIE HAUSMAN are with Honeywell Electronic Materials, Spokane, WA.