By David W. Price and Douglas G. Sutherland

Author’s Note: This is the eighth in a series of 10 installments that explore certain fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications.

Moving to the next design rule can be stressful for the inspection and metrology engineer. Like everything else in the fab, process control generally doesn’t get any easier as design rules shrink and new processes are introduced.

The eighth fundamental truth of process control for the semiconductor IC industry is:

Process Control Requirements Increase with Each Design Rule

This statement has proven to be historically accurate, as evidenced by the increase in process control spending as a percentage of wafer front-end (WFE) total costs. This article, however, will focus on a few of the forward-looking observations that we believe will further accelerate the adoption of process control.

The historical increase in process control with shrinking design rules has been driven largely by the introduction of key technical inflections. Recent examples for logic/foundry include immersion lithography, high-k metal gates, gate-last integration, and FinFET transistor structures. These high profile process changes required enormous engineering focus and led to the implementation of new inspection and metrology steps to characterize the associated defectivity and drive yield learning.

While the industry will continue to face significant technical challenges (next-generation lithography being the most obvious example), there is another factor emerging which will play an equally large role in setting the inspection and metrology strategy for the 16/14nm design node and beyond.

Figure 1 shows the number of process steps as a function of design rule for a generic logic/foundry process. Up to the 20nm node, there has been a very modest increase in process steps with design rule shrinks due to, for example, more metal levels and the addition of hard mask steps. But starting at 16/14nm, there will be an unprecedented increase in the number of process steps. This jump in process steps will be driven by:

• The shift from 2D to 3D transistor structures in both logic and memory
• More complicated integration in both the front end and back end
• The push-out of EUV lithography, leading to massive numbers of multi-patterning steps

Process Tool Defectivity

Because of this increase in process steps—and the accumulative nature of yield loss—fabs must reduce the defectivity at each individual step in order to achieve the same final yield. Figure 2 shows the total yield as a function of the number of process steps where the average per-step yield is held constant. Prior to 16/14nm, this effect was scarcely noticeable since the total increase in process steps was minimal.

Moving forward, fab defect reduction teams must continue to resolve the challenging new technical inflections. But they must also place more focus on driving down defectivity at all process steps:

1. Line Yield: To maintain the same line yield (wafers out / wafers in), there must be fewer excursions and less scrap at each step
2. Die Yield: Every operation in the fab must be held to a tighter specification for defect density (D0) and variation (Cpk)

To make matters worse, defect inspection and metrology operations will continue to become more difficult. The defect count must go down even as the number of yield-relevant defects increases and the detection task becomes harder. Similarly, the variability in metrology measurements must be reduced even as those measurements become more difficult to make.

Impact on Cycle Time

The increase in process steps has another downside: increased cycle time. If cycle time increases in proportion to the number of process steps then it follows from Figure 1 that the cycle time will roughly double from the 20nm to the 10nm node. One publication has even suggested that the cycle time may double from 20nm to an advanced 16nm process ^[2].

The fab’s ability to do yield learning via feedback from electrical test and physical failure analysis (PFA) is directly tied to the “hot lot” cycle time. Longer hot-lot cycle times mean fewer opportunities for these long-loop learning cycles as device manufacturers try to ramp yield and deliver products to market. More emphasis must therefore be placed on in-line yield learning methodologies.

Sampling Pressure

Finally, more process steps will increase the manufacturing cost per wafer. In the second article in this series, Sampling Matters, we showed that the ideal sampling rate (that which provides the lowest total cost to the fab) goes with the square root of the device manufacturing cost. In other words, if the manufacturing cost increases by 30 percent then the corresponding process control sampling rate needs to increase by 14 percent (everything else being constant) to stay at the lowest total cost. This sampling increase will put further pressure on the fab’s inspection and metrology teams.

Summary

In summary, each new design rule will introduce:

• Technical inflections that require engineering focus and innovation, as well as the implementation of new process control methodologies
• More process steps that must be directly monitored
• Tighter controls and lower defect density at each individual step due to the compounding nature of yield loss
• Longer cycle times, resulting in more reliance on in-line (vs. end-of-line) techniques for yield learning
• Higher stakes (greater economic impact to the fab) in the event of an excursion due to the higher wafer manufacturing costs, which will put pressure on the fab to increase inspection and metrology sampling

The cascade of challenges that flows from the increase in process steps is sometimes referred to as the “Tyranny of Numbers.” For further exploration of how fabs are adapting their process control strategy for new design rules, please contact the authors of this article.

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

1. Lipsky, “TSMC Outlines 16nm, 10nm Plans.” EE Times, 4/8/2015.
2. Jones, Strategic Cost Model, IC Knowledge, LLC. http://www.icknowledge.com/

Read more Process Watch: 

Time is the enemy of profitability

Know your enemy

The most expensive defect

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”