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Research led by Michigan State University could someday lead to the development of new and improved semiconductors.

In a paper published in the journal Science Advances, the scientists detailed how they developed a method to change the electronic properties of materials in a way that will more easily allow an electrical current to pass through.

The electrical properties of semiconductors depend on the nature of trace impurities, known as dopants, which when added appropriately to the material will allow for the designing of more efficient solid-state electronics.

The MSU researchers found that by shooting an ultrafast laser pulse into the material, its properties would change as if it had been chemically “doped.” This process is known as “photo-doping.”

“The material we studied is an unconventional semiconductor made of alternating atomically thin layers of metals and insulators,” said Chong-Yu Ruan, an associate professor of physics and astronomy who led the research effort at MSU. “This combination allows many unusual properties, including highly resistive and also superconducting behaviors to emerge, especially when ‘doped.'”

An ultrafast electron-based imaging technique developed by Ruan and his team at MSU allowed the group to observe the changes in the materials. By varying the wavelengths and intensities of the laser pulses, the researchers were able to observe phases with different properties that are captured on the femtosecond timescale. A femtosecond is 1 quadrillionth, or 1 millionth of 1 billionth, of a second.

“The laser pulses act like dopants that temporarily weaken the glue that binds charges and ions together in the materials at a speed that is ultrafast and allow new electronic phases to spontaneously form to engineer new properties,” Ruan said. “Capturing these processes in the act allows us to understand the physical nature of transformations at the most fundamental level.”

Philip Duxbury, a team member and chairperson of the department of physics and astronomy, said ultrafast photo-doping “has potential applications that could lead to the development of next-generation electronic materials and possibly optically controlled switching devices employing undoped semiconductor materials.”

A semiconductor is a substance that conducts electricity under some conditions but not others, making it a good medium for the control of electrical current. They are used in any number of electronics, including computers.

Bruno Mourey, chef du Département intégration hétérogène sur siliciumBy Bruno Mourey, Chief Technology Officer, CEA-Leti

As these early days of the Internet of Things show the network’s promise and reveal technological challenges that could threaten its ability to meet user expectations in the years ahead, technology providers will be charged with supplying the solutions that will meet those challenges.

Chief among them for designers and chipmakers are the increased complexity and cost of IC design and yield ramp-ups, and wafer costs, said Carlo Reita, strategic marketing manager at CEA-Leti.

“Disruptive architecture and integration technologies are required,” Reita told participants at the 17th annual LetiDays in Grenoble, France, June 24-25. In his talk, “Technologies and architectures for low-power data processing,” Reita noted the spikes in both complexity and cost that accompany the industry’s progression to smaller technology nodes. The spikes are driven primarily by costly new tools and increases in both design manpower and the number of expensive licenses for software-design tools that accompany increasing device complexity.

Reita cited projections from IBS that industry-wide, non-recurring engineering (NRE) costs will total $38 million for IC designs at the 28nm node, $132 million at the 16nm node and $1.34 billion at the 5nm node.

Adding yield ramp-up costs to IC design costs, which include both new designs and specializations, the projected NREs skyrocket from $59 million at 28nm to $176 million at 16nm and $2.24 billion at 5nm. Meanwhile, the average selling price of 300mm wafers grow from $9,885 at 16nm to $19,620 at 5nm.

Reita noted that such projections underscore the pressure that the industry will face to develop new design-implementation approaches that change the cost metrics for advanced-features, so that initial products can generate revenues that justify the design and yield ramp-up costs.

He said that managing data traffic that is increasing exponentially, while maintaining data-center server performance and lowering the centers’ energy consumption, is among the top challenges for the computing industry in the years ahead. Meanwhile, mobile computing and the Internet of Things are adding a different set of challenges that will feed the design-cost escalation, ranging from the requirement for mandatory long battery life to supporting heterogeneous and power-hungry applications and the capability to adjust to process, voltage and temperature variations.

Reita also outlined Leti’s plans and vision for technologies that address these challenges in the short, medium and longer terms.

Like other speakers during the two-day event, he noted FD-SOI’s advantages compared to FinFET as a proven low-power, cost-effective solution that will meet current and mid-term needs for devices down to the 10nm node. In addition, transistor-stacking options, such as Leti’s low-temperature CoolCube technology, support denser and higher-performing CMOS devices. CoolCube also makes it easier for designers to use heterogeneous integration of material and/or functions and provides a greater degree of freedom for design partitioning, Reita said.

Other avenues of exploration include adaptive fine-grain architecture that mitigates local and dynamic PVT variations, and permits either better use of the chip surface or smaller chips

Leti also is working on resistive RAM that can reduce power consumption at the storage level by putting high-density, non-volatile memory closer to logic chips.

On Leti’s roadmap for the medium term, neuromorphic architectures may enable full transfer of successful algorithms into a specific physical system that will achieve power-efficient computation. Deep recurrent networks with spike coding are a likely candidate to best match physical implementation characteristics.

In Leti’s view, this architecture also allows co-localization of memory and computation similar to a biological system, where a synaptic element performs storage, interconnect and non-linear operations. In addition, the architecture takes full advantage of Leti’s advanced RRAM, 3D and low-power CMOS techniques to break memory-bottleneck and synaptic-density issues, while maintaining ultra low power.

Reita also spoke briefly about quantum computing, “a very long-term” technology possibility, whose appeal includes superposition of the quantum bits (qubits) states in an ultimate parallel system and reversible operators that keep power use at a minimum. This architecture, which is probably 20 years down the road, is expected to massively accelerate computation. It will be best suited for tackling complex optimization problems, Reita said.

Leti collaborates with CEA’s fundamental research departments on topics including SiGe nanowire devices, in which electronics states can act as qubits and use Pauli spin blockade for spin-charge conversion and interaction with CMOS and the external world.

Related news:

Leti workshop covers major trends in FD-SOI technologies

ASCENT project offers unparalleled access to European nanoelectronics infrastructure

Leti launches new Silicon Impulse FD-SOI Development Program

Power transistor sales are forecast to grow 6 percent in 2015 and set a new record high of $14.0 billion following a strong recovery in 2014, which drove up dollar volumes by 14 percent after two consecutive years of decline, according to IC Insights’ 2015 O S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.  In the last six years, power transistor sales have swung wildly, overshooting and undershooting end-use demand as equipment makers struggled to balance inventories in the midst of economic uncertainty since the 2008-2009 recession.

IC Insights believes the power transistor business is finally stabilizing and returning to more normal growth patterns in the 2014-2019 forecast period of the 2015 O-S-D Report.  Driven by steady increases in automotive, consumer electronics, portable systems, industrial, and wireless communications markets, power transistor sales are expected to rise by a compound annual growth rate (CAGR) of 5.3 percent between 2014 and 2019, when worldwide revenues are forecast to reach $17.1 billion (Figure 1).  Worldwide power transistor sales grew by a CAGR of 6.2 percent between 1994 and 2014.

For more than three decades, power transistors have been the growth engine in the commodity-filled discrete semiconductor market, which grew 11 percent in 2014 to a record-high $23.0 billion after falling 7 percent in 2012 and dropping 5 percent in 2013.  The new O-S-D Report shows power transistors accounted for 58 percent of total discretes sales in 2014 versus 51 percent in 2004 and 36 percent in 1994.  A number of power transistor technologies are needed to control, convert, and condition currents and voltages in an ever-expanding range of electronics—including battery-operated portable products, new energy-saving equipment, hybrid and electric vehicles,  “smart” electric-grid applications, and renewable power systems.

Despite the spread of system applications, power transistors have struggled to maintain steady sales growth since the 2009 semiconductor downturn, when revenues fell by 16 percent.  Power transistor sales sharply rebounded in the 2010 recovery year with a record-high 44 percent increase followed by 12 percent growth in 2011 to reach the current annual peak of $13.5 billion.  Power transistors then posted the first back-to-back annual sales declines in more than 30 years (-8 percent in 2012 and -6 percent in 2013) due to inventory corrections, price erosion, and delays in purchases by cautious equipment makers responding to economic uncertainty.   Power transistors ended the two-year losing streak in 2014 with sales and unit shipments both growing by 14 percent.

Figure 1

Figure 1

The 2015 O-S-D Report’s forecast shows power transistor sales returning to a more normal 6% increase in 2015 with power FET revenues growing 6 percent to $7.4 billion, insulated-gate bipolar transistor (IGBT) modules climbing 8 percent to $3.1 billion, IGBT transistors rising 6 percent to $1.1 billion, and bipolar junction transistors being up 4 percent to $893 million this year.

Semiconductor Manufacturing International Corporation, China’s largest and most advanced semiconductor foundry; Huawei, a global information and communications technology (ICT) solutions provider; imec, a nanoelectronics research and development (R&D) centers; and Qualcomm Global Trading Pte. Ltd., an affiliate of Qualcomm Incorporated, one of the world’s largest fabless semiconductor vendors, held a signing ceremony at the Great Hall of the People, to announce the formation of SMIC Advanced Technology Research & Development (Shanghai) Corporation, an equity joint venture company. The joint venture company will focus on R&D towards next generation CMOS logic technology and build China’s most advanced integrated circuit (IC) development R&D platform.

His Majesty (H.M.) King Philippe of Belgium is visiting China in the framework of several cooperation agreements between China and Belgium related to cutting-edge technology. A Chinese leader and H.M. King Philippe of Belgium witnessed the signing ceremony of the joint investment.

SMIC Advanced Technology R&D (Shanghai) Corporation will be majority owned by SMIC, while Huawei, imec, and Qualcomm will be minority shareholders. The current focus will be on developing 14nm logic technology. Dr. Tzu-Yin Chiu, Chief Executive Officer and Executive Director of SMIC will be the legal representative, Dr. Yu Shaofeng, Vice President of SMIC will be the general manager.

This project is a major breakthrough in the cooperation model for IC manufacturers, international trade companies and research institutions. This project will facilitate closer cooperation between upstream and downstream companies, leading-edge R&D, and other synergies in the industry’s global eco-system. With the joint venture company oriented on innovation, it can target the demands of the industry more quickly and effectively through its R&D and manufacturing resources. Meanwhile, by enabling fabless semiconductor companies to join the development process as shareholders, the product development cycle can be shortened and the advanced process node tape out time can be accelerated.

In the first phase, the joint venture company will develop 14nm CMOS technology for mass production, which will be based on imec’s knowhow in advanced semiconductor processing technology. The new R&D project will be done at SMIC’s production line.

SMIC will have the rights to license the required intellectual property rights on the mass production technologies of advanced nodes developed by the joint venture company, enabling these technologies to be applied to SMIC’s current and future range of products and serve SMIC’s business with other companies. This can improve the overall level of China’s IC technologies, and is expected to facilitate the mass production of 16/14nm ICs in China by 2020, which is one of the goals set by the National IC Industry Development Outline. In the future, companies in China’s IC manufacturing industry, universities and colleges, and research institutions will continue working together on this platform to further enhance the core competitiveness of the industry.

Dr. Zhou Zixue, Chairman, of SMIC; Steve Chu, Vice President of Huawei; Ludo Deferm, Executive Vice President of Corporate Business and Public Affairs of imec; and Derek Aberle, President of Qualcomm Incorporated were all present at the signing ceremony.

“This is the most advanced work for China’s IC industry,” said Dr. Tzu-Yin Chiu, Chief Executive Officer and Executive Director, of SMIC, “With 15 years of experience in manufacturing and R&D, SMIC is China’s largest semiconductor enterprise and has the capabilities to bring 14nm technology into production. It is exciting to be working with the largest IC design company both in China and abroad, and the world’s top research institutes to tackle advanced IC process technology. This collaboration will play an important role in improving our technologies and products. The new company model has allowed us to explore a new path to open up R&D and manufacturing resources in this industry’s ecosystem, and develop our advanced technology and R&D capabilities. In addition, it actively promotes the collaboration across all parts of the eco-system in China. ”

Steve Chu, Vice President of Huawei said: “Huawei has always been open to win-win partnerships. With our 20 years of experience in the IC design field and collaboration from our global partners, we are keen to promote the development of research capabilities in IC technology, to create China’s most advanced IC R&D platform. We believe that this collaboration will consolidate the IC domain, increase its resources and capabilities, and thereby improving the overall level of China’s IC industry. The improvements will provide more benefits to operators, companies, customers and partners.”

Luc Van den hove, CEO and president of imec, added: “We see a growing potential in China, both as a market and as a source of innovative engineering. The expertise of the four partners is focused on the creation of an excellent platform to foster nanoelectronics R&D in China. And the joint development of a 14nm process facility will be a step stone to achieve this goal. A step stone that, I am convinced, will benefit the world’s IC manufacturing community.”

“We are pleased to collaborate with SMIC, Huawei and imec to establish this new technology R&D joint venture company,” said Derek Aberle, president of Qualcomm Incorporated. “This is a significant milestone for the Chinese and global IC industries, which reinforces Qualcomm’s commitment to the continued growth of the vibrant semiconductor ecosystem in China. We believe that this venture will serve to better meet the growing needs of local Chinese and global customers who demand high performance, low power mobile devices. The collaboration will also help bring even more advanced processing technology and wafer manufacturing capacity to China, thereby helping China to build capability in FinFET technology. “

Cadence Design Systems, Inc. and Applied Materials, Inc. today announced the companies are collaborating on a development program to optimize the chemical-mechanical planarization (CMP) process through silicon characterization and modeling for advanced-node designs at 14 nanometer (nm) and below. The program allows design teams to predict the impact of CMP on both functional yield and parametric yield, and for manufacturing teams to boost planarization performance, which is increasingly critical for advanced FinFET architectures.

The Cadence and Applied Materials joint development program is focused on front end-of-line (FEOL) and wafer-level CMP modeling. Applied Materials can use the Cadence CMP Process Optimizer, a tool that allows silicon calibration of semi-physical models and optimization of CMP material and process parameters such as pressure, polish time and overall CMP uniformity, to enhance the precision performance of its Reflexion LK Prime CMP system.

Once models are calibrated, design teams can leverage Cadence CMP Predictor, a tool that enhances design performance and yield through model-based CMP hotspot detection and CMP-aware RC extraction. It provides full-chip, multi-level CMP thickness and topography predictions for shallow trench isolation (STI) and replacement metal gate (RMG) CMP processes.

Applied Materials is an industry leader in precision CMP technology with its Reflexion LK Prime CMP system that offers high-speed planarization and multi-zone polishing heads to enable superior uniformity and efficiency with low downforce for extendibility to <14nm device generations. The Reflexion LK Prime CMP system also implements a full suite of advanced process control capabilities that ensure excellent within-wafer and wafer-to-wafer process uniformity control and repeatability for all planarization applications.

“Working together with Cadence, we’re driving advances in CMP process performance,” said Derek Witty, vice president and general manager of the CMP Products Group at Applied Materials. “From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster.”

“Cadence CMP Predictor helps turn the uncertainty of manufacturing process variation into predictable impacts, and then minimizes these impacts during the design stage,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “The joint development program with Applied Materials can allow us to drive advancements in CMP modeling processes so our design and manufacturing customers can maximize design yield and performance.”

From connectivity to globalization and sustainability, the “Law” created by Gordon Moore’s prediction for the pace of semiconductor technology advances has set the stage for global technology innovation and contribution for 50 years. The exponential advances predicted by Moore’s Law have transformed the world we live in. The ongoing innovation, invention and investment in technology and the effects that arise from it are likely to enable continued advances along this same path in the future, according to a new report from IHS Inc. Titled “Celebrating the 50th Anniversary of Moore’s Law,” the report describes how the activity predicted by Moore’s Law not only drives technological change, but has also created huge economic value and driven social advancement.

In April of 1965, Fairchild Semiconductor’s Research and Development Director, Gordon Moore, who later founded Intel, penned an article that led with the observation that transistors would decrease in cost and increase in performance at an exponential rate. More specifically, Moore posited that the quantity of transistors that can be incorporated into a single chip would approximately double every 18 to 24 months. This seminal observation was later dubbed “Moore’s Law.”

“Fifty years ago today, Moore defined the trajectory of the semiconductor industry, with profound consequences that continue to touch every aspect of our day-to-day lives,” said Dale Ford, vice president and chief analyst for IHS Technology. “In fact, Moore’s Law forecast a period of explosive growth in innovation that has transformed life as we know it.”

The IHS Technology report, which is available as a free download, finds that an estimated $3 trillion of additional value has been added to the global gross domestic product (GDP), plus another $9 trillion of indirect value in the last 20 years, due to the pace of innovation predicted by Moore’s Law. The total value is more than the combined GDP of France, Germany, Italy and the United Kingdom.

If the cadence of Moore’s Law had slowed to every three years, rather than two years, technology would have only advanced to 1998 levels: smart phones would be nine years away, the commercial Internet in its infancy (five years old) and social media would not yet have skyrocketed.

“Moore’s Law has proven to be the most effective predictive tool of the last half-century of technological innovation, economic advancement, and by association, social and cultural change,” Ford said. “It has implications for connectivity and the way we interact, as evidenced by the way social relationships now span the globe. It also provides insight into globalization and economic growth, as technology continues to transform entire industries and economies. Finally it reveals the importance of how sustainability affects life on Earth, as we continue to transform our physical world in both positive and negative ways.”

Moores Law full

The Moore’s Law Era: Explosive Economic and Societal Change

The consequences of Moore’s Law has fueled multifactor productivity growth. The activity forecast by the law has contributed a full percentage point to real GDP growth, including both direct and indirect impact, every year between 1995 and 2011, representing 37 percent of global economic impact.

“Not even Gordon Moore himself predicted the blistering pace of change for the modern world,” Ford said. “While it is true most people have never seen a microprocessor, every day we benefit from experiences that are all made possible by the exponential growth in technologies that underpin modern life.”

According to the “Moore’s Law Impact Report,” the repercussions of Moore’s Law have contributed to an improved quality of life, because of the advances made possible in healthcare, sustainability and other industries. The results of advanced digital technology include the following:

  • Forty percent of the world’s households now have high-speed connections, compared to less than 0.1 percent in 1991
  • Up to 150 billion incremental barrels of oil could potentially be extracted from discovered global oil fields
  • Researchers can perform 1.5 million high-speed screening tests per week (up from 180 in 1997), allowing for the development of new material, such as bio-fuels and feedstock’s for plant-based chemicals

Moore’s Law: Reflecting the Pace of Change

Moore’s Law is not a law but an unspoken agreement between the electronics industry and the world economy that inspires engineers, inventors and entrepreneurs to think about what may be possible.

“Whatever has been done, can be outdone,” said Gordon Moore. “The industry has been phenomenally creative in continuing to increase the complexity of chips. It’s hard to believe – at least it’s hard for me to believe – that now we talk in terms of billions of transistors on a chip rather than tens, hundreds or thousands.”

Moore’s observation has transformed computing from a rare, expensive capability into an affordable, pervasive and powerful force – the foundation for Internet, social media, modern data analytics and more. “Moore’s Law has helped inspire invention, giving the world more powerful computers and devices that enable us to connect to each other, to be creative, to be productive, to learn and stay informed, to manage health and finances, and to be entertained,” Ford said.

Millennials: The Stewards of Moore’s Law

From the changing shape and feel of how humans communicate to the delivery of healthcare, changing modes of transportation, cities of the future, harvesting energy resources, classroom learning and more – technology innovations that spring from Moore’s Law likely will remain a foundational force for growth into the next decade.

From data sharing, self-driving cars and drones to smart cities, smart homes and smart agriculture, Moore’s Law will enable people to continuously shrink technology and make it more power efficient, allowing creators, engineers and makers to rethink where – and in what situations – computing is possible and desirable.

Computing may disappear into the objects and spaces that we interact with – even the fabric of our clothes or ingestible tracking devices in our bodies. New devices may be created with powerful, inexpensive technology and combining this with the ability to pool and share more information, new experiences become possible.

North America-based manufacturers of semiconductor equipment posted $1.56 billion in orders worldwide in May 2015 (three-month average basis) and a book-to-bill ratio of 0.99, according to the May EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 0.99 means that $99 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in May 2015 was $1.56 billion. The bookings figure is 0.8 percent lower than the final April 2015 level of $1.57 billion, and is 11.0 percent higher than the May 2014 order level of $1.41 billion.

The three-month average of worldwide billings in May 2015 was $1.57 billion. The billings figure is 3.7 percent higher than the final April 2015 level of $1.51 billion, and is 11.6 percent higher than the May 2014 billings level of $1.41 billion.

“The May book-to-bill ratio slipped below parity as billings improved and bookings dipped slightly from April’s values,” said Denny McGuirk, president and CEO of SEMI.  “Compared to one year ago, both bookings and billings continue to trend at higher levels.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
December 2014 

$1,395.9

$1,381.5

0.99
January 2015 

$1,279.1

$1,325.6

1.04
February 2015 

$1,280.1

$1,313.7

1.03
March 2015 

$1,265.6

$1,392.7

1.10
April 2015 (final)

$1,515.3

$1,573.7

1.04
May 2015 (prelim)

$1,571.2

$1,561.4

0.99

Source: SEMI (www.semi.org), June 2015

Since the global economic recession of 2008-2009, the IC industry has been on a mission to pare down older capacity (i.e., ≤200mm wafers) in order to produce devices more cost-effectively on larger wafers.  From 2009-2014, semiconductor manufacturers have closed or repurposed 83 wafer fabs, according to data compiled, updated, and now available in IC Insights’ Global Wafer Capacity 2015-2019 report.

Figure 1 shows that 41 percent of fab closures since 2009 have been 150mm fabs and 27 percent have been 200mm wafer fabs.  Qimonda was the first company to close a 300mm wafer fab after it went out of business in early 2009.  More recently, ProMOS and Powerchip closed their respective 300mm wafer fabs in 2013.

IC fabs Fig 1

 

Semiconductor suppliers in Japan have closed 34 wafer fabs since 2009, more than any other country/region over the past six years.   In the 2009-2014 timeframe, 25 fabs were closed in North America and 17 were shuttered in Europe (Figure 2).

IC fabs Fig 2

 

Worldwide fab closures surged in 2009 and 2010 partly as a result of the severe economic recession at the end of the previous decade.  A total of 25 fabs were closed in 2009, followed by 24 being shut down in 2010.  Ten fabs closed in 2012 and 12 were removed from service in 2013.  Six fabs were closed in both 2011 and in 2014, the fewest number of closures per year during the 2009-2014 time span.

Given the flurry of merger and acquisition activity seen in the semiconductor industry recently, the skyrocketing cost of new wafer fabs and manufacturing equipment, and as more IC companies transition to a fab-lite or fabless business model, IC Insights expects the number of fab closures to accelerate in the coming years—a prediction that will likely please foundry suppliers but make semiconductor equipment and material suppliers a little bit nervous.

Fairchild, a supplier of high-performance semiconductor solutions, today launched the FIS1100 6-axis MEMS Inertial Measurement Unit (IMU), the company’s first MEMS product stemming from its strategic investments in MEMS and motion tracking. The FIS1100 IMU integrates a proprietary AttitudeEngine motion processor with best-in-class 9-axis sensor fusion algorithms to provide designers with an easy to implement, system-level solution for superior user experiences with up to ten times lower processing power consumption in a wide range of motion enabled, battery-powered applications.

Fairchild's FIS1100 Intelligent IMU is an easy-to-implement, system-level motion tracking solution that can reduce processor power consumption by as much as 10x. (Graphic: Business Wire)

Fairchild’s FIS1100 Intelligent IMU is an easy-to-implement, system-level motion tracking solution that can reduce processor power consumption by as much as 10x. (Graphic: Business Wire)

“The launch of Fairchild’s first MEMS product is a key milestone for the company as we take our unique design and manufacturing expertise and apply it towards system-level solutions that go beyond power,” said Fairchild Chairman & CEO Mark Thompson. “The advanced algorithms and deep applications know-how from the Xsens acquisition position us well in enabling our customers to develop advanced motion solutions in diverse, quickly growing segments within markets such as consumer, industrial, and health.”

The FIS1100 IMU, with its built in AttitudeEngine motion processor and XKF3 senor fusion, is a low power, highly accurate system solution that provides customers with the always-on sensor technology required for a range of application such as wearable sensors for sports, fitness, and health; pedestrian navigation; autonomous robots; and virtual and augmented reality.

“Motion tracking in consumer devices has expanded rapidly from game interfaces and smartphones into many new Internet of Moving Things applications,” said Jérémie Bouchaud, director and senior principal analyst, MEMS & Sensors, at IHS. “As designers look to differentiate their products with motion, the availability of an IMU with an integrated motion processor and a complete software solution, accelerates time to market while ensuring the best trade-off between competing goals such as small size, long battery life and motion tracking accuracy.”

The AttitudeEngine processes 6-axis inertial data at a high rate internally and outputs to the host processor at a lower rate matching the application needs, eliminating the necessity for high-frequency interrupts. This allows the system processor to remain in sleep-mode longer, providing consumers longer battery life without any compromises in functionality or accuracy. The bundled XKF3 high-performance 9-axis sensor fusion algorithms combine inertial sensor data from the on-chip gyroscopes and accelerometers and data from an external magnetometer. The sensor fusion also includes background auto calibration that enables excellent performance in terms of accuracy, consistency, and fluidity. When combined with the XKF3 sensor fusion algorithms, the FIS1100 is the world’s first complete consumer inertial measurement unit with orientation (quaternion) specifications, featuring pitch and roll accuracy of ±3° and yaw accuracy of ±5°.

The FIS1100 uses Fairchild’s proprietary MEMS process, designed specifically for inertial sensors. The process features several design elements for optimal performance, size and robustness. These include a 60µm device layer with high-aspect ratio, through silicon via (TSV) interconnects and vertical electrodes, as well as a single die gyroscope and accelerometer with a unique dual vacuum design.

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI

Semiconductor capital expenditures (without fabless and backend) are expected to slow in rate, but continue to grow by 5.8 percent in 2015 (over US$66 billion) and 2.5 percent in 2016 (over $68 billion), according to the May update of the SEMI World Fab Forecast report. A significant part of this capex is fab equipment spending.

Fab equipment spending is forecast to depart from the typical historic trend over the past 15 years of two years of spending growth followed by one year of decline.  Departing from the norm, equipment spending could grow every year for three years in a row: 2014, 2015, and 2016 (see Table 1).

Table 1: Fab Equipment Spending by Wafer Size

Table 1: Fab Equipment Spending by Wafer Size

At the end of May 2015, SEMI published its latest update to the World Fab Forecast report, reporting on more than 200 facilities with equipment spending in 2015, and more than 175 facilities projected to spend in 2016.

The report shows a large increase in spending for DRAM, more than 45 percent in 2015. Also, spending for 3D NAND is expected to increase by more than 60 percent in 2015 and more than 70 percent in 2016. The foundry sector is forecast to show 10 percent higher fab equipment spending in 2015, but may experience a decline in 2016.  Even with this slowdown, the foundry sector is expected to be the second largest in equipment spending, surpassed only by spending in the memory sector.

A weak first quarter of 2015 is dropping spending for the first half of 2015, but a stronger second half of 2015 is expected. Intel and TSMC reduced their capital expenditure plans for 2015, while other companies, especially memory, are expected to increase their spending.

The SEMI data details how this varies by company and fab.  For example, the report predicts increased fab equipment spending in 2015 by TSMC and Samsung. Samsung is the “wild card” on the table, with new fabs in Hwaseong, Line 17 and S3.  The World Fab Forecast report shows how Samsung is likely to ramp these fabs into 2016. In addition, Samsung is currently ramping a large fab in China for 3D NAND (VNAND) production.   Overall, the data show that Samsung is will likely spend a bit more for memory in 2015 and much more in 2016.  After two years of declining spending for System LSI, Samsung is forecast to show an increase in 2015, and especially for 2016.

Figure 1 depicts fab equipment spending by region for 2015.

Figure 1: Fab Equipment Spending in 2015 by Region; SEMI World Fab Forecast Report (May 2015).

Figure 1: Fab Equipment Spending in 2015 by Region; SEMI World Fab Forecast Report (May 2015).

In 2015, fab equipment spending by Taiwan and Korea together are expected to make up over 51 percent of worldwide spending, according to the SEMI report.  In 2011, Taiwan and Korea accounted for just 41 percent, and the highest spending region was the Americas, with 22 percent (now just 16 percent).  China’s fab spending is still dominated by non-Chinese companies such as SK Hynix and Samsung, but the impact of Samsung’s 3D NAND project in Xian is significant. China’s share for fab spending grew from 9 percent in 2011 to a projected 11 percent in 2015; because of Samsung’s fab in Xian, the share will grow to 13 percent in 2016.

Table 2 shows the share of the top two companies drive a region for fab equipment spending:

Table 2: Share of Fab Equipment Spending of Top Two Companies per Region

Table 2: Share of Fab Equipment Spending of Top Two Companies per Region

Over time, fab equipment spending has also shifted by technology node.  See Figure 2, where nodes have been grouped by size:

Figure 2: Fab Equipment Spending by Nodes (Grouped)

Figure 2: Fab Equipment Spending by Nodes (Grouped)

In 2011, most fab equipment spending was for nodes between 25nm to 49nm (accounting for $24 billion) while nodes with 24nm or smaller drove spending less than $7 billion. By 2015, spending flipped, with nodes equal or under 24nm accounting for $27 billion while spending on nodes between 25nm to 49nm dropped to $8 billion.  The SEMI World Fab data also predict more spending on nodes between 38nm to 79nm, due to increases in the 3DNAND sector in 2015 and accelerating in 2016 (not shown in the chart).

When is the next contraction?

As noted above, over the past 15 years the industry has never achieved three consecutive years of positive growth rates for spending.  2016 may be the year which deviates from this historic cycle pattern.  A developing hypothesis is that with more consolidation, fewer players compete for market positions, resulting in a more controlled spending environment with much lower volatility.

Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase.