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By Paula Doe, SEMI

As if scaling to 7nm geometries and going vertical with FinFETs, TSVs and other emerging technologies wasn’t challenge enough, the emerging market for connected smart devices will bring more changes to the semiconductor sector. And then there’s 3D printing looming in the wings.

Sometime between 2009 and 2010, there was a point of inflection, where the number of connected devices began outnumbering the planet’s human population. And these aren’t just laptops, mobile phones, and tablets – they also include sensors and everyday objects that were previously unconnected, says Tony Shakib, Cisco Systems VP IoE Vertical Solutions, who will talk about the impact of these changes on the chip industry at SEMICON West this summer in San Francisco.  Connected “things” may reach 25 to 50 billion by the year 2020, he projects. These connections of people, process, data and things will create opportunities for new revenue streams, new options for competitive advantage, and new operating models to drive both efficiency and value, potentially driving massive gains in efficiency, business growth, and quality of life, he suggests. “But as we connect the unconnected, this will require that we think differently about business strategy and IT, analytics, security, and more.”

Source: Cisco

Source: Cisco

Chip makers will need to provide easy-to-use IoT security for startups

One big change: some 50 percent of Internet of Things (IoT) solutions by 2017 will probably come from startups, according to Gartner’s projections.  “Whatever the exact percentage, the increased role of new and small players in the IoT edge devices will be a fundamental paradigm shift from the big companies that have conventionally dominated the electronics industry, says Gowri Chindalore, head of Technology and Business Strategy for Microcontrollers business group at Freescale, who will speak on the issue at SEMICON West’s “Monetizing the IoT: Opportunities and Challenges” session.  “And these startups’ knowledge of security is often very low.  So as IC makers we need to make it easy for them to do.” He suggests the best solution is to offer on-chip security features, such as secure storage, cryptographic accelerators, and tamper resistance mechanisms, and supplement them with a software dashboard that makes it easy for the systems maker to set up and enable the desired features appropriate for the application.  Though the encryption technology is very complex, by using library programs and selling in volume, the actual cost can probably be reduced to a few cents per chip.

Security for the internet will also improve markedly within several years as passwords are replaced by personal transmitters that automatically send secure codes to websites at log on. Similarly, local aggregator devices at the edge for all the IoT devices in the house or the factory will serve as the security gateway to screen users or devices by transmitted codes or biometric sensors. “We need proliferation of these security features into even all the benign IoT gadgets in the house to protect the network, but consumers will be willing to pay the small extra cost for security — especially after a few more highly publicized instances of hacking,” he notes.

Designers combining more IP blocks face challenges in reliability and verification

The key challenge across the board from the design side for successful IoT devices will be figuring out how to combine the right component capabilities of sensors and memory and processing and connectivity and size and power for a compelling application, and then making the right tradeoffs in the architecture to make it all work, explains Steve Carlson, VP marketing, Cadence Design Systems, another speaker at SEMICON West. “IP blocks will be especially useful for smaller companies to add functions without necessarily having the in house expertise,” he notes.  But combining the blocks will challenge many users by dramatically new issues of isolating noisy analog parts from the digital as they add RF and sensors that they haven’t had to deal with before, and all at near-threshold and ultralow power.  That will mean more issues with variation and reliability, and verification will increasingly need to include both hardware blocks and software together, so emulation will become more critical, he notes.

Fabs may need to deal with more diverse processes, but may improve productivity

“The IoT will drive demand for more IC manufacturing across a wide range of technologies, from the most advanced logic process to high voltage devices and MEMS, all with diverse requirements,” says Peter Huang, VP Field Technical Support, TSMC North America, another speaker. He notes that MEMS and other emerging devices, ranging from micro-lenses for machine vision to batteries to power wireless sensors, will require some unique tools and processes, and will be less easily scalable than CMOS.  Material handling and the need for isolated lines will create additional challenges. “Heterogeneous integration will require 2.5D packaging for both form factor and cost,” he suggests. “And the real challenge will be high volume manufacturing and IP interface at the package level.”

Though manufacturing equipment is already highly automated and interconnected, the availability of hundreds of low-cost, connected sensors may bring opportunities to increase tool automation and productivity, he adds.

IoT graphic 2

Compact integration of multiple chip and sensor technologies for IoT devices will demand more sophisticated system- in-package technology.  The new Apple Watch has 30 components in its core S1 SiP, all packed on to a 26mm x 28mm motherboard and overmolded with a conventional IC packaging resin compound. (from Chipworks)

Progress on technology for 3D printing of tooling and components

Then there’s the disruptive potential for 3D printing some of the tooling and components all along the supply chain to speed time to market, allow more customization, reduce weight and simplify dealing with legacy parts — if the process can meet the required quality and cost. Phillip Trinidad, president of service provider Proto Café, who has worked with semiconductor sector players,  argues that progress in optimizing designs now means additive manufacturing is increasingly becoming suitable not just for prototyping, but also for production of specialty parts in performance plastics.

In addition, there’s recent progress in 3D printing for challenging metal industrial parts, which will be addressed at SEMICON West “Factory of the Future: Disruptive Technologies from IoT to 3D Printing — Impact on the Semiconductor Manufacturing Sector” session. Ryan Dehoff, lead for Metal Additive Manufacture at Oakridge National Laboratory, will provide an update on the current state of the art for printing in metal, while Wayne King, director of the Initiative for Accelerated Certification of Additive Manufactured Metals, will talk about the progress on speeding qualification of the additive metal parts by modeling and inline process monitoring and control.

Along with the regular coverage of next-generation scaling technology, SEMICON West 2015 will also address the impact of the Internet of Things and 3D printing on manufacturing technology across the semiconductor supply chain, as well as related developments in MEMS, emerging non-volatile memory technology, and automotive and biomedical applications. Please visit www.semiconwest.org.

Europe’s leading nanoelectronics institutes, Tyndall National Institute in Ireland, CEA-Leti in France and imec in Belgium, have entered a €4.7 million collaborative open-access project called ASCENT (Access to European Nanoelectronics Network). The project will mobilize European research capabilities at an unprecedented level and create a unique research infrastructure that will elevate Europe’s nanoelectronics R&D and manufacturing community.

ASCENT opens the doors to the world’s most advanced nanoelectronics infrastructures in Europe. Tyndall National Institute in Ireland, CEA-Leti in France and imec in Belgium, leading European nanoelectronics institutes, have entered into a collaborative open-access project called ASCENT (Access to European Nanoelectronics Network), to mobilise European research capabilities like never before.

The €4.7 million project will make the unique research infrastructure of three of Europe’s premier research centres available to the nanoelectronics modelling-and-characterisation research community.

ASCENT will share best scientific and technological practices, form a knowledge-innovation hub, train new researchers in advanced methodologies and establish a first-class research network of advanced technology designers, modellers and manufacturers in Europe. All this will strengthen Europe’s knowledge in the integral area of nanoelectronics research.

The three partners will provide researchers access to advanced device data, test chips and characterisation equipment.  This access programme will enable the research community to explore exciting new developments in industry and meet the challenges created in an ever-evolving and demanding digital world.

The partners’ respective facilities are truly world-class, representing over €2 billion of combined research infrastructure with unique credentials in advanced semiconductor processing, nanofabrication, heterogeneous and 3D integration, electrical characterisation and atomistic and TCAD modelling. This is the first time that access to these devices and test structures will become available anywhere in the world.

The project will engage industry directly through an ‘Industry Innovation Committee’ and will feed back the results of the open research to device manufacturers, giving them crucial information to improve the next generation of electronic devices.

Speaking on behalf of project coordinator, Tyndall National Institute, CEO Dr. Kieran Drain said: “We are delighted to coordinate the ASCENT programme and to be partners with world-leading institutes CEA-Leti and imec. Tyndall has a great track record in running successful collaborative open-access programmes, delivering real economic and societal impact. ASCENT has the capacity to change the paradigm of European research through unprecedented access to cutting-edge technologies. We are confident that ASCENT will ensure that Europe remains at the forefront of global nanoelectronics development.”

“The ASCENT project is an efficient, strategic way to open the complementary infrastructure and expertise of Tyndall, Leti and imec to a broad range of researchers from Europe’s nanoelectronics modelling-and-characterisation sectors,” said Leti CEO MarieNoëlle Semeria. “Collaborative projects like this, that bring together diverse, dedicated and talented people, have synergistic affects that benefit everyone involved, while addressing pressing technological challenges.”

“In the frame of the ASCENT project, three of Europe’s leading research institutes – Tyndall, imec and Leti – join forces in supporting the EU research and academic community, SMEs and industry by providing access to test structures and electrical data of state-of-the-art semiconductor technologies,” stated Luc Van den hove, CEO of imec. “This will enable them to explore exciting new opportunities in the ‘More Moore’ as well as the ‘More than Moore’ domains, and will allow them to participate and compete effectively on the global stage for the development of advanced nano-electronics.”

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under Grant Agreement No. 65384.

Over the past 15 years, strong growth in optoelectronics has been fueled by several different product categories at different times.  Laser transmitters for high-speed optical networks were a major growth driver before the “dot.com” implosion in 2001. Image sensors and lamp devices (primarily light-emitting diodes—LEDs) became star performers in the last decade, and more recently, laser transmitters have re-emerged as a major growth driver in optoelectronics.  IC Insights believes these three products will be key contributors to overall growth of the optoelectronics market through 2019 (Figure 1).

optoelectronics snapshot

 

Through 2019, IC Insights sees these three trends driving optoelectronics market growth:

•    High-brightness LEDs (HB-LEDs) have reached the luminous efficacy of fluorescent lights and are in a position to be a major factor in the $100 billion global lighting industry.  Since the end of the last decade, strong sales of HB-LEDs have gone into backlighting systems for cellphones, tablets, LCD TVs, and computer displays, but this growth has greatly eased with penetration rates reaching nearly 100 percent in these applications.  With production capacity growing, HB-LED suppliers are concentrating on cutting costs and improving the overall quality of light for general illumination products in homes, businesses, buildings, outdoor lighting, and other applications, such as automotive headlamps and digital signs. HB-LED 2014 -2019 CAGR forecast (sales):  9.7 percent.

•    CMOS image sensors have entered into another wave of strong sales growth as digital imaging moves into new automotive-safety systems, medical equipment, video security and surveillance networks, human-recognition user interfaces, wearable body cameras, and other embedded applications beyond camera phones and stand-alone digital cameras. CMOS image sensor 2014-2019 CAGR forecast (sales):  11.1 percent.

•    Fiber-optic laser transmitters will continue to be the fastest growing optoelectronics product category as network operators struggle to keep up with huge increases in Internet traffic, video streaming and downloads, cloud-computing services, and the potential for billions of new connections in the Internet of Things (IoT).  Laser transmitter 2014-2019 CAGR forecast (sales):  15.3 percent.

Suppliers of MEMS-based devices rode a safety sensing wave in 2014 to reach record turnover in automotive applications, according to analysis from IHS, the global source of critical information and insight.

Mandated safety systems such as Electronic Stability Control (ESC) and Tire Pressure Monitoring Systems (TPMS) – which attained full implementation in new vehicles in major automotive markets last year – are currently driving revenues for MEMS sensors. Those players with strong positions in gyroscopes, accelerometers and pressure sensors needed in these systems grew as well, while companies in established areas like high-g accelerometers for frontal airbags and pressure sensors for side airbags also saw success.

Major suppliers of pressure sensors to engines similarly blossomed – for staple functions like manifold absolute air intake and altitude sensing – but also for fast-growing applications like vacuum brake boosting, gasoline direct injection and fuel system vapor pressure sensing.

Bosch was the overall number one MEMS supplier with US$790 million of devices sold last year, close to three times that of its nearest competitor, Sensata (US$268 million). Bosch has a portfolio of MEMS devices covering pressure, flow, accelerometers and gyroscopes, and also has a leading position in more than 10 key applications. The company grew strongly in ESC and roll-over detection applications, and key engine measurements like manifold absolute pressure (MAP) and mass air flow on the air intake, vacuum brake booster pressure sensing and common rail diesel pressure measurement.

Compared to 2013, Sensata jumped to second place in 2014 ahead of Denso and Freescale, largely on strength in both safety and powertrain pressure sensors, but also through its acquisition of Schrader Electronics, which provides Sensata with a leading position among tire pressure-monitoring sensor suppliers.

While Sensata is dominant in TPMS and ESC pressure sensors, it also leads in harsh applications like exhaust gas pressure measurement. Freescale, on the other hand, is second to Bosch in airbag sensors and has made great strides in its supply of pressure sensors for TPMS applications.

Despite good results in 2014, Denso dropped two places compared to its overall second place in 2013, largely as a result of the weakened Yen. Denso excelled in MAP and barometric pressure measurement in 2014, but also ESC pressure and accelerometers. Denso has leadership in MEMS-based air conditioning sensing and pressure sensors for continuous variable transmission systems, and is also a supplier of exhaust pressure sensors to a major European OEM.

Secure in its fifth place, Analog Devices was again well positioned with its high-g accelerometers and gyroscopes in safety sensing, e.g. for airbag and ESC vehicle dynamics systems, respectively.

The next three players in the top 10, in order, Infineon, Murata and Panasonic, likewise have key sensors to offer for safety. Infineon is among the leading suppliers of pressure sensors to TPMS systems, while Murata and Panasonic serve ESC with gyroscope and accelerometers to major Tier Ones.

The top 10 represents 78 percent of the automotive MEMS market volume, which reached $2.6 billion in 2014. By 2021, this market will grow to $3.4 billion, a CAGR of 3.4 percent, given expected growth for four main sensors — pressure, flow, gyroscopes and accelerometers.  In addition, night-vision microbolometers from FLIR and ULIS and humidity sensors from companies like Sensirion and E+E Elektronik for window defogging will also add to the diversity of the mix in 2021.

Auto_MEMS_H1_2015_Graphic

DLP chips from Texas Instruments for advanced infotainment displays will similarly bolster the market further in future. More details can be found in the IHS Technology H1 2015 report on Automotive MEMS.

Read more: 

What’s next for MEMS?

Growing in maturity, the MEMS industry is getting its second wind

UPDATE:15 December 2015: Minor changes made to reflect correct ARM product nomenclature.

By Jeff Dorsch, Contributing Editor

Those 16-nanometer chips with FinFETs? Yesterday’s news. Taiwan Semiconductor Manufacturing wants you to know that they’re ready, willing, and able to help you design chips with 10-nanometer features.

The foundry presented Monday morning with its long-time partners, ARM Holdings and Synopsys, on its preparations for the 10nm process node.

20150608_072835 (640x360)

“The N10 design ecosystem is ready for customer design starts,” said Willy Chen, TSMC’s deputy director of Design & Technology Platform. He noted that TSMC has been collaborating with Synopsys for 15 years, while ARM and TSMC together offer “the most advanced ARM processor cores in the most advanced TSMC technology.”

Rob Aitken of ARM added, “10-nanometer enablement needs an ecosystem,” which the three companies are prepared to provide. He said ARM has “some cool things under development to make chip design faster,” without elaborating.

Haroon Gahur, principal design engineer at ARM, began the program by describing attributes of the ARM Cortex-A72 processor design, which he said consumes 75% less energy than previous ARM cores.

Joe Walston of Synopsys said ARM used the DC Graphical, IC Compiler I, and IC Compiler II tools from Synopsys in developing Cortex-A72, with signoff performed by PrimeTime SI. ARM’s Gahur noted that IC Compiler II provided a significant runtime advantage over its predecessor, IC Compiler I, by completing its run in five hours, compared with about 24 hours for IC Compiler I.

The program also featured Denny Liu, deputy general manager of Design Technology at MediaTek, who spoke of his company’s involvement with Synopsys and TSMC. He detailed MediaTek’s Helio X20, introduced last month, which is a tri-cluster mobile processor with 10 cores. MediaTek also employed IC Compiler II in designing the chip.

For all the 10nm talk, TSMC is hitting its stride with the N16FF+ process. Synopsys and TSMC announced Monday that the IC Compiler II place-and-route tool is certified for the foundry’s 16nm FinFET Plus process.

“The 16FF+ design flow is here,” TSMC’s Chen said.

The program finished with a presentation by Henry Sheng, group director of research and development at Synopsys, who noted that 90 percent of FinFET tapeouts are done with Synopsys place-and-route tools. Touting his company’s “healthy working relationship with TSMC,” Sheng said that emerging process nodes present a number of challenges, specifically new yield and manufacturing rules, process scaling, and new FinFET devices. Of FinFETs, he said, “These things are electrically different.”

Separately, Synopsys announced Sunday that it has agreed to acquire Atrenta, without disclosing financial terms. The transaction is expected to close this summer.

CEA-Leti announced today during the Design Automation Conference that seven partners have joined its new FD-SOI IC development program, Silicon Impulse, launched to provide a comprehensive IC technology platform that offers IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles.

The collaborative design platform for advanced processes includes a network of design services and facilities focused on accelerating development of products for today’s and tomorrow’s devices that require low-power use. These include energy-efficient computing systems, Ultra-Low-Power (ULP) Internet of Things (IoT) devices and robust and reliable applications in harsh environments. The platform leverages the competencies and expertise of the CEA-Leti and CEA-List institutes and Leti’s industrial partners, which comprise a wide spectrum of technical and application knowledge.

Silicon Impulse partners are major industrial players in the semiconductor ecosystem, world-class research centers and technology providers. Based on this strong foundation, Silicon Impulse will significantly reduce development time and speed industrialization, thus putting innovative companies at the cutting edge of energy-efficient system development and implementation. It will do this through a network of FD-SOI experts and access to a strong industrial supply chain.

Silicon Impulse partners:

CEA-Leti (coordinator)

CEA-List

STMicroelectronics

Dolphin Integration

CMP

Mentor Graphics

Cortus

Presto Engineering

 

In addition, CEA-Leti is planning to use its research & development license from ARM to demonstrate various energy-efficient processor implementations in FD-SOI for its IoT development platform. The FD-SOI ecosystem also includes Synopsys, with its rich portfolio of proven DesignWare IP products and EDA tools for the FD-SOI design community. Silicon Impulse is in discussion with Synopsys to join the program in order to further extend the program’s reach.

Launched by Leti in 2015, Silicon Impulse is designed to help innovative companies deal with the challenge of switching to new technologies and markets by augmenting both their knowledge of the supply chain and their skills to master the entire design process from ideas to products. To that end, Silicon Impulse will provide technical expertise, knowhow and access to advanced industrial, energy-efficient solutions to get innovators up to speed on the ecosystem of energy-efficient products by facilitating access to FD-SOI technology and manufacturing facilities.

“Leti has always concentrated on research that helps our partners adopt technology to become more competitive in their markets. Now with Silicon Impulse we provide a new service in collaboration with our industrial partners to help companies evaluate, design, prototype and launch new products,” said Marie-Noëlle Semeria, CEO of Leti. “From that foundation, Silicon Impulse will leverage the existing ecosystem to bring the full value chain from research, design solutions and industrialization services to high value-added products. This combination will concentrate through a single entry point all the necessary expertise and competencies to provide innovative companies from any sector with a one-stop-shop opportunity to build leading-edge, energy-efficient systems.”

As electronic devices become increasingly integrated into everyday activities, designing for energy efficiency becomes more important than ever for all mainstream sectors of industry. Embedded systems and particularly the IoT are key enablers in the market, and new entrants (startups, SMEs, large companies) drive innovation. By enabling integration of advanced processes – 28nm FD-SOI technology today – into IoT design and helping companies develop innovative products more rapidly, Silicon Impulse will foster leading-edge technologies and facilitate their adoption for manufacturing.

With the program’s flexible format, Silicon Impulse’s involvement can be limited to architectural consulting or extended to developing and delivering the whole system or anything in between. It can help innovators with their projects from concept through production hand-off. Companies can receive architectural advice and have their products shaped from a very high level, including a feasibility study and recommendations on how to implement the system. Leti and its partners also can provide unique IP and/or technology components such as foundation IP or more complex system level IP blocks, RF, NVM, N/MEMS, 3D components and any other advanced technology to shape a unique and advanced, yet manufacturable, product. At another level, Leti and List could provide embedded software to complete the whole product.

One key goal of the Silicon Impulse platform is to provide and ease silicon access. MPW shuttles are provided to open the doors to a wider set of users and projects. The goal is to enable innovators to test their ideas, especially mixed-signal, analog or RF technologies or any new IP that would require silicon validation in FD-SOI. This also provides an affordable platform for startups and other small companies to build their prototypes and run small volumes until they receive financing and/or demonstrate market traction to build their own mask set. The first 28nm FD-SOI MPW is planned for February 2016 to be processed at STMicroelectronics’ site in Crolles, which is near Grenoble.

A new, low pH, BTA free, noble-bond chemistry produced equivalent yield at substantially lower costs.

BY CHRISTOPHER ERIC BRANNON, Texas Instruments, Dallas, TX

The 2010 economic downturn affected many industries, semiconductor manufacturing notwithstanding. Many fabrication facilities had to layoff employees and curtail spending, all the while managing lower wafer output. This effect caused many semiconductor companies to rethink how they spend on resources. Everything was considered, from the cost of the wafers to the cost of the tool consumables and chemistries.

Texas Instruments (TI) copper chemical-mechanical planarization (Cu CMP) was no different. All spending had to be reduced and copper hillock defect had to
be eliminated. The CMP Team proposed developing a process based on the new third generation clean chemistry on the market for a number of economic and logistical reasons. The first rationale for this strategy was cost and second was time – most of the clean chemis- tries on the market were considerably cheaper than the current process of record (POR). CMP had also seen many defects due to via-to-via shorts caused by Cu hillocking (localized Cu protrusion into the above interlayer dielectric; see FIGURE 1).

FIGURE 1. TEM of copper hillocks [1].

FIGURE 1. TEM of copper hillocks [1].

A successful Cu cleaning CMP process

There were two key reasons that TI succeeded in developing a Cu cleaning process: detailed engineering work and strong vendor support. Process development went through four generations of refinement before it was ready for high volume manufacturing. The first version focused on new clean chemistry improvements such as third generation low pH, high acid clean chemistry and an array of design of experiments (DOE) continuous improvement through optimization of the process controls and equipment modification followed in the second. The third generation attempted to adapt an existing Mirra-Desica process using a previous qualified process. A final successful attempt was made during the fourth cycle to develop a lower cost, higher throughput multi-copper platen cleaning process using a commercial chemistry from Air Products, COPPEREADY®CP72B. This paper will discuss the work that went into building TI’s successful Cu cleaning CMP process.

TI Cu CMP

Neutral pH clean chemistries using Benzotriazole (BTA) were the first generation application on most Cu CMP dual damascene back end of the line process at TI. This was dependent on using dry-in wet-out Cu CMP AMAT tools with spray acid Vertec hoods for cleaning and drying. It was also very high in cost and low in consumable life compared to most conventional CMP clean process (e.g. Tungsten, STI, Oxide). The TI POR was no different, a first generation Cu clean using three different chemistries, BTA, Electra Clean and ESC774TM. These chemistries were very expensive to use and were not very efficient at cleaning or passivating the polished copper surface. They were able to passivate the copper surface but were prone to leave many types of incompatible carbon residue defects on the wafers. Cu hillocking was very prevalent with this type of cleaning solution and via-to-via shorts in the back end of the line (BEOL) were the top defect pareto for TI.

Clean chemistry identification

To reduce the time to develop a new Cu CMP clean process, most of the development cycle focused on Cu cleans leveraging a Mirra-Desica DIDO Cu polishing process using existing pads, conditioning pucks, and heads. Early on, it was decided that to achieve maximum throughput, the wafers would need to be processed through the tool’s onboard scrubber and dry station as quickly as possible. With time running out, the Cu CMP team had contacted the major players in Cu clean chemistry to obtain their specific information and prepare a white paper screening to determine the correct path. The four candidates were evaluated on chemistry type, makeup, pH, passivation (BTA), cost, and compatibility to our current Cu and barrier slurry. Two of the chemistries fit the bill for the criteria and were selected for further testing. Chemistry 1 was a novel approach for Cu CMP and was from our current clean chemistry vendor, Chemistry 2 was similar to the current TI process of record.

The initial criteria used to judge the chemistries were blanket test wafer performance (Cu, Teos, Ta, and Nitride): etch rate, passivation, cleaning tunability via recipe parameter windowing, and defectivity. Experimental designs were run on the basic process controls with these chemistry’s with respect to the polish process: carrier speed, table speed, down-force, carrier position, carrier oscillation, and chemical flow. Both cleans performed well on the blanket experiments and were advanced to short loop, patterned wafer tests. These patterned wafer tests were used to study product behavior in the polisher and brush cleaner. A significant amount of time was spent adjusting recipe parameters to eliminate defects. The team contacted both vendors to do lifetime experiments with consumables at their facilities. The data that was collected revealed many issues with each candidate, one more so than the other (FIGURE 2).

FIGURE 2. Charts of Cu CMP defects showing effects of new clean chemistry.

FIGURE 2. Charts of Cu CMP defects showing effects of new clean chemistry.

Chemistry A was a second generation Cu clean that had high pH but had chemical additives that would aid in cleaning, still a very basic approach to wafer cleaning. The overall defectivity was sufficient on the product test wafers but would degrade after a short time window after polish. It also had to be paired with another chemistry to achieve the same Cu passivation as the POR. This chemistry was disqualified due to this reason.

Chemistry B is a third generation Cu clean that had low pH (about ~2.1) and it is BTA-free, unlike any other Cu cleans on the market at that time. This chemistry is an organic acid blend, which helps ionize Cu2O and CuO to form water and soluble Cu complex, used for passivation. This forms a strong bond with the Cu to make the surface nobel. The low pH helps to dissolve the surface defects resulting in a step function decrease in defectivity compared to baseline (see Figure 2). The chemistry was also scalable, depending on concentration making cost of ownership low. This chemistry was selected for qualification at TI Cu CMP.

Vendor support

TI’s internal polishing engineering staff was augmented with exceptional support from several consumable vendors during development. Together TI engineers developed proprietary and patent-pending technologies to enhance the Mirra Desica cleaner performance on Cu BEOL CMP. TI also benefited from strong relationships with its contact clean brush suppliers. Rippy was instrumental in brush evaluations and consul- tation on process developments. To improve the tool’s performance, DOW was pivotal in adding additional functionality to the process through end of life evaluations. Perhaps most important of all relationships that developed was with Air Products, who provided an invaluable education into Cu cleaning process development.

Solving defect issues

During process development, TI engineers encountered several defect related issues. Some issues like photo-induced corrosion were resolved quickly after some technical research. There were two others that took more troubleshooting: carbon residue defects and Cu hillock formation.

The presence of gross surface defects, like carbon residue is an obvious yield killer. The Cu CMP Engineers come to the conclusion through EDX (Energy-dispersive X-ray spectroscopy) and much lab analysis that the current Cu slurry still had traces of BTA in it and were causing this residue defect to form on the wafers after polish. Many DOE later determined that extending the clean chemistry buff polish would eliminate this defect.

With residue defects effectively eliminated, the next major technical challenge was Cu hillock formation. TI had been experiencing higher defectivity due to back end of the line via to via shorts on the previous Cu CMP clean chemistry process. It was understood that the formation of Cu hillocks were the cause for this signature. To solve this problem, a completely different wafer cleaning chemistry was needed to passivate the copper surface. TI Cu CMP Engineers looked for one that did not use BTA or other high pH chemistries, but, would coat the wafer surface and not allow native oxides to grow on the Cu. The new chemistry (CoppeReady®CP72B) proved to form a nobel bond with the Cu (CuO2) and eliminated hillock growth formation, thereby reducing via-to-via shorts (see FIGURE 3).

FIGURE 3. Metal 1 via etch contact pitting chart (dark vias induced by copper hillock).

FIGURE 3. Metal 1 via etch contact pitting chart (dark vias induced by copper hillock).

Further process development

One of the last stages of development on the new process was a project to develop a faster through-put process. Although this work was successful, it highlights some of the challenges in pursuing this type of strategy. The motivation for this work was to dramatically boost the throughput and to further cut process expense. The POR process was limited by the cleaner and was much slower causing higher cost and higher wafer-per-hour rates. To maximize throughput, the new process would have two components: speed up the on board cleaner, brush box 1&2 throughput, as well decrease the platen 2&3 process times but include a clean chemistry buff. Because of the high down forces employed to achieve a flat removal profile, the Cu polishing component of this work, platen 1, was surprisingly fast but was the intended bottle neck. These changes allowed for a 10 percent increase in overall wafer through put compared to the baseline process. This had an alternate effect on the Cu polish process. TI’s current Cu slurry is thermally driven, with making platen 1 the bottle neck it kept that platen at one constant temperature throughout the lot, causing the overall end point times (EPD) to be reduced and streamlined. This further increased the tools throughput by 2 percent and reduced wafer to wafer EPD variation down to 2 to 3 seconds; previous was 10 to 12 sec between wafers (see FIGURE 4).

FIGURE 4. Cu CMP end point charts, variation reduction, clean chemistry and throughput enhancements.

FIGURE 4. Cu CMP end point charts, variation reduction, clean chemistry and throughput enhancements.

Benchmarking performance

For initial qualification and benchmarking, TI installed and setup the best known method (BKM) Cu polishing process on an Applied Materials Mirra-Desica. To
bring the new clean process into production, Cu Polish engineers needed to demonstrate equivalent or better yield between the two competing process. The new clean chemistry needed to be tested for EM (electro migration), which is a stress test of Cu interconnects between two metal lines. This test had to be outsourced to a third party company that specializes in oven-baking stress tests (FIGURE 5). After extensive electrical and yield testing, the new clean process was fully released. Sample yield comparisons consistently demonstrated that the performance is equivalent to slightly better and the new process has higher through-put (~12 percent). The chemical costs (dilute 60 to 1 CP72B®) are 68 percent less per wafer pass than the competing process. The pad/ conditioner life had increased by 13 percent from the previous process due to thermal driven Cu slurry through put modification (FIGURES 6 AND 7).

FIGURE 5. Electromigration (EM) stress test, new clean vs baseline.

FIGURE 5. Electromigration (EM) stress test, new clean vs baseline.

FIGURE 6. Sample availability with the new clean chemistry improvements.

FIGURE 6. Sample availability with the new clean chemistry improvements.

FIGURE 7. Clean chemistry cost over time in Cu CMP in terms of lots processed.

FIGURE 7. Clean chemistry cost over time in Cu CMP in terms of lots processed.

Conclusion

TI engineers developed a Cu CMP cleaning process using new third generation low pH Cu chemistry. Despite the tool’s many limitations, the engineering staff successfully delivered an integrated process capable of producing equivalent yield at substantially lower costs over the best alternative method. There were undoubtedly challenges along the way, only a fraction of which have been described in this paper. By leveraging an existing deep reservoir of engineering, maintenance, and operational talent, an existing and efficient supply chain, and the outstanding support of numerous vendors, TI Polish module was able to realize its goal of making efficient use of its assets to achieve a competitive advantage.

References

1. Tsung-Kuei Kanga, and Wei-Yang Choub Author. ‘Avoiding Cu Hillocks during the Plasma Process’

Journal of The Electrochemical Society, 151

CHRISTOPHER ERIC BRANNON is a TI Cu CMP Manufacturing Engineering, Texas Instruments, Dallas, TX.

SEMI today announced the update of its World Fab Forecast report for 2015 and 2016. The report projects that semiconductor fab equipment spending (new, used, for Front End facilities) is expected to increase 11 percent (US$38.7 billion) in 2015 and another 5 percent ($40.7 billion) in 2016. Since February 2015, SEMI has made 282 updates to its detailed World Fab Forecast report, which tracks fab spending for construction and equipment, as well as capacity changes, and technology nodes transitions and product type changes by fab.   

Capital expenditure (capex without fabless and backend) by device manufacturers is forecast to increase almost 6 percent in 2015 and over 2 percent in 2016. Fab equipment spending is forecast to depart from the typical historic trend over the past 15 years of two years of spending growth followed by one of decline.  For the first time, equipment spending could grow every year for three years in a row: 2014, 2015, and 2016.

The SEMI World Fab Forecast Report, a “bottoms up” company-by-company and fab-by-fab approach, lists over 48 facilities making DRAM products and 32 facilities making NAND products. The report also monitors 36 construction projects with investments totaling over $5.6 billion in 2015 and 20 construction projects with investments of over $7.5 billion in 2016.  

According to the SEMI report, fab equipment spending in 2015 will be driven by Memory and Foundry ─ with Taiwan and Korea projected to become the largest markets for fab equipment at $10.6 billion and $9.3 billion, respectively. The market in the Americas is forecast to reach $6.1 billion, with Japan and China following at $4.5 and $4.4 billion, respectively. Europe/Mideast is predicted to invest $2.6 billion. The fab equipment market in South East Asia is expected to total $1.2 billion in 2015.

Learn more about the SEMI World Fab Forecast and plan to attend the SEMI/Gartner Market Symposium at SEMICON West 2015 on Monday, July 13 for an update on the semiconductor supply chain market outlook. In addition to presentations from Gartner analysts, Christian Dieseldorff of SEMI will present on “Trends and Outlook for Fabs and Fab Capacity” and Lara Chamness will present on “Semiconductor Wafer Fab Materials Market and Year-to-Date Front-End Equipment Trends.”   

Fab Equipment Spending
(for Front-End Facilities, includes new, used, in-house)

 

2014

(US$B)

2015

(US$B)

Year-over-Year

Americas

7.8

6.1

-22%

China

4.1

4.4

10%

Europe and Mideast

2.2

2.6

18%

Japan

3.8

4.5

17%

Korea

7.4

9.3

27%

SE Asia

1.1

1.2

2%

Taiwan

8.5

10.6

25%

Total

34.9

38.7

11%

Source: SEMI World Fab Forecast Reports (May 2015)Totals may not add due to rounding

The Semiconductor Industry Association (SIA) announced worldwide sales of semiconductors reached $27.6 billion for the month of April 2015, 4.8 percent higher than the April 2014 total of $26.3 billion and 0.4 percent lower than last month’s total of $27.7 billion. The Americas market posted double-digit growth compared to last year, leading all regions. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects steady market growth for the next three years.

“Year-to-year semiconductor sales increased for the 24th straight month in April, thanks largely to continued growth in the Americas and Asia Pacific regional markets,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The global industry has posted higher sales through April than at the same point in 2014, and we expect continued growth for the rest of 2015 and beyond.”

Regionally, year-to-year sales increased in the Americas (12.2 percent), China (9.9 percent), and Asia Pacific/All Other (5.2 percent), while sales decreased compared with last year in Europe (-5.6 percent) and Japan (-10.7 percent). Compared with last month, sales were up in the Asia Pacific/All Other (2.3 percent) category, but down in Japan (-0.2 percent), China (-0.7 percent), Europe (-2.3 percent), and the Americas (-3.4 percent).

Additionally, SIA today endorsed the WSTS Spring 2015 global semiconductor sales forecast, which projects the industry’s worldwide sales will reach $347.2 billion in 2015, a 3.4 percent increase from the 2014 sales total. WSTS projects year-to-year increases for 2015 in Asia Pacific (7.0 percent) and the Americas (3.7 percent), with decreases projected for Europe (-3.6 percent) and Japan (-9.5 percent).

Beyond 2015, the industry is expected to grow at a modest pace across all regions. WSTS forecasts 3.4 percent growth globally for 2016 ($358.9 billion in total sales) and 3.0 percent growth for 2017 ($369.6 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

April 2015
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 5.81 5.61 -3.4%
Europe 2.96 2.89 -2.3%
Japan 2.54 2.54 -0.2%
China 7.83 7.78 -0.7%
Asia Pacific/All Other 8.58 8.78 2.3%
Total 27.72 27.60 -0.4%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 5.00 5.61 12.2%
Europe 3.06 2.89 -5.6%
Japan 2.84 2.54 -10.7%
China 7.08 7.78 9.9%
Asia Pacific/All Other 8.35 8.78 5.2%
Total 26.34 27.60 4.8%
Three-Month-Moving Average Sales
Market Nov/Dec/Jan Feb/Mar/Apr % Change
Americas 6.51 5.61 -13.8%
Europe 2.95 2.89 -2.0%
Japan 2.62 2.54 -3.0%
China 8.07 7.78 -3.6%
Asia Pacific/All Other 8.40 8.78 4.5%
Total 28.54 27.60 -3.3%

By Lara Chamness, Industry Research and Statistics, SEMI

As the fabless business model has transformed the semiconductor manufacturing landscape, Taiwan and South Korea have undeniably grown into key semiconductor producing regions. However, it should be noted that North America is home to Intel, Texas Instruments, Micron, GLOBALFOUNDRIES, Freescale, Fairchild, Microchip, ON Semiconductor, significant operations of Samsung, and other manufacturers.  As a result, North America accounts for 15 percent (without discretes) of the global total installed fab capacity in 2014 according to the SEMI Fab database.

SEMI graphic 1--2014_Global_Fab_Capacities_0

Due to the presence of leading device manufacturers, North America represents a significant portion of the new equipment market; for the last two years, North America was the second largest market for semiconductor manufacturing equipment. In 2011, North America was the largest market for new equipment. While spending is expected to decline in the region this year, it is anticipated that device manufacturers in North America will still spend about $7 billion on new equipment this year.

SEMI graphic 2--Regional_Equipment_Markets_2010_2014

With such a large installed fab base, North America also claims a significant portion of the wafer fab materials market.  Comparing global fab capacity to global wafer fab market share, North America represents 18 percent of the Wafer Fab Materials market compared to 15 percent of global fab capacity. This is due to the advanced device manufacturing that occurs in the region, which requires more advanced materials which fetch higher average selling prices. The same phenomenon occurs in Taiwan and Europe as well.

SEMI graphic 3--Regional_Wafer_Fab_Materials_Markets

Even though the equipment market is expected to decline in North America this year, the Wafer Fab Materials Market is expected to increase amodest 3 percent. This is due to equipment purchased and installed last year becoming operational. The semiconductor manufacturing market in North America is still very much alive and innovating, whether it be for advanced manufacturing or chip design, companies in North America have proven adept at evolving with the industry.

Plan to attend the SEMI/Gartner Market Symposium at SEMICON West 2015 on Monday, July 13 for an update on the semiconductor market outlook.