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IC Insights will release its Update to the 2015 IC Market Drivers report in June. The Update includes revisions to IC market conditions and forecasts for the 2015 2018 automotive, smartphone, personal computer and tablet markets, as well as an update to the market for the Internet of Things. This bulletin reviews IC Insights’ 2015 unit shipment forecast for total personal computing unit shipments.

Five years ago, touchscreen tablets began pouring into the personal computing marketplace, stealing growth from standard personal computers and signaling the start of what has been widely described as the “post-PC” era. Led by Apple’s iPad systems, tablet shipments overtook notebook PCs in 2013, and it appeared as if they would surpass total personal computer units (counting both desktop and portable systems) by 2016. However, that scenario no longer seems possible after tablet growth lost significant momentum in 2014 and then nearly stalled out in the first half of 2015 due to the rise in popularity of large-screen smartphones and the lack of interest in new tablets that do not add enough features or capabilities to convince existing users to buy replacements. Consequently, IC Insights has downgraded its forecast for the overall personal computing market, including much lower growth in tablets and continued weakness in standard PCs (Figure 1).

The updated forecast shows total personal computing unit shipments (desktop PCs, notebook PCs, tablets, and Internet/cloud-computing “thin-client” systems) dropping 1 percent in 2015 to 545 million. In the original forecast of the 2015 IC Market Drivers report (MD15), total personal computing system shipments were projected to rise 8 percent in 2015 to 609 million units, followed by a 10 percent increase in 2016 to 670 million. The revised outlook cuts the compound annual growth rate (CAGR) of personal computing unit shipments to 2.1 percent between 2013 and 2018. Total personal computing system shipments are now projected to reach 578 million in 2018.

Worldwide shipments of keyboard-equipped standard PCs (desktops and notebooks) peaked in 2012 at 345 million, but they are expected to decline by a CAGR of -0.5 percent in the 2013-2018 timeperiod. In the updated outlook, tablets are projected to account for 45 percent of total systems sold in 2018 (259 million units) versus the MD15’s original forecast of 57 percent (423 million) that year. Further into the future, tablets are now expected to account for about half of personal computing system shipments with the remaining units being divided between standard PCs and Internet/cloud-centric platforms.

IC Insights June Report

Figure 1

 

Additional details on the IC market for medical and wearable electronic is included in the 2015 edition of IC Insights’ IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits.  This report examines the largest, existing system opportunities for ICs and evaluates the potential for new applications that are expected to help fuel the market for ICs.

IC Insights will release its May Update to the 2015 McClean Report later this month.  This Update includes a discussion of the history and evolution of IC industry cycles, an update of the capital spending forecast by company, and a look at the top 25 1Q15 semiconductor suppliers (the top 20 1Q15 semiconductor suppliers are covered in this research bulletin).

The top 20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 1Q15 is shown in Figure 1.  It includes seven suppliers headquartered in the U.S., four in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and four fabless companies.  It is interesting to note that the top four semiconductor suppliers all have different business models. Intel is essentially a pure-play IDM, Samsung a vertically integrated IC supplier, TSMC a pure-play foundry, and Qualcomm a fabless company.

IC Insights includes foundries in the top 20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  As shown in the listing, the foundries and fabless companies are identified.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

It should be noted that not all foundry sales should be excluded when attempting to create marketshare data. For example, although Samsung had a large amount of foundry sales in 1Q15, some of its foundry sales were to Apple.  Since Apple does not resell these devices, counting these foundry sales as Samsung IC sales does not introduce double counting.

Figure 1

Figure 1

Overall, the top-20 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

In total, the top 20 semiconductor companies’ sales increased by 9 percent in 1Q15/1Q14 (6 percent excluding the foundries), three points greater than the total worldwide semiconductor industry growth rate.  Although, in total, the top-20 1Q15 semiconductor companies registered a 9 percent increase, there were six companies that displayed >20 percent 1Q15/1Q14 growth.  Nine companies had sales of at least $2.0 billion in 1Q15.  As shown, it took just over $1.1 billion in quarterly sales just to make it into the 1Q15 top-20 semiconductor supplier ranking.

There were two new entrants into the top 20 ranking in 1Q15—Japan-based Sharp and Taiwan-based pure-play foundry UMC, which replaced U.S.-based AMD and Nvidia.  AMD had a particularly rough 1Q15 and saw its sales drop 26 percent year-over-year.  It currently appears that AMD’s 2013 restructuring and new strategy programs to focus on non-PC end-use segments have yet to pay off for the company (in addition to its sales decline, AMD lost $180 million in 1Q15 after losing $403 million in 2014).

Although Intel’s sales were flat in 1Q15, and it believes its 2015 sales will be flat with 2014, it remained firmly in control of the number one spot.  There were, however, some significant changes in the remainder of the top 10 ranking.

SK Hynix continued its ascent up the semiconductor company rankings that started a few years ago and moved into 5th place in 1Q15, displacing Micron.  With Qualcomm’s sales hitting a soft patch and SK Hynix continuing to gain share in the memory market, IC Insights believes that the company could move past Qualcomm into the fourth spot when the full-year sales totals for this year are tallied.

While MediaTek’s growth has slowed somewhat from its torrid pace over the past few years, the company posted a year-over-year sales increase of 12 percent to move into the top 10.  IC Insights believes that MediaTek will remain in this position in the full-year 2015 ranking.

Although Sharp as a whole is having a difficult time, its semiconductor group, which represents only about 14 percent of the company’s corporate sales, posted a whopping 62 percent growth rate (an 88 percent increase in yen), the best 1Q15 sales increase of any top-20 semiconductor supplier.  This sales surge was almost entirely due to the company’s success in the CMOS image sensor market.

As would be expected, given the possible acquisitions and mergers that could occur this year (e.g., NXP/Freescale, GlobalFoundries/IBM’s IC group, etc.), as well as any new ones that may develop, the top 20 semiconductor ranking is likely to undergo a tremendous amount of upheaval over the next couple of years as the semiconductor industry continues along its path to maturity.

By Paula Doe, SEMI

Ever growing volumes of data to be stored and accessed, and advancing process technologies for sophisticated control of deposition and etch in complex stacks of new materials, are creating a window of opportunity for an emerging variety of next-generation non-volatile memory technologies.  While flash memory goes vertical for  higher densities, resistive RAM and spin-transfer magnetic RAM  technologies are moving towards commercial manufacture for  initial applications in niches that demand a different mix of speed,  power and endurance than  flash or SRAM. This article delves into some of the topics that will be addressed at SEMICON West 2015.

Micron: Memory Needs to go Vertical

“Memory is going through a transformation, making it an exciting time to be in the sector, with both emerging opportunities and new challenges,” notes Naga Chandrasekaran, Micron Technology VP of process R&D, who will keynote the next-generation memory program at SEMICON West 2015.  As new applications in the connected world drive demand for increased storage, bandwidth, and smart memory, and as conventional planar memory scaling faces more challenges, memory suppliers across the industry face a transformation, requiring new emerging memory types and a transition from planar to vertical technology.

“Memory needs to go vertical to meet growing demands placed on performance, and that means a new set of process and equipment requirements,” says Chandrasekaran.  Scaling the vertical 3DNAND structures is no longer limited by the lithography, but instead is driven by the capability of the etch, film and characterization processes.  “Metrology and structure/defect characterization is a holdup for the entire sector, which is slowing down the cycle time for development,” he notes. “In addition, there are challenges in materials, structural scaling, equipment technology, and manufacturability on the new roadmap that need to be resolved.”

Everspin Targets ST-RAM on GLOBALFOUNDRIES’ 40nm 300mm Process in a Year

Everspin Technologies’ recently introduced 64Mb spin transfer torque MRAM makes a big jump in density over the company’s earlier 16Mb device, as switching the magnetization by a current of electrons of aligned spin allows much better selectivity than applying a magnetic field.  Manufacturing these spin-transfer devices has traditionally been a challenge, but the company claims it sees a clear roadmap to continue to increase the density. “We’re squeezing a 64Mb device on 90nm silicon out of the quarter-micron process equipment in our fab,” says VP of manufacturing Sanjeev Aggarwal, who will give an update on the technology at SEMICON West.  The company is in the process of transferring the technology to a 40nm process on 300mm wafers at partner GLOBALFOUNDRIES in the next year, to significantly reduce the cell size and spacing.

Aggarwal notes that the layers in the magnetic stack of the spin-transfer torque device (ST RAM) are similar in thickness to those of the earlier magnetic-field switched MRAM devices, which have already shipped some  50 million units. In the 28nm version of the ST-RAM, targeted for a couple of years out, the company plans to switch from an in-plane to a perpendicular structure, which will significantly improve efficiency to cut power consumption by an order of magnitude, though the material stack and processing will remain very similar.

Current deposition tools can provide the layer uniformity required for the many ultrathin layers of these magnetic stacks, and etching technology being developed with a vendor for cleanly removing these non-volatile magnetic material looks promising for 40nm, says Aggarwal. Key is the company’s IP for depositing the tunnel barrier MgO and for stopping the etch uniformly on the tunnel barrier when etching the magnetic stack. “These deposition and etch technologies should extend to 1Gb without much change, though at 16Gb we may need something new,” he adds. “In the next several years we will need help from vendors on better ways to clean up the etch residue, such as by ion milling after RIE, or encapsulating the stack to protect it before the next round of etching.”

Demand for the 64Mb ST-RAM is coming from buffer storage applications, such as high-end enterprise-class solid state drives, where an array of the fast-writing, non-volatile chips holds the data until it can be more permanently filed and stored, and where the high volumes of data require better endurance than flash,  reports Terry Hulett,  Evergreen VP Systems Engineering and GM Storage Solutions.  “As our products increase in density, we expect to serve the same function for bigger storage systems, like a whole rack of solid state drives,” he projects. The company also targets applications for potential power savings for the instant-on persistent memory, such as powering off the display buffer between every refresh cycles for mobile devices, or shutting down the server between operations.

Both Sanjeev Aggarwal (Everspin) and Naga Chandrasekaran (Micron Technology) will update SEMICON West attendees on the state of these emerging memory technologies in a TechXPOT.   In addition, Wei D. Lu (Crossbar), Robert Patti (Tezzaron), and Jim Handy (Objective Analysis) will provide analysis and updates at the July 14 event in San Francisco:

Crossbar Aims for Embedded ReRAM IP Blocks from Foundry by End of Year

ReRAM suppliers, meanwhile, argue that their technology potentially offers better prospects for scaling and lower costs than either flash or spin-based MRAM, although it is still a ways from a commercial volume process.   Crossbar Co-founder and chief scientist Wei Lu, who will also speak at SEMICON West, says the company plans to deliver its ReRAM technology to strategic partners as an IP block for embedded non-volatile memory on logic chips from a leading-edge manufacturing foundry by the end of the year.  The company’s approach stores data by changing the resistance by forming a conductive metallic bridge through a resistive layer of amorphous silicon sandwiched between two electrode layers.

Lu says the devices are being made with two-mask steps on top of the CMOS transistors in a leading foundry.  Key to improving performance to commercial levels and achieving very dense crossbar arrays, he notes, is the addition of a high speed selector device on top of the memory layer.  This layer blocks unwanted sneak currents at low voltages and turns on at the threshold level to enable formation of the conduction bridge. “It’s like a volatile RAM stacked on top of the ReRAM, with nanosecond recovery time,” he explains. “This brings the on/off selectivity up to 108.”

Initial target market is chip makers who want to embed nonvolatile memory directly in the logic fab, for low-power applications like the IoT, with faster speed and higher endurance than flash.  But ultimately the company targets the bigger market of stand-alone enterprise data storage with lower read and write latencies.  “We expect to offer Gigabit-level density at faster speed than NAND flash by around 2017,” claims Lu.  He figures ReRAM and STT RAM will both find their place in the more diverse memory market of the future, with SST RAM offering better endurance, and ReRAM offering higher density and lower cost.

Tezzaron Reports High ReRAM Yields from Repair and Remapping through Multilayer Stack

Tezzaron Semiconductor takes a different approach to ReRAM, storing data by moving oxygen vacancies instead of metal ions across the thin layers to change resistance.  CTO Robert Patti, another SEMICON West speaker, credits the Tezzaron fab’s ALD technology for the tight control of layer uniformity required to build its 16-tiers of ReRAM cells on top of a CMOS transistor tier from another foundry.  Controlling the chemistry of the layering and the reaction is a challenge, but the tiers allow dynamic repair and remapping of defective cells, which Patti claims can enable yields of up to 98%.  “The possibility to repair across the vertical structure makes defect density less of an issue, and lets us deal with materials and processes that are less mature,” he notes.

Patti says his company’s aerospace/military customers, who need a non-volatile option with better endurance than flash memory, will likely move to ReRAM within a couple of years.  Server makers are also starting to look at the potential for adding a new intermediate level of memory, between the solid state disk and the DRAM, which could potentially significantly improve server performance in analyzing big data by holding big chunks of data for faster access at lower power. It might also reduce system-level costs, although it will require changes in operating system architecture to use it effectively, and sophisticated programming algorithms to manage the memory to limit wear.  Demands on the intermediate storage memory should be limited enough that the ReRAM target endurance of 10cycles should be sufficient, though it remains lower than DRAM’s 1015.  If ReRAM endurance reaches 1012 cycles, the nonvolatile, instant-on memory could become a viable replacement for mobile memory, Patti suggests.

Vertical NAND is appealing because it’s more familiar, which has probably delayed interest in ReRAM.  But ReRAM has a smaller cell size so may ultimately be easier to scale and more cost effective,” argues Patti.

Costs Remain the Challenge

“The only thing that ultimately matters in memory is cost,” argues Objective Analysis analyst Jim Handy, another speaker, pointing out that the target aerospace and enterprise storage applications remain small markets, and volumes are not high enough yet to build up deep understanding of the new materials used, so there will be bumps in the road to come.  But as costs come down as MRAM and ReRAM scale to higher densities, he expects them to gradually take over more mainstream applications, starting with the highest cost memories, so first SRAM (especially SRAM with battery backup), then NOR flash, DRAM and finally NAND flash — perhaps by ~2023.  “We have been predicting that 2017 is the earliest we’ll see significant penetration of 3D NAND into the planar NAND market,” he notes. “And now that some suppliers are saying it will be 2017, it makes me think it may be longer.”

On July 14, all of these industry leaders will present at SEMICON West at the emerging memory technologies TechXPOT (www.semiconwest.org/node/13781). Register now and save $100 off registration.

In 2014, the MEMS sector represented an $11.1B business for Si-based devices. According to Yole Développement (Yole) latest MEMS report “Status of the MEMS Industry”, the MEMS industry is preparing to exceed $20B by 2020.

“We have seen different market leaders in the past and the competition is still very open,” said Jean-Christophe Eloy, President & CEO, Yole. “But 2014 will be remembered for the emergence of what could be a future “MEMS Titan”: Robert Bosch (Bosch),” he added.

Under this new analysis entitled, “Status of the MEMS Industry” report Yole proposes a deep understanding of the MEMS markets trends and players dynamics. The More than Moore market research and strategy consulting company announces its 2014 MEMS manufacturers and foundries ranking and proposes an overview of the future game-changers including new devices, disruptive technologies, 300mm wafers, sensor fusion and new markets.

mems market forecast

Bosch’s MEMS revenues have increased by 20 percent to top $1.2B, driven by consumer sales. STMicroelectronics’ revenue is thus now lagging $400M behind. Compared to 2013, the top five companies remain unchanged and together they earn $3.8B, around a third of the total MEMS business. However, Bosch’s dominance is clear, as its revenues now account for around one-third of that figure. Among the 10 or so MEMS titans that are currently sharing most of the MEMS market, Yole distinguishes the “Titans with Momentum” from the “Struggling Titans”

Titans with Momentum group includes Bosch, InvenSense and others.

“Bosch’s case is particularly noteworthy as it is today the only MEMS company in dual markets – namely automotive and consumer – that has the right R&D/production infrastructure,” said Dr Eric Mounier, Senior Technology & Market Analyst, MEMS devices & Technology at Yole.

STMicroelectronics, Texas Instruments, Knowles, Denso and Panasonic are part of the second group, “Struggling Titans.” These companies are currently struggling to have an efficient value growth engine.

A third family is the upcoming “Baby Titans” like Qorvo and Infineon that have grown significantly in the past couple of years and could become serious MEMS players.

Yole has analyzed the three “Brick Walls” players have to overcome to develop a significant MEMS business. The first is to launch a first MEMS product on the market. The second is moving from one to multiple MEMS product lines to diversify a company’s portfolio. The last is the move from being a device maker to a system maker with a successful MEMS business. So far, only Bosch has achieved a very successful transition.

Yole also announces: “New MEMS devices are emerging.” Under its analysis, the consulting company considers gas and chemical sensors. Such devices are based on semiconductor technologies. But MEMS is a further improvement that can reduce size by half or more and also cut costs, thus opening up new opportunities. According to Yole’s analysis, MEMS-based gas sensors will be increasingly used in applications with formfactor/cost issues, particularly in wearables and then consumer applications such as smartphones.

Another example is MEMS micro mirrors. Yole explains: “They are attracting new interest from the market for optical datacom, with Calient achieving impressive growth, or human-machine interfaces, as demonstrated by Intel’s acquisition of Lemoptix.”

Under its analysis on the MEMS & Sensors industry, Yole and its team took the opportunity to exchange with Jeanne Forget, Global Marketing Director, Bosch Sensortec and Dr Frank Schafer, Senior Manager of product management for automotive micro-electro-mechanical sensors (MEMS) at Robert Bosch on the evolution of the MEMS markets and the ability of Bosch, in the last 20 years and for the next decade, to build and maintain its unique leadership on MEMS industry. Full discussion is available on i-micronews.com, MEMS & Sensors news.

Applied Materials, Inc. today announced its Applied Endura Cirrus  HTX PVD system with breakthrough technology for patterning copper interconnects at 10nm and beyond. As chip features continue to shrink, innovations in hardmask are required to preserve the pattern integrity of tightly packed, tiny interconnect structures.With the introduction of this technology, Applied enables scaling of the TiN metal hardmask – the industry’s material of choice – to meet the patterning needs of copper interconnects in advanced microchips.

“Precision engineering of metal hardmask films is key to addressing the patterning challenges for advanced interconnects,” said Dr. Sundar Ramamurthy, vice president and general manager of Applied’s Metal Deposition Products business unit. “The Cirrus HTX TiN product represents Applied’s decades of expertise in applying PVD technology for engineering TiN film properties. Incorporating our unique VHF-based technology offers customers the flexibility of tuning stress in TiN films from compressive to tensile to overcome their specific integration challenges.”

Today’s advanced microchips can pack 20 kilometers of copper wiring in a 100 square millimeter area, stacked in 10 layers with up to 10 billion vias or vertical connections between layers. The role of the metal hardmask is to preserve the integrity of these patterned lines and vias in soft ULK dielectrics. However, with scaling, the compressive stress from conventional TiN hardmask layers can cause the narrow lines patterned in ULK films to deform or collapse. The tunable Cirrus HTX TiN hardmask with high etch selectivity delivers superior CD line width control and via overlay alignment resulting in yield improvement.

This breakthrough in TiN hardmask is made possible by precision materials engineering at the wafer level to produce a high density, low-stress film. Combining exceptional film thickness uniformity with low defectivity on a proven Endura platform, the Cirrus HTX system addresses the stringent high volume manufacturing needs of patterning multiple interconnect layers.

Applied Materials, Inc. is a developer precision materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries.

By Douglas G. Sutherland and David W. Price

Author’s Note: This is the sixth in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article in this series introduces one of the 10 fundamental truths and highlights their implications. Within this article we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

In previous installments we discussed capability, sampling, missed excursions, risk management and variability. Although all of these topics involve an element of time, in this paper we will discuss the importance of timeliness in more detail.

The sixth fundamental truth of process control for the semiconductor IC industry is:

Time is the Enemy of Profitability

There are three main phases to semiconductor manufacturing: research and development (R&D), ramp, and high volume manufacturing (HVM). All of them are expensive and time is a critical element in all three phases.

From a cash-flow perspective, R&D is the most difficult phase: the fab is spending hundreds of thousands of dollars every day on man power and capital equipment with no revenue from the newly developed products to offset that expense. In the ramp phase the fab starts to generate some revenue early on, but the yield and volume are still too low to offset the production costs. Furthermore, this revenue doesn’t even begin to offset the cost of R&D. It is usually not until the early stages of HVM that the fab has sufficient wafer starts and sufficient yield to start recovering the costs of the first two phases and begin making a profit. Figure 1 below shows the cumulative cash flow for the entire process.

Figure 1. The cumulative cash-flow as a function of time. In the R&D phase the cash-flow is negative but the slope of the curve turns positive in the ramp phase as revenues begin to build. The total costs do not turn positive until the beginning of high-volume manufacturing.

Figure 1. The cumulative cash-flow as a function of time. In the R&D phase the cash-flow is negative but the slope of the curve turns positive in the ramp phase as revenues begin to build. The total costs do not turn positive until the beginning of high-volume manufacturing.

What makes all of this even more challenging is that all the while, the prices paid for these new devices are falling. The time required from initial design to when the first chips reach the market is a critical parameter in the fab’s profitability. Figure 2 shows the actual decay curve for the average selling price (ASP) of memory chips from inception to maturity.

Figure 2.  Typical price decline curve for memory products in the first year after product introduction.   Similar trends can be seen for other devices types.

Figure 2. Typical price decline curve for memory products in the first year after product introduction. Similar trends can be seen for other devices types.

Consequently, while the fab is bleeding money on R&D, their ability to recoup those expenses is dwindling as the ASP steadily declines. Anything that can shorten the R&D and ramp phases shortens the time-to-market and allows fabs to realize the higher ASP shown on the left hand side of Figure 2.

From Figures 1 and 2 it is clear that even small delays in completing the R&D or ramp phases can make the difference between a fab that is wildly profitable and one that struggles just to break even. Those organizations that are the first to bring the latest technology to market reap the majority of the reward. This gives them a huge head start—in terms of both time and money—in the development of the next technology node and the whole cycle then repeats itself.

Process control is like a window that allows you to see what is happening at various stages of the manufacturing cycle. Without this, the entire exercise from R&D to HVM would be like trying to build a watch while wearing a blindfold. This analogy is not as far-fetched as it may seem. The features of integrated circuits are far too small to be seen and even when inspections are made, they are usually only done on a small percentage of the total wafers produced. For parametric measurements (films, CD and overlay) measurements are performed only on an infinitesimal percentage of the total transistors on each of the selected wafers. For the vast majority of time, the fab manager truly is blind. Parametric measurements and defect inspection are brief moments when ‘the watch maker’ can take off the blindfold, see the fruits of their labor and make whatever corrections may be required.

As manufacturing processes become more complex with multiple patterning, pitch splitting and other advanced patterning techniques, the risk of not yielding in a timely fashion is higher than ever. Having more process control steps early in the R&D and ramp phases increases the number of windows through which you can see how the process is performing. Investing in the highest quality process control tools improves the quality of these windows. A window that distorts the view—an inspection tool with poor capture rate or a parametric tool with poor accuracy—may be worse than no window at all because it wastes time and may provide misleading data. An effective process control strategy, consisting of the right tools, the right recipes and the right sampling all at the right steps, can significantly reduce the R&D and ramp times.

On a per wafer basis, the amount of process control should be highest in the R&D phase when the yield is near zero and there are more problems to catch and correct. Resolving a single rate-limiting issue in this phase with two fewer cycles of learning—approximately one month—can pay for a significant portion of the total budget spent on process control.

After R&D, the ramp phase is the next most important stage requiring focused attention with very high sampling rates. It’s imperative that the yield be increased to profitable levels as quickly as possible and you can’t do this while blindfolded.

Finally, in the HVM phase an effective process control strategy minimizes risk by discovering yield limiting problems (excursions) in a timely manner.

It’s all about time, as time is money. 

References:

1)     Process Watch: You Can’t Fix What You Can’t Find, Solid State Technology, July 2014

2)     Process Watch: Sampling Matters, Semiconductor Manufacturing and Design, September 2014

3)     Process Watch: The Most Expensive Defect, Solid State Technology, December 2014

4)     Process Watch: Fab Managers Don’t Like Surprises, Solid State Technology, December 2014

5)     Process Watch: Know Your Enemy, Solid State Technology, March 2015 

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

 

Semiconductor Research Corporation (SRC) announced today that Ken Hansen has been appointed SRC’s new President and Chief Executive Officer (CEO), effective June 1.

Hansen’s professional experience includes serving as Vice President and Chief Technology Officer (CTO) at Freescale Semiconductor since 2009. Hansen replaces retiring SRC President and CEO Larry Sumney who guided the organization for more than 30 years since its inception in 1982. SRC’s many accolades over the years include being the recipient of the National Medal of Technology in 2007.

“SRC under Larry Sumney’s leadership has made an indelible impact on the advancement of technology during the past three decades, and we congratulate Larry on his retirement and salute him for his contributions to the semiconductor industry,” said Mike Mayberry, Intel Corporate Vice President and Director of Components Research who is SRC Board Chairman. “We also welcome Ken Hansen to his new role guiding SRC, and we look forward to Ken’s leadership helping SRC reach new heights in an era where basic research and development is as critical as ever.”

Prior to his CTO role at Freescale, Hansen led research and development teams for more than 30 years in multiple senior technology and management positions at Freescale and Motorola. Hansen holds Bachelor and Master of Science degrees in Electrical Engineering from the University of Illinois where he has been recognized as an ECE (Department of Electrical and Computer Engineering) Distinguished Alumni.

In his new role at SRC, Hansen intends to build on the consortium’s mission of driving focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry.

“SRC also has an opportunity to strengthen its core by recruiting new members to gain more leverage to fund industry wide solutions for some of the challenging technology roadblocks that are ahead of us,” said Hansen.

“The model that SRC has developed is unmatched in the industry and has proven to be extremely significant. The industry would not be where it is today without the contributions of SRC under the leadership and vision of Larry Sumney,” Hansen continued.

Meanwhile, Sumney’s decorated career began in 1962 at the Naval Research Laboratory. He later directed various other research programs at Naval Electronics Systems Command and the Office of the Undersecretary of Defense — including the Department of Defense’s major technology initiative, Very High Speed ICs (VHSIC) —before agreeing to lead SRC following its formation by the Semiconductor Industry Association.

Under his leadership, SRC has also formed wholly owned subsidiaries managing the Nanoelectronics Research Initiative (NRI), the Semiconductor Technology Advanced Research network (STARnet) and the SRC Education Alliance, among other programs. Sumney received a Bachelor of Physics from Washington and Jefferson (W&J) College, which recognized him with the 2012 Alumni Achievement Award, and a Master of Engineering Administration from George Washington University.

“I have enjoyed a front row seat in the development of today’s technology-based economy and advancement of humanity through the semiconductor industry,” said Sumney. “I am completely confident that SRC is well positioned and will continue to flourish, to seed breakthrough innovation and help provide the people and ideas to keep the U.S. semiconductor industry competitive and prosperous in years to come.”

Additional industry leaders with strong ties to SRC commended Sumney for his service over the years while supporting Hansen’s appointment.

“Over more than 30 years, Larry Sumney’s visionary leadership of SRC has steered one of the world’s most transformative industries through times of tremendous growth and innovation,” said John Kelly, Senior Vice President, Solutions Portfolio and Research for IBM.  “I’ll personally miss working with Larry, but also have tremendous respect for and confidence in Ken Hansen, and we look forward to collaborating with him to drive the next generation of research in this vital industry.”

“Larry’s leadership and vision are key reasons why SRC’s research has played a fundamental role behind many of the most significant semiconductor innovations of the last three decades,” said Lisa Su, AMD president and CEO and a former SRC student. “Ken’s broad industry experience makes him ideally suited to lead the next phase of the SRC, as the organization continues to expand its capabilities and provide the basic research and development foundation needed to further accelerate innovation across the industry.”

By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

Scaling is now bifurcating – some scaling on with 28/22nm, while other push below 14nm.

In his famous 1965 paper Cramming more components onto integrated circuits, Moore wrote: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year”. Dimensional scaling below 28nm will only increase the ‘component cost’ as we described in Moore’s Law has stopped at 28nm and is detailed in the following tables published recently by IBS.

Fig 1

 

While there is still a strong effort behind dimensional scaling to 14, 10 and 7nm – and possibly even beyond, a new scaling effort is emerging to reduce the ‘component costs’ and increase integration yet still utilize the 28 nm process node. The semiconductor industry is now going through a bifurcation phase.

This new emerging trend of scaling by factors other than dimensional scaling was recognized early-on by Gordon Moore and was detailed in his 1975 famous IEDM paper “Progress in digital integrated electronics.”. In that paper Moore updated the time scaling rate to every two years and suggested the following factors are helping to drive scaling forward:

  1.  “Die size” – “larger chip area”
  2. “Dimension” – “higher density” and “finer geometries”
  3. “Device and circuit cleverness”

A fourth factor should have been added to the list above – improvement in manufacturing efficiency, which ensued from the increase in wafer sizes from 4” to 5” and all the way to the 12” of today, and many other manufacturing improvements.

In the past, all of these factors were aggregated into dimensional scaling as old fabs got obsolete and improvements were implemented predominantly in the new emerging node. Nowadays, as dimensional scaling has reached its diminishing returns phase, we can see a very diverse adaption of technology improvments.

In his keynote presentation at the 2014 Synopsys user group meeting, Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys’ newer tools to improve older node design effectiveness. The following is one of them:

Fig 2

AMD’s recent presentation at ISSCC 2015 clearly illustrates this point by showing device improvements while still staying at the same 28 nm process node, see slide below. As could be seen, major improvements in power, yield, and performance are possible over time without changing the technology node. AMD’s President & CEO Dr. Lisa Su presentation in 2015 Semicon China, reiterated AMD’s technology progress within the same 28nm technology node:

Fig 3

Even more significant would be the adoption of a breakthrough technology. A good example is the SRAM technology developed by Zeno Semiconductor, which has recently been validated on a 28nm process. This new SRAM technology replaces the 6T SRAM bit cell with 1T SRAM (true SRAM – no refresh is needed) providing significant reduction of ‘component costs’ as is illustrated in the following two slides.

Fig 4

Fig 5

This new industry trend was nicely articulated by Kelvin Low of Samsung covered in “Samsung Describes Road to 14nm, FinFETs a challenge, FD-SOI an alternative.” Quoting: “Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price …The cost per transistor has increased in 14nm FinFETs and will continue to do so, Low said, so an alternative technology such as 28nm SOI is necessary”. TSMC too is now spending on new R&D efforts to improve their 28 nm as was presented in TSMC 2015 Technology Symposium, introducing new 28nm processes, 28HPC+ and 28ULP. 28HPC+ is for high performance, a speed gain of about 15% for the same leakage, or a reduction of 30-50% in leakage for the same speed. The 28ULP (for ultra-low power) process is for IoT applications with a lower operating voltage of 0.7V (versus 0.9V for 28HPC+). And also new standard cell libraries were developed for this process with 9 and 7 track libraries (compared to 12T/9T before).

“Device and circuit cleverness” as a factor will never stop; however, it is made of a series of individual improvements that will not be enough to sustain a long-term scaling path for the industry. An alternative long-term path will be “Die size” – “larger chip area,” which is effectively monolithic 3D, and manufacturing efficiency, which will have an important role in monolithic 3D.

And who is better to call it than Mark Bohr of Intel? In a recent blog piece “Intel predicts Moore’s Law to last another 10 years” Bohr is quoted predicting “that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”

And this is also visible in the marketplace by the industry-wide adoption of 3D NAND devices that Samsung started to mass-produce in 2014, and followed with a second generation 32 layer-stack device this year, and forecasting going to ~ 100 layers, as illustrated in their slide:

Fig 6

 

In the recent webcast “Monolithic 3D: The Most Effective Path for Future IC Scaling,” Dr. Maud Vinet of CEA Leti presented their “CoolCube” monolithic 3D technology, which was followed by our own, i.e., MonolithIC 3D, presentation. An important breakthrough presented by us was a monolithic 3D process flow that does not require changes in transistor-formation process and could be easily integrated by any fab at any process node.

Finally, I’d like to quote Mark Bohr again as we reported in our blog “Intel Calls for 3D IC”: “heterogeneous integration enabled by 3D IC is an increasingly important part of scaling” as was presented in ISSCC 2015.

Fig 7

 

This is illustrated nicely by the following figure presented by Qualcomm in their ISPD ‘15 paper titled “3D VLSI: A Scalable Integration Beyond 2D.”

Fig 8

 

In summary, the general promise of Moore’s Law is not going to end any time soon. Yet it is not going to be the simple brute-force x0.7 dimensional scaling that dominated the industry for the last 5 decades. Quoting Mark Bohr again, it “will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”

P.S. –

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies.

Texas Instruments was again the leading supplier of analog devices in 2014 with $8.1 billion in sales, and increased its analog marketshare to 18 percent, according to rankings of top suppliers of major IC product categories found in IC Insights’ April Update to The McClean Report 2015.  The top 10 analog IC suppliers accounted for 57 percent of total analog sales in 2014, up slightly from 56 percent in 2013.  Among the top suppliers, six companies on the list had sales in excess of $2.0 billion and three others exceeded $1.0 billion in analog sales last year. (Renesas again fell short of the $1.0 billion mark.) Among the top suppliers, Skyworks Solutions (42 percent), NXP (21 percent), and Texas Instruments (13 percent) showed the strongest growth and outperformed the total analog market (9 percent) by the widest margins.

Figure 1

Figure 1

TI’s analog sales represented 62 percent of its total corporate revenue in 2014.  Since the 1990s, TI has focused on increasing its presence in the analog market.  In 2009, TI purchased 300mm manufacturing tools from defunct Qimonda and put them to use to build analog ICs, becoming the first company to manufacture analog devices on 300mm equipment.  In 2010, TI acquired two wafer fabs operated by Spansion in Aizu-Wakamatsu, Japan, and it acquired a fully equipped 200mm fab in China from Cension Semiconductor Manufacturing in Chengdu.  Both facilities were immediately put to use making analog ICs.  In April 2011, TI acquired National Semiconductor—its rival in many analog markets—for $6.5 billion.

TI is boosting its analog position by transferring more manufacturing to 300mm wafers in its newer RFAB and its older DMOS 6 fab.  TI says the 300mm fabs will together help reduce its total production costs by up to 40 percent, increase its available manufacturing capacity substantially, and give it added flexibility to respond to customer demands.

TI’s 2014 analog revenue was nearly 3x larger than second place ST, whose sales grew 2 percent in 2014. ST accounted for 6 percent marketshare. ST attributed its lower analog sales to softer equipment sales (computer, consumer, automotive, industrial) among its primary customers.  Third-ranked Infineon and seventh-ranked NXP were two other European-headquartered companies ranked among the top 10 analog suppliers in 2014.  Collectively, these three European suppliers accounted for 16 percent analog marketshare last year.

Skyworks enjoyed a stellar year in which its analog sales increased 42 percent mostly due to strong worldwide smartphone sales. Skyworks Solutions makes analog and mixed signal semiconductors for Apple, Samsung, and other suppliers of mobile devices.  Multiple power amplifier components from Skyworks are found in Apple’s iPhone 6 models.  It has been estimated that Skyworks supplies $4 worth of content from every new iPhone 6 handset.

While Skyworks is heavily focused in mobile, CEO David Aldrich has said the company’s technology is “a conduit into the Internet of Things.”  In 2015, the company said it would look to the automotive, home, and wearable markets to expand its presence in applications linked to the Internet of Things.

Analog ICs like audio amplifiers, op amps, are analog switches are key components and building blocks for creating innovative wearable applications.  Skyworks’ wireless technology is used in some General Electric healthcare equipment, and the company recently sealed a deal to supply high-performance filter solutions to Panasonic devices.

Analog Devices purchased smaller rival Hittite Microwave in mid-2014, a company that specialized in devices for RF and signal-conversion applications.  ADI’s analog sales grew 9% last year.  ADI is expected to provide devices that enable the 3D/Force Touch feature—currently available on the Apple Watch—to the iPhone 6s that is due out in the second half of 2015 and new generations of the iPad. The Force Touch feature uses tiny electrodes to distinguish between a light tap and a deep press to trigger contextually specific controls.

Using first-principles calculations, the electronic structures and optical properties that arise on doping-atom-containing silicon nitride systems are reported as a function of dielectric constant, reflectivity, absorption and loss spectra.

BY XUEFENG LU, XIN GUO, PEIQING LA, YUPENG WEI, JIANBO YIN and XUELI NAN, Lanzhou University of Technology, Lanzhou, China

The development of hexagonal silicon nitride is concerned predominantly with the design and fabrication of structural materials because of its excellent properties such as high strength, toughness, flexibility and good resistance to thermal shock and oxidation [1-3]. While a great deal is understood of block Si3N4 behavior, one of the challenges to exploiting the functionality will be to better understand the variety and corresponding structural features unique to Si3N4. Eliciting a desired output from controlled inputs using predesigned materials is one of the key aspects of current materials’ research field.

A first-principles calculation within the local density approximation suggested that -βSi3N4 has a direct band gap of about 4.34 eV. Although the calculated band gap may be somewhat underestimated, owing to the LDA, β-Si3N4 is likely to fall into the category of wide-gap semiconductors by appropriate doping [4-5]. Simultaneously, the direct band gap reveals the potential applications as optical or electric devices apart from the structural applications. In order to use β-Si3N4 as a semiconductor, it is necessary to find proper dopants.

Recently, there was substantial interest in investigating the properties of Si3N4 that combined the adsorption and doping. Various theoretical methods have been employed to model and understand these behaviors, motivated by the fact that different structures may exhibit desired and fascinating properties. Wang simulated the interaction of O2 with the β-Si3N4 surface and found that the oxidation occurs on the-SiN (0001) surface at 1200°C more easily 34 by means of the calculated significant chemisorption energy and the short adsorption bond length [6]. Oba investigated n- and p-type dopants for cubic silicon nitride and concluded that P and O are preferable for n-type doping, while Al is favorable for p-type doping in terms of the formation and ionization energies [7]. The dependence of the formation energies on the chemical potentials indicates that a proper choice of growth conditions is mandatory for suppressing the incorporation of these impurities into anti and interstitial sites [8]. For the low Al concentration, the material exhibits the dielectric behavior, while the metallic behavior for the high Al concentration [9]. Ching concluded that cations with small radii tend to occupy the tetrahedral site and those with large radii tend to occupy octahedral sites for γ-Si3N4, which is likely to show some metallic characteristics at the Ti concentration [10].

Previously, we have reported the impurity species appropriate to β-Si3N4 based on the first-principles calculations [11-13]. In the present contribution, we conducted similar calculations to investigate impurities effects in β-Si3N4, as well as the electronic structures and optical properties of rare earth (RE)-doped systems, to obtain the further information in details.

Theoretical approaches and computational procedures

Silicon Nitride Fig 1a

 

FIGURE 1. Supercells (2×1×1) of doped systems: (a) Ga-doped system; (b) Tb-doped system.

FIGURE 1. Supercells (2×1×1) of doped systems: (a) Ga-doped system; (b) Tb-doped system.

Here, we demonstrated the first-principles calculations using the CASTEP program code with plane-wave pseudopotential (PWP). Our simulation model, detailed in the method section, is summarized in FIGURE 1 and described briefly here. The hexagonal β-Si3N4 unit cell contains two formula units (14 atoms) with a space group P63/m. The idealized Si-N layers in an ABAB sequence can depict the structure perfectly. All of the Si atoms are equivalent (6h sites), but there are two inequivalent nitrogen sites: N2c at 2c sites and N6h at N6h sites. The N2c atoms locate in a planar geometry with their three Si nearest neighbors, and N6h atoms locate at slightly puckered sites enclosed by three Si atoms, while Si atoms locate at the center of slightly irregular tetrahedron bonded with one N2c atom and three N6h atoms. Supercells (2×1×1) containing 28 atoms were used to simulate RE-doped β-Si3N4. The doping was realized by substituting some Si atoms with Gd and Tb atoms. The core region and valence electrons of the atoms in the systems were illustrated by the ultrasoft pseudopotential. The lattice constants of primitive cells were determined through calculations using a plane-wave cutoff energy of 770 eV and a 4×4×10 point grid in the irreducible part of the Brillouinzone. The structural optimization was done by relaxing both internal coordinates and the lattice constants by calculating the ab initio forces on the ions, within the Born-Oppenheimer approximation, until the absolute values of the forces were converged to less than 10-2 eV/Å. The stress level for the equilibrium structure is less than 1×10-2 GPa and the max displacement is 5×10-4 Å in supercells.

Results and discussion

Geometry optimization results: Both models are composed of 28-atom, for which the only difference is rare element. The optimization was carried out by relaxing both the internal coordinates and the lattice constants by calculating the ab initio forces on the ions, until the absolute values of the forces were smaller than the set values. The obtained results are summarized in Table 1. Compared to the experiment values, the calculated lattice constants are overestimated within 1%, illustrating a reasonable agreement. Because of the bigger atoms radius of Gd and Tb atoms, the lattice constants and volume increase remarkably after doping. The Eg of Gd-doped system is 0.095 eV, and decreases to 0.073 eV for Tb-doped one due to the narrower distance of the bottom of conduction band and the top of valence band derived from doping. For the purpose of characterizing the stability of doped structures, the Eb and Ef are brought forward in terms of total energy and total sums of elements free energies, and the atomic chemical potential, respectively, as illustrated in Eqs. (1) and (2).

Silicon Nitride Equation

where ESi3N4 and ET denote the total energies of the supercells before and after doping, respectively. X is doping atom, μSi and μX are the chemical potentials of Si and doping atoms, respectively. Note that Eb of system accounts for its stable degree. The and the conduction band is about 0.1 eV, which is adequately in reasonable accordance with the results of energy band structures as discussed above. For Tb-doped system, also three valence band parts can be observed: the bottom band ranging from -43.03 to -41.73 eV originates mostly from Tb s orbital electrons; the next one in the middle of -21.71 and -12.31 eV is briefly due to Tb p and N s states; the larger the absolute value is, the more stable the final structure is. The stability of Gd-doped system with small Eb is higher than that of Tb-doped one. The Ef is relative to the chemical potentials of elements and may also exhibit the stability of doped structures. The obtained Ef values for Gd- and Tb-doped systems are 12 and 15eV, respectively, revealing that the structure of the former is more stable than that of the latter.

Screen Shot 2015-05-07 at 3.08.59 PM

Electronic structures: FIGURES 2A and B show the achieved electronic band structures of Gd- and Tb-doped supercells. For Gd-doped system, the Eg drops obviously to 0.095 as compared to undoped one (4.336 eV). The valence band (VB) can be divided into three group: the bottom of VB is about -40.94 eV; the next one is in the range of -20.9 and -12.8 with a width of 8.1 eV; the top VB locates between -9.62 and 1.15 eV with an extent of 10.77 eV. While for the Tb-doped system, the Eg decreases continu- ously to 0.073. The VB may also be divided into three group: the bottom of VB is at -42.45 eV; the next one locates between -21.29 and -12.79 eV accompanying a width of 8.5 eV; the top VB is in the range of -9.75 and 0.89 eV with a width of 10.64 eV. It is worth noting that both VBs have higher densities than those of undoped system accompanying the overlap of the energy band although doping with a lower concentration.

Silicon Nitride Fig 2a

 

FIGURE 2. Band structures of supercells: (a) Gd-doped system; (b) Tb-doped system.

FIGURE 2. Band structures of supercells: (a) Gd-doped system; (b) Tb-doped system.

In order to analyze further the results according to the band structures, we conduct the densities of states (DOS) coming from the calculations with GGA, as demonstrated in FIGURE 3. The calculated total DOS derives from the partial density (PDOS) of N, Si, Gd, and Tb atoms. The obtained total and partial densities of states for Gd- and Tb-doped systems are displayed in Fig.3a and b, respectively. One can see that for Gd-doped system, there are three valence regions: the lower energy band located between -41.46 and -40.06 eV briefly comes from Gd s orbital electrons; the next energy band in the range of -21.34 and -11.95 eV mainly originates from Gd p and N s orbital electrons; the upper valence band occurs between -9.99 and 1.74 eV is primarily from Gd f and N p states; the conduction band in the range of 3.23 to 6.40 eV principally consists of Si p orbital electrons. The distance between the top valence band top valence band located between -10.07 and 1.38 mainly is owing to Tb f and N p orbital electrons; the conduction band between 2.85 and 6.68 eV is composed of Si p states. Summing up, the above, RE doping contributes to the formation of the lower VB of the doped systems, derived from the s orbital electrons of RE, and the formation of narrow band gap, revealing that potential applications in semiconductor devices.

Silicon Nitride Fig 3a

 

FIGURE 3. Total and partial densities of states: (a) Gd-doped system; (b) Tb-doped system.

FIGURE 3. Total and partial densities of states: (a) Gd-doped system; (b) Tb-doped system.

To explore the insights into the comprehension of the charge transfer of both systems, the electron density difference maps in planes containing different atoms are displayed in FIGURES 4 and 5. The emerged blue and red parts revealed in pictures represent the electron loss and gain, respectively. It can be seen that the changes in electron density are apparent when Si atom is substituted by Gd or Tb atoms, especially for Tb doping. In the case of both cases, the electron loss, which occurred near the N atom between Si and N atoms and is close to doped atoms, weakens after doping, while the electron loss turns into electron gain with regard to Tb intervention compared to undoped field, weakening the strength of the covalent bond. As we investigate more carefully these maps, the charge density distributions of non-spherical in both cases can be observed. Concerning the electron loss, the toothed shapes that the pentagonal starfish and latin cross can be seen for the Gd- and Tb-doped systems, respectively.

FIGURE 4. Electron density difference maps of Gd- doped system (a) Gd-N-Si; (b) Si-N-Gd; (c) 3N-3Si.

FIGURE 4. Electron density difference maps of Gd- doped system (a) Gd-N-Si; (b) Si-N-Gd; (c) 3N-3Si.

FIGURE 5. Electron density difference maps of Tb- doped system (a) Tb-N-Si; (b) Si-N-Tb; (c) 3N-3Si.

FIGURE 5. Electron density difference maps of Tb- doped system (a) Tb-N-Si; (b) Si-N-Tb; (c) 3N-3Si.

Optical properties investigation: The optical properties of doped systems are not perfectly understood at all owing to the two particularly challenging problems. Experimentally obtaining the single-crystal samples and property response is difficult and theoretically the works of optical properties of element doped silicon nitride are lack. Due to optical properties not only contain the occupied and unoccupied parts of the electronic structures but also carry the information about the character of bands, it is of underlying importance. In this work, we carry out a complete analysis of doped systems based on first-principles spectroscopy for different optical functions such as imaginary and real parts of the dielectric function, the reflectivity, the absorption spectra and the loss function. Due to the considered systems crystallize in the hexagonal structure with space group P63/m, the dielectric tensor contains three components corresponding to the electric field along the a, b, and c-crystallographic axes, i.e. εxx, εyy, and εzz. The imaginary part ε2(ω) is given in equation (3), and the real part ε1(ω) can be derived from the imaginary part employing the Kramer- Kronig transformation as shown in equation (4). The absorption coefficient (ω) and the electron energy loss function L(ω) can be gained directly related to ε1(ω) and ε2(ω) as described in equation (5) and (6).

FIGURE 6 shows the real ε1(ω) and imaginary ε2(ω) parts of theoretical dielectric function of supercells doped by Gd- and Tb-doped systems. It is meaningful parameter due to the reason that it embodies the basic feature of linear response to an electromagnetic wave and determines the only propagation behavior of the radiation within. One can see that the static dielectric constant obtained at the zero frequency of the real part decreases to 7.97 after Gd doping, and markedly increases to 10.5 for Tb doping with respect to undoped system (8.2) [16], revealing its potential applications in electrics and optics. Compared to the other two directions, εyy and εzz has larger values of 10.76 and 16.1 for Gd- and Tb-doped systems, respectively. Correspondingly, the change is similar to that of imaging part. This reveals that Gd-doped system can exhibit longer life in application as dielectric materials in the low energy regions because of the low static dielectric constant and loss.

Silicon Nitride Fig 6a

 

FIGURE 6. The theoretical dielectric function of supercells: (a) Gd-doped system; (b) Tb-doped system.

FIGURE 6. The theoretical dielectric function of supercells: (a) Gd-doped system; (b) Tb-doped system.

FIGURE 7 illustrates the absorption spectra η(ω) of doped systems. It is found that the strong absorption edges locate between 5 and 16 eV, giving the threshold for direct optical transitions between the top valence band and bottom of conduction band. All the parts Ai (i=t, xx, yy and zz) display main peaks located at 10.52, 10.47, 10.51 and 9.19 eV for Gd-doped system and 10.55, 10.71, 10.71 and 10.49 eV for Tb-doped system. On the left of the host absorption peaks, the other peaks (about 1.78 and 25eV) appear, which are attributed to the interband transitions of free electronic carries in the top of VB. The values of the peaks are lower and have a small effect on the host peak, indicating that in the low energy region the doping systems may still exhibit “Transparent Type” compared to undoped system [13], but the range of the edges of the absorption peaks reduced. The obtained reflectivity spectra detailed in FIGURE 8 is displayed. Spectra profiles are similar for Gd- and Tb-doped of equal peak situations. At the same time, two host peaks all locate at 11.7 eV. It is worth noting that three components Ri (i=xx, yy and zz) display the similar peaks value and positions, which reveals that the optical properties studied here show the characteristics of some isotropy.

Silicon Nitride Fig 7a

 

FIGURE 7. The absorption spectra of supercells: (a) Gd-doped system; (b) Tb-doped system.

FIGURE 7. The absorption spectra of supercells: (a) Gd-doped system; (b) Tb-doped system.

Silicon Nitride Fig 8a

FIGURE 8. The reflectivity spectra of supercells: (a) Gd-doped system; (b) Tb-doped system.

FIGURE 8. The reflectivity spectra of supercells: (a) Gd-doped system; (b) Tb-doped system.

 

FIGURE 9 summarizes the theoretical electron energy loss spectra (EELS) L(ω) of doped systems, which is in agreement with the imaginary part of the reciprocal of the dielectric function. The peak of EELS is related to the plasma resonance and the frequency interrelated with the peak is the so-called plasma frequency, above which the material exhibits the dielectric behavior, while below which the material behaves like semiconductors and metals.

Silicon Nitride Fig 9a

 

FIGURE 9. The electron energy loss spectra of supercells: (a) Gd-doped system; (b) Tb-doped system.

FIGURE 9. The electron energy loss spectra of supercells: (a) Gd-doped system; (b) Tb-doped system.

It is found from the results that the host peaks of doped systems are at about 12.5 and 14 eV, respectively, which are lower than that of undoped system (20 eV), indicating that a red-shift phenomenon is present after doping. At the same time, one weak peak appears at 2 eV. As can be seen from the calculation results that the doped systems may display the semiconductor behavior, which is in agreement with our calculated values of the static dielectric constants. At the same time, it is also concluded that light spreads easily in the lower energy regions for the doping systems.

Conclusions

In summary, using the first-principles calculations, we report on the electronic structures and optical properties that arise on doping-atom-containing silicon nitride systems as a function of dielectric constant, reflectivity, absorption and loss spectra. The results are as follows:

(1) The fully relaxed structural parameters are found to be in good agreement with experi- mental data. Calculated banding energies of Gd-and Tb-doped systems are -204 and -197 eV, and formation energies are 12 and 15 eV, respectively. It can be readily seen that the structure of the former is more stable than that of the latter.

(2) The electron loss near the N atom between Si and N atoms turns into electron gain with respect to Tb intervention compared to undoped field, weakening the strength of the covalent bond. Concerning the electron loss, the toothed shapes that the pentagonal starfish and latin cross can be observed for the Gd- and Tb-doped systems, respectively.

(3) The absorption band ranges of doped systems become narrower. Both of reflectivity spectra profiles are similar and all locate at 11.7 eV, exhibiting the characteristics of some isotropy. In theoretical electron energy loss spectra, the host peaks of doped systems locate at about 12.5 and 14 eV, indicating that a red-shift phenomenon occurs after doping.

(4) Gd-doped system can exhibit longer life in application as dielectric materials in the low energy regions because of the low static dielectric constant and loss, as well as transparent type characteristic exhibited in lower energy region.

Acknowledgements

The work was supported by The National Natural Science Foundation of China (51402142, 51164022), The Gansu Provincial Youth Science and Technology Fund Projects (1310RJYA006, 1212RJYA004), Gansu Provincial Science and Technology Support Program (1304GKCA027), Gansu Provincial Department of Construction Project (1201ZTC042).

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XUEFENG LU, XIN GUO, PEIQING LA, YUPENG WEI, JIANBO YIN and XUELI NAN are researchers at the State Key Laboratory of Gansu Advanced Non-ferrous Metal Materials, Lanzhou University of Technology, Lanzhou, China. JIANBO YIN is also with the State Key of Solid Lubrication, Lanzhou Institute of Chemical Physics, Chinese Academy of Science, Lanzhou, China.