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Synthetic diamond heat spreaders and GaN-on-Diamond wafers have emerged as a leading thermal-management technology for RF Power Amplifiers

BY THOMAS OBELOER, DANIEL TWITCHEN, JULIAN ELLIS, BRUCE BOLLIGER,
Element Six Technologies, Santa Clara, CA & MARTIN KUBALL AND JULIAN ANAYA, Center for Device Thermography and Reliability (CDTR), H. H. Wills Physics Laboratory, University of Bristol, Bristol, U.K.

GaN-based transistors and their related RF Power Amplifiers (PAs) have emerged as the leading solid-state technology to replace traveling wave tubes in radar, EW (Electronic warfare) systems, and satellite communications, and to replace GaAs transistors in cellular base stations. However, significant thermal limitations prevent GaN PAs from reaching their intrinsic performance capability. Metallized synthetic diamond heat spreaders have recently been used to address this thermal management challenge, particularly in cellular base station and military radar applications.

This article covers several important issues that advanced thermal solutions, particularly for RF power amplifiers, must address. Here, we are presenting new materials, such as CVD (chemical vapor deposition) diamond as a heat spreader to reduce overall package thermal resistance compared to today’s more commonly used materials for thermal management. Also, mounting aspects and some new developments regarding the thermal resistance at the bonding interfaces to diamond heat spreaders are discussed.

CVD diamond

Diamond possesses an extraordinary set of properties including the highest known thermal conductivity, stiffness and hardness, combined with high optical transmission across a wide wavelength range, low expansion coefficient, and low density. These characteristics can make diamond a material of choice for thermal management to significantly reduce thermal resis- tance. CVD diamond is now readily commercially available in different grades with thermal conductivities ranging from 1000 to 2000 W/mK. Also very important is the fact that CVD diamond can be engineered to have fully isotropic characteristics, enabling enhanced heat spreading in all directions. FIGURE 1 shows a comparison of the thermal conductivity of CVD diamond with other materials traditionally used for heat spreading purposes.

FIGURE 1. Comparison of thermal conductivity of CVD diamond and traditional heat spreading materials [1, 2].

FIGURE 1. Comparison of thermal conductivity of CVD diamond and traditional heat spreading materials [1, 2].

On-going development in the technologies to synthesize CVD diamond has enabled it to become readily available in volume at acceptable costs. Unmetallized CVD diamond heat spreaders are available today at a typical volume cost of $1/mm3. Prices vary dependant on the thermal-conductivity grade used. In some instances, system operation at elevated temperatures can reduce both the initial cost of the cooling sub-system and the on-going operating cost as well. When applied with appropriate die-attach methods, diamond heat spreaders provide reliable solutions for semiconductor packages with significant thermal management challenges [1].

Application notes for the use of CVD Diamond

To obtain the most effective use of the extreme properties of CVD Diamond in overall system design, package integration issues need to be carefully considered. Failure to address any one of these issues will result in a sub-optimal thermal solution. Here are the most important points to be considered:

  • Surface preparation
  • Mounting techniques
  • Diamond thickness
  • Functional considerations
  • Metallizations and thermal barrier resistance

Surface preparation: The surfaces of die-level devices have to be machined in a suitable fashion to allow good heat transfer. Surface flatness for heat spreaders should typically be less than 1 micron/mm and the roughness better than Ra < 50 nm, which can be achieved by polishing techniques. Any deficiency in flatness must be compensated for by the mounting techniques which will cause higher thermal resistance.

Mounting techniques: Whereas in some advanced device applications, such as high-power laser diodes, atomic-force bonding techniques are being considered, most applications currently employ soldering techniques for die attachment to the heat spreader. Again, solder layers should be kept to minimum thickness, particularly for the primary TIM1 (thermal interface material (TIM) between die and heat spreader), to minimize thermal resistance. An important factor in applying solder joints is the expansion mismatch between the CVD diamond and the semiconductor material, as it can significantly influence performance and lifetime. GaAs (Gallium Arsenide) devices up to an edge length of 2.5 mm can be hard soldered to CVD diamond without CTE-mismatch problems. (Note that the CTE for CVD Diamond is 1.0 ppm/K at 300K). For edge lengths greater than 2.5 mm, using a soft solder can avoid excessive stresses in the device. TABLE 1 shows a wide range of solder materials commercially available to address various needs for soldering processes.

TABLE 1. Summary of soldering materials [2].

TABLE 1. Summary of soldering materials [2].

Diamond thickness: The thickness of the CVD diamond is important. For devices with small hot spots, such as RF amplifiers or laser diodes, a thickness of 250 to 400 microns is sufficient. Diamond’s isotropic characteristics effectively spread the heat to reduce maximum operation temperature at constant power output. However, applications with larger heat spots on the order of 1 to 10 mm in diameter require thicker diamond for better results. An example is disk lasers that can have an optical output power of several kW and a power density of about 2kW/cm2; a diamond thickness of several mm has proven to be beneficial to disk laser operation [3].

Functional considerations: There are also functional requirements that may be important. One is the electrical conductivity of the heat spreader. For devices such as laser diodes, it is easiest to run the drive current through the device and use the heat spreader for the ground contact. For other devices, the heat spreader is required to be insulating. As CVD diamond is an intrinsic insulator, this insulation can be maintained by keeping the side faces free of metallization. This could be required for RF amplifiers and transistors, especially at higher frequencies (f > 2 GHz).

Thermal simulation helps optimize the heat spreader configuration to find the best solution based on power output needs, material thickness, metallization scheme, heat source geometry and package configuration. For design optimization, it is important that the thermal simulation model includes the complete junction-to-case system, including the device details, all interfaces, materials and the subsequent heat sinking solution.

Metallizations and thermal barrier resistance

Metallizations are an essential component to the application of CVD diamond in RF Amplifier and similar applications. Typically, for reasons of adhesion, mechanical and thermal robustness, three-layer metallization schemes are used. An example of such a three-layer metallization scheme fundamentally comprises: a) a carbide forming metal layer which forms a carbide bonding to the diamond component; b) a diffusion barrier metal layer disposed over the carbide forming metal layer; and c) a surface metal bonding layer disposed over the diffusion barrier metal which provides both a protective layer and a wettable surface layer onto which a metal solder or metal braze can be applied to bond the diamond heat spreader to die and other device components. A particular example of such a three-layer metalli- zation scheme is Ti / Pt / Au.

High-quality, sputter-deposited, thin-film metallizations are strongly recommended for advanced thermal solutions. As thermal contact resistance between the device
and the heat spreader must be minimized, any additional metal interface being added to the system must be avoided. Sputtered layers, especially of titanium, can form a very effective chemical bond with CVD diamond to ensure long-term stability even at elevated temperatures. To separate the required gold attach layer from the titanium adhesion layer, a platinum or titanium/tungsten (TiW) barrier layer is recommended. The Ti/Pt/Au scheme is very commonly used in high-end devices and has excellent characteristics with regards to stability and endurance, even over extended lifetime periods under changing thermal loads. However, this scheme also has a drawback, as the thermal conductivities of the titanium and platinum are relatively low (Tc=22 W/ mK and Tc=70 W/mK respectively). In the search for improved materials to be applied, the use of chromium has been identified as a viable alter- native. Chromium forms a carbide with diamond and is also readily used as a barrier layer, enabling it to perform both functions at a relatively high thermal conductivity of Tc=93.9 W/mk. To test the thermal effectiveness of chromium, samples were prepared at the CDTR (Centre for Device Thermog- raphy and Reliability) at Bristol University comparing a standard Ti/Pt/Au (100/120/500nm) metallization with this novel Cr/Au (100/500nm) configuration. The measurements of the thermal conductivity revealed that the thermal conduc- tivity of the Cr/Au metallization is about 4 times higher as compared to the Ti/Pt/Au. Results are shown in FIGURE 2.

FIGURE 2. Comparison of thermal conductivity of different metallization schemes [4].

FIGURE 2. Comparison of thermal conductivity of different metallization schemes [4].

Application example

To demonstrate the impact of this Cr adhesion/ barrier layer advantage versus Ti/Pt/Au, high power GaN on SiC HEMT (High Electron Mobility Transistor) devices were mounted to a CVD Diamond heat spreader. A cap layer of AuSn with a thickness of 25 microns was chosen. To ensure comparable results for all samples prepared, these samples were placed on a temperature stable platform also made from high thermally conductive diamond material. Results are shown in FIGURE 3: In the left diagram, the base temperature is plotted for increasing power output from the device. As can be seen, the temperature for the Cr/Au configuration is significantly lower, at 9W device power output by about 10 degrees C. On the right hand side, the graph shows the temperature as measured on the transistor channel directly.

FIGURE 3. Temperatures as a function of power for different metallization schemes and solder thickness [4].

FIGURE 3. Temperatures as a function of power for different metallization schemes and solder thickness [4].

In this case, the lower thermal resistivity of the Cr-based metallization layer decreases the channel temperature by more than 20 degrees C at 9W power output.

This significant temperature reduction will result in as much as a 4 times longer lifetime of the device. Alternatively, such devices could be packaged in smaller footprints, at higher power densities, to make use of this increased effectiveness in heat spreading.

Outlook, future developments

One important finding from the above example is the need to modify device architecture for improved thermal management. The main temperature rise is within the device itself. Here, a thinning of the substrate, to bring it closer to the diamond heat spreader, would further enhance the thermal design. Also, mounting such devices with the active layers facing the diamond would provide even further benefit. An example would be the mounting laser diodes p-face down with the quantum well structures soldered directly against the heat spreader. Another way to bring the device gate junction closer to the diamond is the use of a different substrate altogether. This has been demonstrated by using GaN (Gallium Nitride) on diamond wafers, which remove both the Si substrate and transition layers, replacing them instead with CVD diamond [5]. The result brings the diamond material within 1 micron of the heat generating gate junctions. Initial users of GaN-on-diamond wafers for RF HEMT devices have demon- strated as much as 3 times the power density when compared to equivalent GaN/SiC (Silicon Carbide) devices, today’s leading technology for advanced power devices. [6]

Summary

As can be seen, significant thermal-management improvements to electronic systems can be realized by using advanced materials such as CVD diamond. The integration can be relatively straightforward as the diamond heat spreader can be a direct replacement to AlN (Aluminium nitride), BeO (Berillium oxide) or other advanced ceramics. Attention to detail at the interfaces, both in terms of the choice of metals and its thickness, is important to keep overall thermal resistance low and thereby optimizing the effectiveness of the diamond.

As CVD diamond becomes more attractive as a heat spreader through improved synthesis technology, advanced processing and on-going cost reduction efforts, its use in high power density applications has been increasing. It is expected that this trend will be continued in the years to come in line with the ever increasing need for smaller and more powerful electronic devices and systems.

References

1. R. Balmer, B. Bolliger “Integrating Diamond to Maximize Chip Reliability and Performance,“ in Chip Scale Review, July/August 2013, pp. 26 – 30.
2. Internal Element Six Technologies research and report.
3. Element Six internal thermal simulation, C. Bibbe, 2006.
4. GaN-on-Diamond High-Electron-Mobility Transistor – Impact of Contact and Transition Layers, J.Anaya, J.W. Pomeroy, M. Kuball, Center for Device Thermography and Reliability (CDTR), H. H. Wills Physics Laboratory, University of Bristol, BS8 1TL Bristol, U.K.
5. G.D. Via, J.G. Felbinger, J. Blevins, K. Chabak, G. Jessen, J. Gillespie, R. Fitch, A. Crespo, K. Sutherlin,
B. Poling, S. Tetlak, R. Gilbert, T. Cooper, R. Baranyai, J.W. Pomeroy, M. Kuball, J.J. Maurer, and A. Bar-Cohen,
“Wafer-Scale GaN HEMT Performance Enhancement
by Diamond Substrate Integration” in 10th Interna- tional Conference on Nitride Semiconductors, ICNS-10, August 25-30, 2013, Washington DC, USA.
6. M. Tyhach, D. Altman, and S. Bernstein, “Analysis and Characterization of Thermal Transport in GaN HEMTs on SiC and Diamond Substrates”, in GOMACTech 2014, March 31-April 3, 2014, Charleston, SC, USA.

THOMAS OBELOER, DANIEL TWITCHEN, JULIAN ELLIS, BRUCE BOLLIGER, Element Six Technologies, Santa Clara, CA

MARTIN KUBALL AND JULIAN ANAYA, Center For Device Thermography And Reliability (Cdtr), H. H. Wills Physics Laboratory, University Of Bristol, Bristol, U.K. contact: [email protected]

Interconnecting transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, are where the future limitations in performance, power, latency and cost reside.

BY BILL CHEN, ASE US, Sunnyvale, CA; BILL BOTTOMS, 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG, Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI, Toshiba Kangawa, Japan.

Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly that in the aggregate provides enhanced functionality and improved operating characteristics.

In this definition components should be taken to mean any unit whether individual die, MEMS device, passive component and assembled package or sub‐system that are integrated into a single package. The operating characteristics should also be taken in its broadest meaning including characteristics such as system level cost-of-ownership.

The mission of the ITRS Heterogeneous Integration Focus Team is to provide guidance to industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics that is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the require- ments for heterogeneous integration in the electronics industry through 2030, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.

Background

The environment is rapidly changing and will require revolutionary changes after 50 years where the change was largely evolutionary. The major factors driving the need for change are:

  • We are approaching the end of Moore’s Law scaling.
  • The emergence of 2.5D and 3D integration techniques
  • The emerging world of Internet of Everything will cause explosive growth in the need for connectivity.
  • Mobile devices such as smartphones and tablets are growing rapidly in number and in data communications requirements, driving explosive growth in capacity of the global communications network.
  • Migration of data, logic and applications to the cloud drives demand for reduction in latency while accommodating this network capacity growth.

Satisfying these emerging demands cannot be accomplished with the current electronics technology and these demands are driving a new and different integration approach. The requirements for power, latency, bandwidth/bandwidth density and cost can only be accomplished by a revolutionary change in the global communications network, with all the components in that network and everything attached to it. Ensuring the reliability of this “future network” in an environment where transistors wear out, will also require innovation in how we design and test the network and its components.

The transistors ‘power consumption in today’s network account for less than 10 percent of total power, total latency and total cost. It is the interconnection of these transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, where the future limitations in performance, power, latency and cost reside. Overcoming these limitations will require heterogeneous integration of different materials, different devices (logic, memory, sensors, RF, analog, etc.) and different technologies (electronics, photonics, plasmonics, MEMS and sensors). New materials, manufacturing equipment and processes will be required to accomplish this integration and overcome these limitations.

Difficult challenges

The top‐level difficult challenges will be the reduction of power per function, cost per function and latency while continuing the improvements in performance, physical density and reliability. Historically, scaling of transistors has been the primary contributor to meeting required system level improvements. Heterogeneous integration must provide solutions to the non‐transistor infrastructure that replace the shortfall from the historical pace of progress we have enjoyed from scaling CMOS. Packaging and test have found it difficult to scale their performance or cost per function to keep pace with transistors and many difficult challenges must be met to maintain the historical pace of progress.

In order to identify the difficult challenges we have selected seven application areas that will drive critical future requirements to focus our work. These areas are:

  • Mobile products
  • Big data systems and interconnect
  • The cloud
  • Biomedical products
  • Green technology
  • Internet of Things
  • Automotive components and systems

An initial list of difficult challenges for Heterogeneous Integration for these application areas is presented in three categories; (1) on‐chip interconnect, (2) assembly and packaging and (3) test. These are analyzed in line with the roadmapping process and will be used to define the top 10 challenges that have the potential to be “show stoppers” for the seven application areas identified above.

On-chip interconnect difficult challenges

The continued decrease in feature size, increase in transistor count and expansion into 3D structures are presenting many difficult challenges. While challenges in continuous scaling are discussed in the “More Moore” section, the difficult challenges of interconnect technology in devices with 3D structures are listed here. Note that this assumes a 3D structure with TSV, optical interconnects and passive devices in interposer substrates.

ESD (Electrostatic Discharge): Plasma damage on transistors by TSV etching especially on via last scheme. Low damage TSV etch process and the layout of protection diodes are the key factors.

CPI (Chip Package Interaction) Reliability [Process]: Low fracture toughness of ULK (Ultra Low‐k) dielectrics cause failures such as delamination. Material development of ULK with higher modulus and hardness are the key factors.

CPI (Chip Package Interaction) Reliability [Design]: A layout optimization is a key for the device using Cu/ULK structure.

Stress management in TSV [Via Last]: Yield and reliability in Mx layers where TSV land is a concern.

Stress management in TSV [Via Middle]: Stress deformation by copper extrusion in TSV and a KOZ (Keep Out Zone) in transistor layout are the issues.

Thermal management [Hot Spot]: Heat dissipation in TSV is an issue. An effective homogenization of hot spot heat either by material or layout optimization are the key factors.

Thermal management [Warpage]: Thermal expansion management of each interconnect layer is necessary in thinner Si substrate with TSV.

Passive Device Integration [Performance]: Higher Q, in other words, thicker metal lines and lower tan dielectrics is a key for achieving lower power and lower noise circuits.

Passive Device Integration [Cost]: Higher film and higher are required for higher density and lower footprint layout.

Implementation of Optical Interconnects: Optical interconnects for signaling, clock distribution, and I/O requires development of a number of optical components such as light sources, photo detectors, modulators, filters and waveguides. On‐chip optical interconnects replacing global inter- connects requires the breakthrough to overcome the cost issue.

Assembly and packaging difficult challenges

Today assembly and packaging are often the limiting factors in performance, size, latency, power and cost. Although much progress has been made with the introduction of new packaging architectures and processes, with innovations in wafer level packaging and system in package for example, a significantly higher rate of progress is required. The complexity of the challenge is increasing due to unique demands of heterogeneous integration. This includes integration of diverse materials and diverse circuit fabric types into a single SiP architecture and the use of the 3rd dimension.

Difficult packaging challenges by circuit fabric

  • Logic: Unpredictable hot spot locations, high thermal density, high frequency, unpredictable work load, limited by data bandwidth and data bottle‐necks. High bandwidth data access will require new solutions to physical density of bandwidth.
  • Memory: Thermal density depends on memory type and thermal density differences drive changes in package architecture and materials, thinned device fault models, test & redundancy repair techniques. Packaging must support low latency, high bandwidth large (>1Tb) memory in a hierar- chical architecture in a single package and/or SiP).
  • MEMS: There is a virtually unlimited set of requirements. Issues to be addressed include hermetic vs. non‐hermetic, variable functional density, plumbing, stress control, and cost effective test solutions.
  • Photonics: Extreme sensitivity to thermal changes, O to E and E to O, optical signal connections, new materials, new assembly techniques, new alignment and test techniques.
  • Plasmonics: Requirements are yet to be determined, but they will be different from other circuit type. Issues to be addressed include acousto‐ magneto effects and nonlinear plasmonics.
  • Microfluidics: Sealing, thermal management and flow control must be incorporated into the package.

Most if not all of these will require new materials and new equipment for assembly and test to meet the 15 year Roadmap requirements.

Difficult packaging challenges by material

Semiconductors: Today the vast majority of semiconductor components are silicon based. In the future both organic and compound semiconductors will be used with a variety of thermal, mechanical and electrical properties; each with unique mechanical, thermal and electrical requirements.

Conductors: Cu has replaced Au and Al in many applications but this is not good enough for future needs. Metal matrix composites and ballistic conductors will be required. Inserting some of these new materials will require new assembly, contacting and joining techniques.

Dielectrics: New high k dielectrics and low k dielectrics will be required. Fracture toughness and interfacial adhesion will be the key parameters. Packaging must provide protection for these fragile materials.

Molding compound: Improved thermal conductivity, thinner layers and lower CTE are key requirements.

Adhesives: Die attach materials, flexible conductors, residue free materials needed o not exist today.

Biocompatible materials: For applications in the healthcare and medical domain (e.g. body patches, implants, smart catheters, electroceuticals), semiconductor‐based devices have to be biocompatible. This involves the integration of new (flexible) materials to comply with specific packaging (form factor) requirements.

Difficult challenges for the testing of heterogeneous devices

The difficulties in testing heterogeneous devices can be broadly separated into three categories: Test Quality Assurance, Test Infrastructure, and Test Design Collaboration.

Test quality assurance needs to comprehend and place achievable quality and reliability metrics for each individual component prior to integration, in order to meet the heterogeneous system quality and reliability targets. Assembly and test flows will become inter- twined and interdependent. They need to be constructed in a manner that maintains a cost effective yield loss versus component cost balance and proper component fault isolation and quantification. The industry will be required to integrate components that cannot guarantee KGD without insurmountable cost penalties and this will require integrator visible and accessible repair mechanisms.

Test infrastructure hardware needs to comprehend multiple configurations of the same device to enable test point insertion at partially assembled and fully assembled states. This includes but is not limited to different component heights, asymmetric component locations, and exposed metal contacts (including ESD challenges). Test infrastructure software needs to enable storing and using volume test data for multiple components that may or may not have been generated within the final integrators data domains but are critical for the final heterogeneous system functionality and quality. It also needs to enable methods for highly granular component tracking for subsequent joint supplier and integrator failure analysis and debug.

Test design collaboration is one of the biggest challenges that the industry will need to overcome. It will be a requirement for heterogeneous highly integrated highly functional systems to have test features co‐designed across component boundaries that have more test coverage and debug capability than simple boundary scans. The challenge
of breaking up what was once the responsibility of a wholly contained design for test team across multiple independent entities each trying to protect IP, is only magnified by the additional requirement that the jointly developed test solutions will need to be standardized across multiple competing heterogeneous integrators. Industry wide collaboration on and adherence to test standards will be required in order to maintain cost and time effective design cycles for highly desired components that traditionally has only been required for cross component boundary communication protocols.

The roadmapping process

The objective of ITRS 2.0 for heterogeneous integration is to focus on a limited number of key challenges (10) that have the greatest potential to be “show stoppers,” while leaving other challenges identified and listed but without focus on detailed technical challenges and potential solutions. In this process collaboration with other Focus Teams and Technical Working Groups will be a critical resource. While we will need collaboration with other groups both inside and outside the ITRS some of the collaborations are critical for HI to address its mission. FIGURE 1 shows the major internal collaborations in three categories.

FIGURE 1. Collaboration priorities.

FIGURE 1. Collaboration priorities.

We expect to review these key challenges and our list of other challenges on a yearly basis and make changes so that our focus keeps up with changes in the key challenges. This will ensure that our efforts remain focused on the pre‐competitive technologies that have the greatest future value to our audience. There are four phases in the process detailed below.

1. Identify challenges for application areas: The process would involve collaboration with other focus teams, technical TWGs and other roadmapping groups casting a wide net to identify all gaps and challenges associated with the seven selected application areas as modified from time to time. This list of challenges will be large (perhaps hundreds) and they will be scored by the HI team by difficulty and criticality.

2. Define potential solutions: Using the scoring in phase (1) a number (30‐40) will be selected to identify potential solutions. The remainder will be archived for the next cycle of this process. This work will be coordinated with the same collabo- ration process defined above. These potential solutions will be scored by probable success and cost.

3. Down select to only the 10 most critical challenges: The potential solutions with the lowest probability of success and highest cost will have the potential to be “show stopping” roadblocks. These will be selected using the scoring above and the focus issues for the HI roadmap. The results of this selection process will be commu- nicated to the relevant collaboration partners for their comments.

4. Develop a roadmap of potential solutions for “show stoppers”: The roadmap developed for the “show stopping” roadblocks shall include analysis of the blocking issue and identification of a number of potential solutions. The collaboration shall include detail work with other units of the ITRS, other roadmapping activity such as the Jisso Roadmap, iNEMI Roadmap, Communications Technology Roadmap from MIT. We are continuing to work with the global technical community: industry, research institutes and academia, including the IEEE CPMT Society.

The blocking issues will be specifically investigated by the leading experts within the ITRS structure, academia, industry, government and research organizations to ensure a broad based understanding. Potential solutions will be identified through a similar collaboration process and evaluated through a series of focused workshops similar to the process used by the ERD iTWG. This process is a workshop where there is one proponents and one critic presenting to the group. This is followed by a discussion and a voting process which may have several iterations to reach a consensus.

The cross Focus Team/TWG collaboration will use a procedure of iteration to converge on an understanding of the challenges and potential solutions that is self‐ consistent across the ITRS structure. An example is illustrated in FIGURE 2.

FIGURE 2. Iterative collaboration process

FIGURE 2. Iterative collaboration process

It is critically important that our time horizon include the full 15 years of the ITRS. The work to anticipate the true roadblocks for heterogeneous integration, define potential solutions and implement a successful solution may require the full 15 years. Among the tables we will include 5 year check points of the major challenges for the key issues of cost, power, latency and bandwidth. In order for this table to be useful we will face the challenge of identifying the specific metric or metrics to be used for each application driver as we prepare the Heterogeneous Integration roadmap chapter for 2015 and beyond.

BILL CHEN is a senior technical advisor for ASE US, Sunnyvale, CA; BILL BOTTOMS is President and CEO of 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG is director of business development at Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI works in the Toshiba’s Center for Semiconductor Research & Development, Kangawa, Japan.

A new study coauthored by Wellesley economist, Professor Daniel E. Sichel, reveals that innovation in an important technology sector is happening faster than experts had previously thought, creating a backdrop for better economic times ahead.

The Producer Price Index (PPI) of the United States suggests that the prices of semiconductors have barely fallen in recent years. The slow decline in semiconductor prices stands in sharp contrast to the rapidly falling prices reported from the mid-1980s to the early 2000s, and has been interpreted as a signal of sluggish innovation in this key sector.

The apparent slowdown puzzled Sichel and his coauthors, David M. Byrne of the Federal Reserve Board, and Stephen D. Oliner, of the American Enterprise Institute and UCLA–particularly in light of evidence that the performance of microprocessor units (MPUs), which account for about half of U.S. semiconductor shipments, has continued to improve at rapid pace. After closely examining historical pricing data, the economists found that Intel, the leading producer of MPUs, dramatically changed the way it priced these chips in the mid-2000s–roughly the same time when the slowdown reported by government data occurs. Prior to this period, Intel typically lowered the list prices of older chips to remain competitive with newly introduced chips. However, after 2006, Intel began to keep chip prices relatively unchanged over their life cycle, which affected official statistics.

To obtain a more accurate assessment of the pace of innovation in this important sector, Sichel, Byrne, and Oliner developed an alternative method of measurement that evaluates changes in actual MPU performance to gauge the rate of improvement in price-performance ratios. The economists’ preferred index shows that quality-adjusted MPU prices continued to fall rapidly after the mid-2000s, contrary to what the PPI indicates–meaning that worries about a slowdown in this sector are likely unwarranted.

According to Sichel, these results have important implications, not only for understanding the rate of technological progress in the semiconductor industry but also for the broader debate about the pace of innovation in the U.S. economy.

“These findings give us reason to be optimistic,” said Sichel. “If technical change in this part of the economy is still rapid, it provides hope for better times ahead.”

Sichel and his coauthors also acknowledge that their results raise a new puzzle. “In recent years,” they write, “the price index for computing equipment has fallen quite slowly by historical standards. If MPU prices have, in fact, continued to decline rapidly, why have prices for computers–which rely on MPUs for their performance–not followed suit?” The researchers believe it is possible that the official price indexes for computers may also suffer from measurement issues, and they are investigating this possibility in further work.

“How Fast Are Semiconductor Prices Falling,” coauthored by Daniel E. Sichel, Wellesley College and NBER; David M. Byrne, Federal Reserve Board; and Stephen D. Oliner, American Enterprise Institute and UCLA, is available as an NBER working paper and is online at http://www.nber.org/papers/w21074 and https://www.aei.org/publication/how-fast-are-semiconductor-prices-falling/.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $83.1 billion during the first quarter of 2015, an increase of 6.0 percent compared to the first quarter of 2014. Global sales for the month of March 2015 were $27.7 billion, 6.0 percent higher than the March 2014 total of $26.1 billion and 0.1 percent lower than last month’s total. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Despite macroeconomic challenges, first quarter global semiconductor sales are higher than they were last year, which was a record year for semiconductor revenue,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas region posted its sixth straight month of double-digit, year-to-year growth to lead all regional markets, and DRAM and analog products continue to be key drivers of global sales growth.”

Regionally, sales were up compared to last month in Asia Pacific/All Other (3.1 percent), Europe (2.7 percent), and China (1.0 percent), which is broken out as a separate country in the sales data for the first time. Japan(-0.4 percent) and the Americas (-6.9 percent) both saw sales decrease compared to last month. Compared to March 2014, sales increased in the Americas (14.2 percent), China (13.3 percent), and Asia Pacific/All Other (3.8 percent), but decreased in Europe (-4.0 percent) and Japan (-9.6 percent).

“Congress is considering a legislative initiative called Trade Promotion Authority (TPA) that would help promote continued growth in the semiconductor sector and throughout the U.S. economy,” Neuffer continued. “Free trade is vital to the U.S. semiconductor industry. In 2014, U.S. semiconductor company sales totaled $173 billion, representing over half the global market, and 82 percent of those sales were to customers outside the United States. TPA paves the way for free trade, and Congress should swiftly enact it.”

March 2015
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 6.23 5.80 -6.9%
Europe 2.88 2.95 2.7%
Japan 2.55 2.54 -0.4%
China 7.75 7.83 1.0%
Asia Pacific/All Other 8.33 8.59 3.1%
Total 27.74 27.71 -0.1%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 5.08 5.80 14.2%
Europe 3.08 2.95 -4.0%
Japan 2.81 2.54 -9.6%
China 6.91 7.83 13.3%
Asia Pacific/All Other 8.27 8.59 3.8%
Total 26.15 27.71 6.0%
Three-Month-Moving Average Sales
Market Oct/Nov/Dec Jan/Feb/Mar % Change
Americas 6.73 5.80 -13.8%
Europe 3.01 2.95 -1.7%
Japan 2.80 2.54 -9.1%
China 8.03 7.83 -2.5%
Asia Pacific/All Other 8.57 8.59 0.2%
Total 29.13 27.71 -4.9%

About SIA

Stiff competition in sensors for high-volume design wins and a recovery in actuator growth shuffled the ranking of suppliers in the $9.2 billion market for sensors and actuators in 2014, according to IC Insights’ new 2015 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes. The new O-S-D Report says the overall trend in sensors and actuators is for the largest suppliers to keep getting bigger, gaining marketshare because more high-volume applications—such as smartphones and the huge potential of the Internet of Things (IoT)—and automotive systems require well-established track records for quality, long-term reliability, and on-time delivery of semiconductors.

Sensor leader Robert Bosch in Germany extended its lead in this market with a 16 percent sales increase in 2014 to nearly $1.2 billion. The German company became the first sensor maker to reach $1.0 billion in 2013 when its sales climbed 29 percent, reflecting continued strong growth in its automotive base and expansion into high-volume consumer and mobile applications. Bosch’s marketshare in sensor-only sales grew to 20 percent in 2014 from 18 percent in 2013 and 15 percent in 2012, according to the 10th edition of IC Insights’ annual O-S-D Report.

Meanwhile, STMicroelectronics saw its sensor/actuator sales volume fall 19 percent in 2014 to $630 million, which caused it to drop to fourth place among the market’s top suppliers from second in 2013. ST’s drop was partly caused by marketshare gains by Bosch and U.S.-based InvenSense, which climbed from 14th in 2013 to ninth in the 2014 sensor/actuator ranking with a 33 percent increase in sensor sales to $332 million last year. Bosch and InvenSense sensors—which are made with microelectromechanical systems (MEMS) technology—have knocked ST’s MEMS-based sensors from a number of high-volume smartphones, including Apple’s newest iPhone handsets.

ST’s drop in sensor revenues and modest sales increases in MEMS-based actuators at Texas Instruments (micro-mirror devices for digital projectors and displays) and Hewlett-Packard (mostly inkjet-printer nozzle devices) moved TI and HP up one position in IC Insights’ 2014 ranking to second and third place, respectively (as shown in Figure 1). Infineon remained in fifth place in the sensors/actuator ranking with an 8 percent sales increase to $520 million last year. The 2015 O-S-D Report provides top 10 rankings of suppliers in sensors/actuators, optoelectronics, and discrete semiconductors in addition to a top 30 O-S-D list of companies, based on combined revenue in optoelectronics, sensors/actuators and discretes.

Figure 1

Figure 1

The new O-S-D Report forecasts worldwide sensor sales to increase 7 percent in 2015 to reach a record-high $6.1 billion after growing 5 percent in 2014 to $5.7 billion and rising just 3 percent in 2013.  Total actuator sales are expected to increase 7 percent in 2015 to $3.7 billion, which will tie the record high set in 2011. Actuator sales fell 10 percent in 2012 and dropped another 4 percent in 2013 before recovering in 2014 with a 7 percent increase to $3.5 billion.  MEMS technology was used in about 34 percent of the 11.1 billion sensors shipped in 2014 and essentially all of the 999 million actuators sold last year, based on an analysis in the new O-S-D Report.  Tiny MEMS structures are used in these devices to perform transducer functions (i.e., detecting and measuring changes around sensors for inputs in electronic systems, and initiating physical actions in actuators from electronic signals).

Despite the inventory adjustment caused by LCD TV brands reducing their panel orders in the first quarter (Q1) of 2015, the strong demand for leading TV brands to fulfill their panel facilitation plans — combined with a strong cross-marketing push by TV panel makers — helped LCD TV panel shipments reach a record monthly high in March 2015. According to the latest Monthly TFT LCD Shipment Databasefrom IHS Inc. (NYSE: IHS), a global source of critical information and insight, LCD TV panel shipments from global panel makers reached 23.9 million in March 2015, growing 20 percent month over month and 11 percent year over year.

Panel shipments declined seasonally in Q1 of this year, because most LCD TV modules are manufactured in China and the Chinese New Year holidays in February meant fewer working days in LCD cell fabs in Asia and LCD module lines in China. Meanwhile, as the LCD TV panel supply-demand balance shifted from tightness to oversupply, TV makers have started to reduce orders, especially for older models. However, positive year-over-year growth is still expected, especially since there was such a strong rebound for LCD TV panel shipments in March.

“Although the LCD TV panel demand has shown signs of slowing after the holidays, leading TV brands are preparing their new models for launch, so orders are not diminished,” said Yoonsung Chung, director of large area display research for IHS.  “Meanwhile, panel makers are aggressively introducing 4K resolution, wide color gamut, ultra-slim bezels and other new features, to improve panel shipment growth”

While LCD TV panel shipments reached 253 million units in 2014, panel makers are aggressively targeting 261 million units this year. “Demand will slow, beginning in the second quarter of 2015, and panel prices are already starting to fall, so TV panel shipments may face some growth challenges in the coming months,” Chung said.

IHS_Large-area_shipments_2008-2015_150427

 

LCD shipment growth also varied by size in March, representing a shift in LCD TV size trends. The 23.6-inch display, which is primarily available in emerging regions, shipped a record 2.1 million units. Other display sizes setting records last month were 40-inch displays (3.3 million), 43-inch displays (1.2 million), 49-inch displays (0.9 million), and 65-inch displays (0.4 million).

Led by Samsung Display and LG Display, 4K LCD TV panel shipments grew from 1.7 million in February to a record-setting 2.6 million units in March 2015. Red-green-blue-white (RGBW) pixel-layout technology, which can help reduce power consumption, is expected to rise rapidly in 2015 as the industry’s acceptance of this technology has gradually extended from the Chinese market to the global market.

The Monthly TFT LCD Shipment Database provides the latest panel shipment numbers, surveyed from all large-area panel makers.

Communication and computer systems are forecast to account for the greatest percentage of IC sales in every geographic region—Americas, Europe, Japan, and Asia-Pacific—this year, according to data released in the 2015 edition of IC Insights’ IC Market Drivers, A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits. Communications applications are expected to capture just over 41 percent of IC sales in Asia-Pacific and 39 percent of the revenue in the Americas region this year.  Computer applications are forecast to be the largest end-use market in Japan and Europe, accounting for nearly one-third of ICs sales in both regions in 2015 (Figure 1).

Fig. 1

Fig. 1

Consumer systems are forecast to be the third-largest end-use category for ICs in the Americas, Japan, and Asia-Pacific regions in 2015. In Europe, automotive applications are expected to remain the third largest end-use category for ICs this year.

Collectively, communications, computers, and consumer systems are projected to account for 85.7 percent of IC sales in the Americas this year compared to 77.9 percent in Japan and 90.8 percent in Asia-Pacific. Communications, computer, and automotive applications are forecast to represent 82.3 percent of IC sales in Europe in 2015.

For more than three decades, computer applications were the largest market for IC sales but that changed in 2013 when the global communications IC market took over the top spot due to steady strong growth in smartphones and weakening demand for personal computers. Globally, communications systems are forecast to represent 38.1 percent of the $310.5 billion IC market this year compared to 35.2 percent for computers, and 12.2 percent for consumer (Figure 2). IC sales to the automotive market are forecast to represent only about 8 percent of the total IC sales this year but from 2013-2018, this segment is projected to rise by a compound average growth rate (CAGR) of 10.8%, highest among all the end-use applications.

Fig. 2

Fig. 2

IC Market Drivers 2015—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits examines the largest, existing system opportunities for ICs and evaluates the potential for new applications that are expected to help fuel the market for ICs.

By Paula Doe, SEMI

In this 50th year anniversary of Moore’s Law, the steady scaling of silicon chips’ cost and performance that has so changed our world over the last half century is now poised to change it even further through the Internet of Things, in ways we can’t yet imagine, suggests Intel VP of IoT Doug Davis, who will give the keynote at SEMICON West (July 14-16) this year.  Powerful sensors, processors, and communications now make it possible to bring more intelligent analysis of the greater context to many industrial decisions for potentially significant returns, which will drive the first round of serious adoption of the IoT. But there is also huge potential for adding microprocessor intelligence to all sorts of everyday objects and connecting them with outside information, to solve all sorts of real problems, from saving energy to saving babies’ lives. “We see a big impact on the chip industry,” says Davis, noting the needs to deal with highly fragmented markets, as well to reduce power, improve connectivity, and find ways to assure security.

The end of the era of custom embedded designs?

The IoT may mean the end of the era of embedded chips, argues Paul Brody, IBM’s former VP of IoT, who moves to a new job this month, one of the speakers in the SEMICON West TechXPOT program on the impact of the IoT on the semiconductor sector.  Originally, custom embedded solutions offered the potential to design just the desired features, at some higher engineering cost, to reduce the total cost of the device as much as possible. Now, however, high volumes of mobile gear and open Android systems have brought the cost of a loaded system on a chip with a dual core processor, a gigabit of DRAM and GPS down to only $10.  “The SoC will become so cheap that people won’t do custom anymore,” says Brody. “They’ll just put an SoC in every doorknob and window frame.  The custom engineering will increasingly be in the software.”

Security of all these connected devices will require re-thinking as well, since securing all the endpoints, down to every light bulb, is essentially impossible, and supposedly trusted parties have turned out not to be so trustworthy after all. “With these SoCs everywhere, the cost of distributed compute power will become zero,” he argues, noting that will drive systems towards more distributed processing.  One option for security then could be a block chain system like that used by Bit Coin, which allows coordination with no central control, and when not all the players are trustworthy. Instead of central coordination, each message is broadcast to all nodes, and approved by the vote of the majority, requiring only that the majority of the points be trustworthy.

While much of the high volume IoT demand may be for relatively standard, low cost chips, the high value opportunity for chip makers may increasingly be in design and engineering services for the expanding universe of customers. “Past waves of growth were driven by computer companies, but as computing goes into everything this time, it will be makers of things like Viking ranges and Herman Miller office furniture who will driving the applications, who will need much more help from their suppliers,” he suggests.

Intel Graphics

Source: Intel, 2015

Adding context to the data from the tool

The semiconductor industry has long been a leader in connecting things in the factory, from early M2M for remote access for service management and improving overall equipment effectiveness, to the increased automation and software management of 300mm manufacturing, points out Jeremy Read, Applied Materials VP of Manufacturing Services, who’ll be speaking in another SEMICON West 2015 program on how the semiconductor sector will use the IoT. But even in today’s highly connected fabs, the connections so far are still limited to linking individual elements for dedicated applications specifically targeting a single end, such as process control, yield improvement, scheduling or dispatching.  These applications, perhaps best described as intermediate between M2M and IoT, have provided huge value, and have seen enormous growth in complexity. “We have seen fabs holding 50 TB of data at the 45nm node, increasing to 140 TB in 20nm manufacturing,” he notes.

Now the full IoT vision is to converge this operational technology (OT) of connected things in the factory with the global enterprise (IT) network, to allow new ways to monitor, search and manage these elements to provide as yet unachievable levels of manufacturing performance. “However, we’ve learned that just throwing powerful computational resources at terabytes of unstructured data is not effective – we need to understand the shared CONTEXT of the tools, the process physics, and the device/design intent to arrive at meaningful and actionable knowledge,” says Read.  He notes that for the next step towards an “Internet-of-semiconductor-manufacturing-things” we will need to develop the means to apply new analytical and optimizing applications to both the data and its full manufacturing context, to achieve truly new kinds of understanding.

With comprehensive data and complete context information it will become possible to transform the service capability in a truly radical fashion – customer engineers can use the power of cloud computation and massive data management to arrive at insights into the precise condition of tools, potentially including the ability to predict failures or changes in processing capability. “This does require customers to allow service providers to come fully equipped into the fab – not locking out all use of such capabilities,” he says. “If we are to realize the full potential of these opportunities, we must first meet these challenges of security and IP protection.”

Besides these programs on the realistic impact of the IoT on the semiconductor manufacturing technology sector, SEMICON West 2015, July 14-16 in San Francisco, will also feature related programs on what’s coming next across MEMS, digital health, embedded nonvolatile memory, flexible/hybrid systems, and connected/autonomous cars.  

IHS Technology’s final market share results for 2014 reveal that worldwide semiconductor revenues grew by 9.2 percent in 2014 coming in just slightly below the growth projection of 9.4 percent based on preliminary market share data IHS published in December 2014. The year ended on a strong note with the fourth quarter showing 9.7 percent year-over-year growth.  IHS semiconductor market tracking and forecasts mark the fourth quarter of 2014 as the peak of the annualized growth cycle for the semiconductor industry.

Global revenue in 2014 totaled $354.5 billion, up from $324.7 billion in 2013, according to a final annual semiconductor market shares published by IHS Technology). The nearly double-digit percentage increase follows solid growth of 6.6 percent in 2013, a decline of 2.6 percent in 2012 and a marginal increase of 1.3 percent in 2011. The performance in 2014 represents the highest rate of annual growth since the 33 percent boom of 2010.

“While 2014 marked a peak year for semiconductor revenue growth, the health of both the semiconductor supply base and end-market demand, position the industry for another year of strong growth in 2015,” said Dale Ford, vice president and chief analyst at IHS Technology. “Overall semiconductor revenue growth will exceed 5 percent in 2015, and many component categories and markets will see improved growth over 2014.  The more moderate 2015 growth is due primarily to more modest increases in the memory and microcomponent categories.  The dominant share of semiconductor markets will continue to see vibrant growth in 2015.”

More information on this topic can be found in the latest release of the Competitive Landscaping Tool from the Semiconductors & Components service at IHS.

Top ten maneuvers

Intel maintained its strong position as the largest semiconductor supplier in the world followed by Samsung Electronics and Qualcomm at a strong number two and three position in the rankings.  On the strength of its acquisition of MStar, MediaTek jumped into the top 10 replacing Renesas Electronics at number 10.  The other big mover among the top 20, Avago Technologies, also was boosted by an acquisition, moving up nine places to number 14 with its acquisition of LSI in 2014.

Strategic acquisitions continue to play a major role in shaping both the overall semiconductor market rankings and establishing strong leaders in key semiconductor segments.  NXP and Infineon will be competing for positions among the top 10 semiconductor suppliers in 2015 with the boost from their mergers/acquisitions of Freescale Semiconductor and International Rectifier, respectively.

Among the top 25 semiconductor suppliers, 21 companies achieved growth in 2014.  Out of the four companies suffering declines, three are headquartered in Japan as the Japanese semiconductor market and suppliers continue to struggle.

Broad-based growth

As noted in the preliminary market share results, 2014 was one of the healthiest years in many years for the semiconductor industry.  Five of the seven major component segments achieved improved growth compared to 2013 growth. All of the major component markets saw positive growth in 2014.  Out of 128 categories and subcategories tracked by IHS, 73 percent achieved growth in 2014.  The combined total of the categories that did not grow in 2014 accounted for only 8.1 percent of the total semiconductor market.

Out of more than 300 companies included in IHS semiconductor research, nearly 64 percent achieved positive revenue growth in 2014.  The total combined revenues of all companies experiencing revenue declines accounted for only roughly 15 percent of total semiconductor revenues in 2014.

Semiconductor strength

Memory still delivered a strong performance driven by continued strength in DRAM ICs. However, memory market growth declined by a little more than 10 percent compared to the boom year of 2013 with over 28 percent growth in that year.  Growth in sensors & actuators came in only slightly lower than 2013.

Microcomponents achieved the strongest turn around in growth moving from a -1.6 percent decline in 2013 to 8.9 percent growth in 2014.  It also delivered the best growth among the major segments following memory ICs.  Even Digital Signal Processors (DSPs) achieved positive growth in 2014 following strong, double-digit declines in six of the last seven years.  MPUs lead the category with 10.7 percent growth followed by MCUs with 5.4 percent growth.

Every application market delivered strong growth in 2014 with the exception of Consumer Electronics.  Industrial Electronics lead all segments with 17.8 percent growth.  Data Processing accomplished the strongest improvement in growth as it grew 13.7 percent, up nearly 10 percent from 2014.  Of course, MPUs and DRAM played a key role in the strength of semiconductor growth in Data Processing.  The third-strongest segment was Automotive Electronics which was the third segment with double-digit growth at 10 percent.  Only Wireless Communications saw weaker growth in 2014 compared to 2013 as its growth fell by roughly half its 2013 level to 7.8 percent in 2014.

IC Insights will release its April Update to the 2015 McClean Report later this month. The Update includes the final 2014 company sales rankings for the top 50 semiconductor and top 50 IC companies, and the leading IC foundries. Also included are 2014 IC company sales rankings for various IC product segments (e.g., DRAM, MPU, etc.).

In 2014, there were only two Japanese companies—Toshiba and Renesas—that were among the top 10 semiconductor suppliers (Figure 1). Assuming the NXP/Freescale merger is completed later this year, IC Insights forecasts that Toshiba will be the lone Japanese company left in the top 10 ranking. Anyone who has been involved in the semiconductor industry for a reasonable amount of time realizes this is a major shift and a big departure for a country that once was feared and revered when it came to its semiconductor sales presence in the global market.

Fig 1

Fig 1

Figure 1 traces the top 10 semiconductor companies dating back to 1990, when Japanese semiconductor manufacturers wielded their greatest influence on the global stage and held six of the top 10 positions.  The six Japanese companies that were counted among the top 10 semiconductor suppliers in 1990 is a number that has not been matched by any country or region since (although the U.S. had five suppliers in the top 10 in 2014). The number of Japanese companies ranked in the top 10 in semiconductor sales slipped to four in 1995, fell to three companies in 2000 and 2006, and then to only two companies in 2014.

Figure 1 also shows that, in total, the top 10 semiconductor sales leaders are making a marketshare comeback. After reaching a marketshare low of 45 percent in 2006, the top 10 semiconductor sales leaders held a 53 percent share of the total semiconductor market in 2014.  Although the top 10 share in 2014 was eight points higher than in 2006, it was still six points below the 59 percent share they held in 1990.  As fewer suppliers are able to achieve the economies of scale needed to successfully invest and compete in the semiconductor industry, it is expected that the top 10 share of the worldwide semiconductor market will continue to slowly increase over the next few years.