Tag Archives: letter-pulse-top

Adlyte Inc., a developer of high-brightness extreme light sources for advanced semiconductor inspection and metrology applications, today announced it has reached a key performance benchmark for its extreme ultraviolet (EUV) light source for high-volume manufacturing (HVM)-readiness. Adlyte has demonstrated that its EUV light source has maintained clean operation after intermediate focus while running for hundreds of hours replicating multiple parameters for a production environment—including power, brightness and uptime—established by mask inspection original equipment manufacturers (OEMs).

Adlyte Inc.'s LPP (Laser Produced Plasma) sources produce high-brightness EUV light by focusing a pulsed laser on high frequency droplets of tin.

Adlyte Inc.’s LPP (Laser Produced Plasma) sources produce high-brightness EUV light by focusing a pulsed laser on high frequency droplets of tin.

One of three laser produced plasma (LPP) EUV light-source suppliers in the world, Adlyte is the only one focused on developing light sources for photomask and wafer inspection applications, which are critical for manufacturing future generations of advanced semiconductor devices.

“Mask inspection is a critical part of the EUV lithography infrastructure, and having actinic or ‘at wavelength’ exposure that meets several key criteria, including cleanliness, is the optimal solution for finding the defects that matter on EUV masks,” stated Hidehiro Watanabe, general manager, EUVL Infrastructure Development Center (EIDEC). “We are pleased with the cleanliness we measured on Adlyte’s light source under conditions that replicate a production environment. This meets our requirements for blank mask inspection.”

“Working with our customers and industry partners, Adlyte is committed to advancing the EUV roadmap and helping to enable the production of defect-free EUV masks,” stated Daniel Boehringer, chairman of the board at Adlyte. “We are very encouraged with the latest results we achieved against the cleanliness benchmark established by mask inspection OEM companies. This is testament to the significant investments we’ve made in developing our light-source technology.”

Importance of “clean” EUV light sources

Extremely small nanometer-scale defects on EUV masks and patterned wafers can result in catastrophic yield losses. High-brightness EUV light sources are needed to detect and capture these defects with high throughput and uptime. As with EUV lithography, the clean operation of light sources for EUV mask and wafer inspection/metrology equipment is very important to achieving higher production efficiency and lower cost of ownership.

LPP sources provide a platform that can achieve high brightness and power operation but have historically been challenged in providing the cleanliness needed for HVM applications. Following its previous achievements of meeting the high-source-brightness (250 Watts/mm2 steradian) and power (20 Watts of power into 2 pi) specifications for EUV mask inspection, Adlyte has now demonstrated the required light-source cleanliness needed after the intermediate focus for implementing EUV photomask inspection in HVM.

Adlyte will present these and other EUV light-source technology developments at the 2014 International Workshop on EUV and Soft X-Ray Sources in Dublin, Ireland, November 3-6.

Gigaphoton Inc., a lithography light source manufacturer, announced today that it has succeeded in achieving 3-hour continuous operation of its prototype LPP EUV light source at 50 percent duty cycle and 42-W output, equivalent to usage in a high-volume-manufacturing (HVM) environment.

The 3-hour continuous operation under such HVM environment as above was achieved by irradiating an Sn target (tin droplet) with a solid-state pre-pulse laser and a CO2 laser after combining and optimizing these lasers. Achievement of 3-hour continuous operation at a duty cycle of 50 percent with the high output of 42 W is proof that the development of HVM EUV scanners has entered its final stage. Gigaphoton remains committed to continuing its R&D efforts, and is targeting around-the-clock operation at 150-W output and 250-W output for high-volume manufacturing by the end of 2014 and 2015, respectively.

Related news: IBM announces EUV benchmark

The prototype LPP light source attains the emission of EUV by radiating ultra-small tin (Sn) droplets of less than 20 μm in diameter with a solid-state pre-pulse laser and main-pulse CO2 laser. Additionally, to maximize the life of the collector mirror, a high-output superconducting magnet generates a powerful magnetic field that guides unwanted debris produced by thermal expansion of the tin droplets towards the tin catcher. Moreover, use of Sn target droplets of less than 20 µm in diameter allows prolongation of the droplet generator life as well as reduction of downtime and cost.

“Our success in 3-hour continuous operation of the prototype LPP EUV light source at 50 percent duty cycle and 42-W output is clear evidence that achievement of a high-performance LPP EUV light source capable of stable operation at higher output and lower running cost will soon be completed,” said Hitoshi Tomaru, president and CEO of Gigaphoton, “I am confident that Gigaphoton’s expertise and efforts to develop an LPP light source that accelerates development of HVM EUV scanners will enable earlier introduction of these scanners as next-generation lithography tools.”

Gigaphoton will present the latest status of its EUV light source development at the 2014 International Symposium on Extreme Ultraviolet Lithography, which will be held in Washington, DC on October 27 through 29. The company will also co-sponsor this 2014 EUVL symposium.

This utilizes the achievement of a program subsidized by NEDO（New Energy and Industrial Technology Development Organization).

A system is described that mitigates unintended oxide growth for bare wafers while in-process storage and potentially post process at tools using nitrogen purge. 

BY SURESH BILIGIRI, Rorze Automation, Fremont, CA 

Unintended oxide growth on wafers while in storage or while in process is an important cause of excess process variability that can lead to poor yield and product quality.

To understand and eliminate the undesired oxide growth on wafers while in storage or between processes, we evaluated and compared wafers storied in a nitrogen-based environment to wafers stored in normal cleanroom environment. Important issues to consider:

  • A typical wafer goes through a clean cycle prior to wafer moves.
  • There are waste chemical handling costs involved in the handling, treatment and disposal of waste chemicals.
  • If the oxide growth are uncertain, then metrology of these wafer before wafer move has to be performed and this adds more cost to the process.
  • If the oxide growth has exceeded the specification, then a second re-cleaning cost is added to the process.
  • Due to stringent environmental controls and corporate responsibility in green initiatives the cost of handling the waste chemicals will have an impact of greater than twice the first cleaning.
  • Each time a wafer is handled, the risk of loss increases causing an impact on yield.
  • In a high demand situation where the fab utilization is approaching the high numbers, the re-clean adds costs and a negatively impacts production volumes.

In order to assess the impact of the unintended oxide growth, tests were conducted at a semiconductor manufacturing fab using a standard bare wafer stocker (BWS600 by Rorze) and a nitrogen purge type stocker (BWS1600 N2 by Rorze). The wafers were removed from each to test for oxide growth and returned to storage after measuring. The tests were repeated with the same set of wafers and data is shared here.

The Rorze BWS1600 N2 consists of wafer PODS (about the size of a FOUP) that are stacked on a carousal. Each POD with 25 wafers is purged with N2 continually. In order to minimize the use of nitrogen and to create a very low O2 level, the POD has independent access door for each wafer slot on the POD (9mm door). This method (Rorze patent pending) offers N2 environment for wafers inside even during the wafer transfer from and to the POD with minimum ambient air interaction. The system and the storage method is shown in FIGURE 1.

FIGURE 1. The design is executed for minimal consumption of N2 as well as to mitigate the hazards of excess N2 in the fab.

FIGURE 1. The design is executed for minimal consumption of N2 as well as to mitigate the hazards of excess N2 in the fab.

FIGURES 2 and 3 shows the N2 and O2 purging sequence data. Note that:

  1. When the shutter is open, O2 density will be increased because of mixture of air of mini- environment (FFU) is forced into the POD/ container environment.
  2. When the shutter is open, N2 gas supply volume will be increased from 5 L/min to 20 L/min from the POD that helps to reduce O2 density inside the POD.
  3. At any given time, when the shutter is open, even with the strong FFU flow as the wafer on end-effector directs flow from FFU the N2 concentration in the POD does not go above 5000 PPM
FIGURE 2. O2 density during wafer handling.

FIGURE 2. O2 density during wafer handling.

FIGURE 3. N2/oxygen density data during storage conditions.

FIGURE 3. N2/oxygen density data during storage conditions.

The results of the oxide growth measurements on wafers stored in N2 environment (Rorze BWS1600 N2) were obtained on a regular frequency (Day 1, 3, 6, 7 10, 14 & 21).

Measurements were made using “Rudolph S3000A” metrology thicknesstool.Toensure the effect is uniform across the stored area, wafers were placed in different PODS inside (C8 is at top on the carousal close to FFU and C1 is farthest from FFU at the bottom).

An identical test method was executed by storing wafers in a bare wafer storage unit where wafer was exposed to the fab environment but in a clean storage area. (Rorze BWS600)

Results of the tests are shown in FIGURE 4. Wafers were set at different locations in the stocker to test the influence of storage location on rate of oxide growth. We found no noticeable difference in oxide growth for different cassettes. Even after 21 days with intermittent extraction to monitor growth (every three days), all wafers had less than 1.7 Anstrom thickness oxide growth. The impact of oxide growth without intermittent exposure could be much smaller.

FIGURE 4. Oxide growth is small even after 21 days.

FIGURE 4. Oxide growth is small even after 21 days.

Cost analysis

As per an earlier Sematech model that takes into account the cost of materials, capital tool costs, uptime in the fab etc. for wafer clean per wafer pass following were the costs estimated and noted below. (Data reference provide by Mr. Rob Randhawa, Founder & CEO of Planar Semiconductor)

  • Single wafer cleaning cost per wafer using DI water based cleaning only: $1.90 per wafer – 300mm wafer
  • Single wafer cleaning cost per wafer using standard chemicals without the IPA: $2.30 per wafer – 300mm wafer
  • Single wafer cleaning cost per wafer using standard chemicals + IPA: $ 3.60 per wafer – 300mm wafer – This includes the reprocess cost of IPA

Based on the initial results we see, there is a substantial benefit to employ this technology that will help to make strides in continuing to help on cost controls while the technology node advances. The opportunity to eliminate the risk of oxide growth can potentially go beyond the wafer clean and to “in-process storage” where a wafer lot is in queue for the next step. There is a risk of delay where the wafer could continue to gain oxide growth resulting in potential yield loss and a domino effect of reduced productivity and a risk of not meeting demand.

As technology proceeds to smaller nodes, the tolerance for variations within atomic layers are not acceptable as it will impact performance and yield, necessitating such products and technologies to keep the cost down.

Tools such as the N2 purged bare wafer stocker can save anywhere from about $900,000 to about $1.7 million per year and easily pay off the cost of the system within a year or two.

Acknowledgements

Rob Randhawa, Founder and CEO of Planar semicon- ductor for sharing wafer cleaning costs, K.Sakata, Design Engineering Manager, at Rorze Corporation for technical details of the BWS1600/BWS3200 N2 purge system.

A novel metal gate integration scheme to achieve precise threshold voltage (VT) control for multiple VTs is described. 

BY NAOMI YOSHIDA, KEPING HAN, MATTHEW BEACH, XINLIANG LU, RAYMOND HUNG, HAO CHEN, WEI TANG, YU LEI, JING ZHOU, MIAO JIN, KUN XU, ANUP PHATAK, SHIYU SUN, SAJJAD HASSAN, SRINIVAS GANDIKOTA, CHORNG-PING CHANG and ADAM BRAND, Applied Materials, Santa Clara, CA 

At very small process geometries, precise control of electrical conductivity is difficult to maintain. The industry requires a viable replacement-gate FinFET architecture to continue scaling high performance CMOS [1, 2] technology and designs. Furthermore, cost-effective and precise VT control to achieve multiple VTs is essential for future ULSI fabrication to achieve optimal power consumption and performance.

In this study, using WFM full fill and combining two techniques — the novel metal composition and ion implantation into the WFM process, we successfully realized three critical aspects for the metal gate for 10 nanometer and beyond. These are: 1) precise effective work function (eWF) control over a 600 millivolt (mV) tuning range to achieve multiple VT, 2) maintaining conductivity for a sub-15 nanometer gate trench, and 3) compatibility to the self-aligned contact (SAC).

A metal oxide semiconductor capacitor (MOSCAP) was used to evaluate the impact of the metal compo- sition and beam line ion implantation on eWF. Ion implantation was performed for some of the samples after high-k dielectric and work function metal deposition on blanket wafers. High frequency capacitance voltage (HFCV) and current voltage (IV) measurements were recorded for the MOSCAP samples. A single damascene structure was used to measure sub-20 nanometer line resistance. A planar MOSFET was also used for evaluating impact on VT and variability.

Work function modulation

FIGURE 1 shows eWF with three compositions of NMOS WF metals (nWFM) compared with RF-PVD titanium aluminum (TiAl) that was used as the nWFM reference metal. Results demon- strated that the difference between the highest and lowest WF was 550 mV and is attributed to the ALD TiAl composition. Nitrogen ion implantation into the ALD TiAl enabled further WF tuning by 100-150 mV steps. This made possible a WF range from near the Si conduction band edge of 4.1 electron volts (eV) for NMOS low VT to above mid-gap 4.7 eV. The WF shift corresponded well to the different dose levels; therefore we demonstrated that ion implantation can be used to pinpoint the target WF. In addition, we found that ion implantation into ALD TiAl does not degrade the gate leakage current and effective oxide thickness (EOT) performance.

FIGURE 1. nWFM composition impact on eWF.

FIGURE 1. nWFM composition impact on eWF.

Maintaining metal gate conductance for 10nm node

According to the ITRS roadmap, a gate length of 17 nanometers is expected for the 10 nanometer technology node [3]. The problem is that after the high-k cap and etch stop depositions, the gate will have limited space left for the metal fill process [4]. One solution is to fully or mostly fill the trench with WF metal. Using an advanced ALD TiAl deposition process, we were able to fill 13 nanometer wide trenches without any gapfill voids. FIGURE 2 shows the extendible conductance of the ALD TiAl and WF fill process.

FIGURE 2. Conductance curves of various metals filling small trenches.

FIGURE 2. Conductance curves of various metals filling small trenches.

It is known that NMOS low WF metals are more prone to oxidization than high WF PMOS films such as titanium nitride (TiN) and that air exposure affects VT control [5]. In our study, degradation on the conductance curves from air exposure was also observed (FIGURE 3). The air exposed sample showed a large offset of the conductance curve to the right while maintaining the slope, i.e. differential resistivity. The TEM (FIGURE 4) shows an additional layer between the TiN barrier and ALD TiAl. Scanning transmission electron microscope- electron energy loss spectroscopy analysis confirmed high oxygen in the white interface. Thus, it is critical to have an in situ ALD TiAl process on the high k TiN cap to maintain conductivity for the 10 nanometer node.

FIGURE 3. Effect of air exposure in between TiN barrier and nWF metal on conductance below 30 nanometers.

FIGURE 3. Effect of air exposure in between TiN barrier and nWF metal on conductance below 30 nanometers.

FIGURE 4. TEM images at interface of TiN barrier and nWFM. The ex situ sample shows oxidized interface by air exposure.

FIGURE 4. TEM images at interface of TiN barrier and nWFM. The ex situ sample shows oxidized interface by air exposure.

Self-aligned contact compatibility and CMOS VT tuning

At the 22 nanometer technology node, a metal gate SAC is necessary to scale contacted gate pitch [1]. This requires a well-controlled etch back of the metal gate, with subsequent capping of the etch stop material such as silicon nitride (SiN) to prevent contact to gate shorts. Tungsten (W) has been used in volume production because it offers a robust etch back process. In our study, we demonstrated that a controlled recess etch can be achieved with the more conductive TiAl fill compared to W (FIGURE 5). In addition, after metal etch back, a SAC cap was successfully formed with a high density plasma (HDP) SiN fill and chemical mechanical planarization (CMP).

FIGURE 5. Cross-sectional TEM images show controlled etch back of ALD TiAl fill metal gate for SAC integration. The left and middle images after recess etch-back. The right image is after Cap Nitride CMP.

FIGURE 5. Cross-sectional TEM images show controlled etch back of ALD TiAl fill metal gate for SAC integration. The left and middle images after recess etch-back. The right image is after Cap Nitride CMP.

Multiple WF metals need to be integrated for CMOS VT tuning for NMOS and PMOS. In our study we examined the CMOS ALD TiAl flow for four VT tunings. From the results, we propose a new process flow: 1) after the high-k and etch stop layer deposition steps, a fully clustered barrier TiN and nWFM be deposited. Some areas can be masked by photoresist (PR) and the exposed area modified by ion implantation. 2) Etch off the first nWF layer from the PMOS areas. 3) Deposit the second WF (N-3) and barrier. 4) Perform second ion implantation to shift the WF of the third device. 5) Lastly, ALD TiAl is again etched off from the PMOS area WFM (TiN), followed by W or Al fill to fill the remaining gap. The last TiN material serves as the highest WF as well as the barrier layer for W or Al. This flow provides four VTs and metal fill with a clustered nWFM film stack.

Conclusion

Metal WF modulation for VT tuning using a new scheme tunable in the range of 600 mV was successfully demonstrated for 10 nanometer CMOS integration. Ion implantation dose control enabled continuous WF tuning for multiple VT targets. Metal gate conductance data showed the benefit of in situ processing with a TiN barrier and NMOS WF metal. Based on the results, a CMOS flow with NMOS WF-first was proposed for multi-VT tuning.

References

1. C. Auth et al., VLSI Tech. Sym. Dig., p. 131, (2012)
2. P. Packan et al., IEDM Tech. Dig., p. 659, (2009)
3. ITRS Roadmap 2011 Edition
4. N. Yoshida, et al., VLSI Tech. Sym. Dig., p. 81, (2012) 5. A. Veloso, et al., VLSI Tech. Sym. Dig., p. 33, (2012)

Scientists have been laboring to detect cancer and a host of other diseases in people using promising new biomarkers called “exosomes.” Indeed, Popular Science magazine named exosome-based cancer diagnostics one of the 20 breakthroughs that will shape the world this year. Exosomes could lead to less invasive, earlier detection of cancer, and sharply boost patients’ odds of survival.

“Exosomes are minuscule membrane vesicles — or sacs — released from most, if not all, cell types, including cancer cells,” said Yong Zeng, assistant professor of chemistry at the University of Kansas. “First described in the mid-’80s, they were once thought to be ‘cell dust,’ or trash bags containing unwanted cellular contents. However, in the past decade scientists realized that exosomes play important roles in many biological functions through capsuling and delivering molecular messages in the form of nucleic acids and proteins from the donor cells to affect the functions of nearby or distant cells. In other words, this forms a crucial pathway in which cells talk to others.”

While the average piece of paper is about 100,000nm thick, exosomes run just 30 to 150nm in size. Because of this, exosomes are hard to separate out and test, requiring multiple-step ultracentrifugation — a tedious and inefficient process requires long stretches in the lab, according to scientists.

“There aren’t many technologies out there that are suitable for efficient isolation and sensitive molecular profiling of exosomes,” said Zeng.  “First, current exosome isolation protocols are time-consuming and difficult to standardize. Second, conventional downstream analyses on collected exosomes are slow and require large samples, which is a key setback in clinical development of exosomal biomarkers.”

Now, Zeng and colleagues from the University of Kansas Medical Center and KU Cancer Center have just published a breakthrough paper in the Royal Society of Chemistry journal describing their invention of a miniaturized biomedical testing device for exosomes. Dubbed the “lab-on-a-chip,” the device promises faster result times, reduced costs, minimal sample demands and better sensitivity of analysis when compared with the conventional bench-top instruments now used to examine the tiny biomarkers.

“A lab-on-a-chip shrinks the pipettes, test tubes and analysis instruments of a modern chemistry lab onto a microchip-sized wafer,” Zeng said. “Also referred to as ‘microfluidics’ technology, it was inspired by revolutionary semiconductor electronics and has been under intensive development since the 1990s. Essentially, it allows precise manipulation of minuscule fluid volumes down to one trillionth of a liter or less to carry out multiple laboratory functions, such as sample purification, running of chemical and biological reactions, and analytical measurement.”

Zeng and his fellow researchers have developed the lab-on-a-chip for early detection of lung cancer — the number-one cancer killer in the U.S. Today, lung cancer is detected mostly with an invasive biopsy, after tumors are larger than 3 centimeters in diameter and even metastatic, according to the KU researcher.

Using the lab-on-a-chip, lung cancer could be detected much earlier, using only a small drop of a patient’s blood.

“Most lung cancers are first diagnosed based on symptoms, which indicate that the normal lung functions have been already damaged,” Zeng said. “Unlike some cancer types such as breast or colon cancer, no widely accepted screening tool has been available for detecting early-stage lung cancers. Diagnosis of lung cancer requires removing a piece of tissue from the lung for molecular examination. Tumor biopsy is often impossible for early cancer diagnosis as the developing tumor is too small to see by the current imaging tools. In contrast, our blood-based test is minimally invasive, inexpensive, and more sensitive, thus suitable for large population screening to detect early-stage tumors.”

Zeng said the prototype lab-on-a-chip is made of a widely used silicone rubber called polydimethylsiloxane and uses a technique called “on-chip immunoisolation.”

“We used magnetic beads of 3 micrometers in diameter to pull down the exosomes in plasma samples,” Zeng said. “In order to avoid other interfering species present in plasma, the bead surface was chemically modified with an antibody that recognizes and binds with a specific target protein — for example, a protein receptor — present on the exosome membrane. The plasma containing magnetic beads then flows through the microchannels on the diagnostic chip in which the beads can be readily collected using a magnet to extract circulating exosomes from the plasma.”

Beyond lung cancer, Zeng said the lab-on-a-chip could be used to detect a range of potentially deadly forms of cancer.

“Our technique provides a general platform to detecting tumor-derived exosomes for cancer diagnosis,” he said. “In addition to lung cancer, we’ve also tested for ovarian cancer in this work. In theory, it should be applicable to other types of cancer. Our long-term goal is to translate this technology into clinical investigation of the pathological implication of exosomes in tumor development. Such knowledge would help develop better predictive biomarkers and more efficient targeted therapy to improve the clinical outcome.”

Zeng’s collaborators on the investigation were Mei He, Jennifer Crow, Marc Roth and Andrew K. Godwin of the Department of Pathology and Laboratory Medicine at the University of Kansas Medical Center.

The research by Zeng and his KU colleagues recently merited a $640,000 grant from the National Cancer Institute at the National Institutes of Health, intended to further develop the lab-on-a-chip technology.

A Portland, Oregon jury today delivered a verdict in favor of Mentor Graphics in a patent infringement trial against Synopsys, Inc., awarding Mentor Graphics $35 million in damages and royalties.

The jury in the United States District Court for the District of Oregon found that one Mentor patent – U.S. Patent No. 6,240,376 – was directly and indirectly infringed by EVE and Synopsys.  As part of the verdict, the jury awarded damages of approximately $36 million and certain royalties to be paid to Mentor Graphics.

Four other Mentor patents were dismissed from the case prior to the trial. Synopsys said it plans to appeal the jury’s verdict.

The 2014 Nobel Prize for physics awarded today to three physicists for their invention of blue light-emitting diodes (LED) led to a significant breakthrough and paved the way for the creation of white light—a cleaner, more energy-efficient and longer-lasting source of illumination that also has generated a multibillion-dollar market and the creation of hundreds of thousands of jobs, according to IHS Technology.

Following the invention of blue LEDs by Isamu Akasaki, Hiroshi Amano and Shuji Nakamura, white light could finally be achieved—either through a combination with previously invented red and green LEDs; or as more commonly seen today, by adding a yellow phosphor layer over the blue LED. Without blue diodes, white light could not be produced.

Since the trailblazing invention of blue LEDs in the early 1990s the LED component market has flourished, reaching an estimated $17.7 billion in 2013, as shown in the attached figure, and supporting more than 250,000 jobs in the industry. The overall market would be even bigger if it included all the LED downstream markets, such as lighting, displays, signage, consumer electronics and even Christmas lights.

2014-10-07_LEDs

William Rhodes, research manager for LEDs and lighting at IHS, said that the invention of Akasaki, Amano and Nakamura was a game-changer.

“Before the invention of blue LEDs, the market was mainly focused on indicator lights in toys, industrial and automotive applications,” Rhodes observed. “Since then the market has evolved with more than 90 percent of all displays sold this year backlit by LEDs, and LEDs will account for 32 percent of all bulb sales and revenue in 2014.”

The LED lighting market is poised for strong growth in the next five to 10 years with energy-hungry technologies being systematically banned across the world. In particular, consumers and business owners alike are increasingly looking for energy-efficient lighting for their homes and offices to replace energy hogs such as incandescent bulbs, which can use as much as six times the amount of electricity compared to LEDs.

All of this would not be possible without the ground-breaking work of this year’s Nobel Prize physics winners Akasaki, Amano and Nakamura, Rhodes said.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that John P. Daane, President, CEO, and Chairman of the Board of Altera, has been named the 2014 recipient of SIA’s highest honor, the Robert N. Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the U.S. semiconductor industry in technology or public policy. Daane will accept the award at SIA’s annual award dinner on Thursday, Nov. 13.

“For many years, John Daane has been one of the semiconductor industry’s strongest and most influential leaders,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “John represents the heart and soul of our industry and the glue that has strengthened our association. Throughout his career, John has brought together our industry’s leaders to tackle challenges and advance core industry priorities. His leadership has helped the semiconductor industry create jobs, boost economic growth, and maintain America’s global technology leadership. On behalf of the SIA board of directors, it is a privilege to announce John’s selection as the 2014 Robert N. Noyce Award recipient in recognition of his outstanding accomplishments.”

Daane has served as Altera’s president and CEO since November 2000 and was named chairman of the board in May 2003. Prior to joining Altera, Daane spent 15 years at LSI Logic, a semiconductor manufacturer, most recently as executive vice president, communications products group. Daane earned a Bachelor’s Degree from the University of California, Berkeley.

“I am honored and humbled to be selected by my friends and colleagues to receive this award and to join the company of previous Noyce recipients, individuals who are recognized as some of the semiconductor industry’s greatest pioneers and champions,” said Daane. “Perhaps our industry’s greatest strength is our ability to continuously and relentlessly look forward – to the next great achievement or innovation. It is in that spirit that I gratefully accept this award and look forward to helping build an even stronger semiconductor industry.”

The Noyce Award is named in honor of semiconductor industry pioneer Robert N. Noyce, co-founder of Fairchild Semiconductor and Intel.

Last month, Yole Développement  announced the update of its technology and market analysis, LED Packaging Technology & Market Trends. Under this new report, the research market and strategy consulting company highlights the impact of advanced packaging technologies in the LED industry.

“The combination of cost reduction and advanced packaging technologies such as Flip Chip and Chip Scale Package, is changing the LED industry landscape, especially its supply chain,” Yole announced.  For example, introduction of Chip Scale Package solution clearly reduces the number of manufacturing steps: today, some LED chip manufacturers, with Chip Scale Package technology already supply their products to the LED module makers directly.

LED packaging

Flip Chip technology has step by step attracted attention from the lighting, backlighting and flash markets, becoming one the most important developing items this year. Following the LED TV crisis and with the entry of Chinese players, positioning has been reshuffled in the LED industry. The product quality of Chinese LED manufacturers has increased to a level where they are now real competitors for all players. In such a highly competitive environment, three major challenges lie ahead for the LED industry regarding the General Lighting market: efficacy improvement, cost decrease and color consistency increase.

To answer these challenges, several players have now turned to Flip Chip (FC) LED, as these components present several advantages over traditional horizontal (MESA) and vertical LEDs: they are wire-bonding free, can be driven at higher current, and have a smaller size package (…).

And although the FC LED technology has been launched for quite a long time by Lumileds, it was restricted from “popularization” due to technical / technological barriers (low yield regarding bumping / eutectic process…). Additionally, the financial investment required for packaging equipment, represented a strong barrier in an industry that was still recovering.

At middle and long term, this technology [CSP] could make chip manufacturers supply directly to module manufacturers.

But the technology has gradually attracted attention from the lighting, backlighting and flash markets, becoming one the most important developing items this year.

“Whereas Flip Chip LED represented only 11 percent of overall high power LED packaging in 2013, we expect this component to represent 34 percent by 2020. Flip Chip LED will take market share from vertical LED that will represent 27 percent of overall high power LED packages by 2020,” said Pars Mukish, Senior Market & Technology Analyst, LED, Lighting Technologies, Compound Semiconductors and OLEDs.

In addition to offering an increased “performance / cost” ratio, Flip Chip LEDs are also a key enabling technology for the development of Chip Scale Package (CSP) that could allow for further cost reduction.

CSPs are novel to the LED industry but they are the mainstay of the semiconductor industry. Development of CSPs in the Silicon ICs was driven by miniaturization, improved thermal management, higher reliability, and simply the need to connect to an ever increasing pin-count on an ever shrinking die. Chip Scale packages also enabled a reduction in device parasitic and allowed for ease of integration into Level 2 packaging (e.g.: module packaging for LED). It is therefore a natural evolution for this packaging innovation to proliferate into other industries (such as the LED industry).
Basically, a CSP represents a single chip direct mountable package that is the same size as the chip. Regarding LED devices, CSPs are made of a blue FC LED die on which a phosphor layer is coated (the main application of such package being General Lighting). CSP presents several advantages such as: miniaturized size, better thermal contact to substrate. However, eliminating several process steps of traditional LED packaging, CSPs are also having an impact on the industry structure with some LED chip manufacturers supplying their products directly to LED module manufacturers. At middle and long term, this technology could make chip manufacturers supply directly to module manufacturers.

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This forecast provides an outlook for the demand in silicon units for the period 2014-–2016. The results show polished and epitaxial silicon shipments totaling 9,410 million square inches in 2014; 9,840 million square inches in 2015; and 10,163 million square inches in 2016 (refer to table below). Total wafer shipments this year are expected to finally exceed the market high set in 2010 and are forecast to continue shipping at record levels in 2015 and 2016.

“Silicon shipment levels are robust this year,” said Denny McGuirk, president and CEO of SEMI.  “We expect silicon shipment volume to set a record high this year, followed by two consecutive years of growth.”

2014 Silicon Shipment Forecast

Total Electronic Grade Silicon Slices* – Does not Include Non-Polished

(Millions of Square Inches)

 

Actual

Forecast
 

2012

2013

2014F

2015F

2016F
MSI

8,814

8,834

9,410

9,840

10,163
Annual Growth

0%

0%

7%

5%

3%

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly-engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.