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The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that worldwide sales of semiconductors reached $28.4 billion for the month of August 2014, an increase of 9.4 percent from the August 2013 total of $26 billion and an uptick of 1.3 percent over the July 2014 total of $28.1 billion. Year-to-date sales through August are 10.1 percent higher than they were at the same point in 2013. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market continued to demonstrate broad and sustained strength in August, and sales remain well ahead of last year’s pace,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “Demand is strong across nearly all semiconductor product categories, and the industry has now posted sequential monthly growth for six consecutive months, thanks in part to continued strength in the Americas market.”

Toohey also noted that continued U.S. semiconductor industry strength bodes well for the overall U.S. economy. He cited an SIA whitepaper released this week that found that the U.S. semiconductor industry is one of the top contributors to U.S. economic growth of any domestic manufacturing industry. To learn more, read the SIA whitepaper here.

Regionally, year-to-year sales increased in Asia Pacific (12.3 percent), Europe (10.9 percent), and the Americas (7 percent), but decreased slightly in Japan (-1.7 percent). Sales were up compared to the previous month in the Americas (2.3 percent) and Asia Pacific (1.7 percent), held flat in Japan, and decreased slightly in Europe (-1.3 percent). Sales increased across all regions for the three-month period from June to August compared to the previous three-month period from March to May.

August 2014

Billions

Month-to-Month Sales

Market Last Month Current Month % Change
Americas

5.43

5.55

2.3%

Europe

3.27

3.23

-1.3%

Japan

2.99

2.99

0.0%

Asia Pacific

16.38

16.66

1.7%

Total

28.07

28.44

1.3%

Year-to-Year Sales

Market Last Year Current Month % Change
Americas

5.19

5.55

7.0%

Europe

2.91

3.23

10.9%

Japan

3.05

2.99

-1.7%

Asia Pacific

14.83

16.66

12.3%

Total

25.98

28.44

9.4%

Three-Month-Moving Average Sales

Market Mar/Apr/May June/July/August % Change
Americas

5.07

5.55

9.6%

Europe

3.13

3.23

3.4%

Japan

2.87

2.99

4.2%

Asia Pacific

15.71

16.66

6.0%

Total

26.78

28.44

6.2%

 

SEMICON Europa will feature semiconductor device technology for a wide range of applications, equipment, materials, services and will provide access to critical information relative to device manufacturing, partnership opportunities, next-generation fab requirements  and funding. The event will be held in France (7-9 October in Grenoble) for the first time with an expanded exhibition (25 percent larger). The opportunities and challenges in microelectronics will be discussed in more than 70 sessions with 300 speakers.

Global capital spending on semiconductor equipment is projected to grow  21.1 percent in 2014 and 21.0 percent in 2015. According to the August edition of the SEMI World Fab Forecast, semiconductor equipment spending will increase from $29 billion in 2013 to $42 billion in 2015.

SEMI projects back-to-back years of double-digit growth in Europe and Mid-East semiconductor equipment sales. The SEMI outlook forecasts that the European/Mid-East semiconductor equipment market will grow 11 percent in 2014 (reaching $1.9 billion) and 100 percent in 2015 (reaching $3.8 billion). In terms of percentage of worldwide sales, the Europe/MidEast region’s share is expected to increase from 5.9 percent in 2013 to 9.0 percent in 2015.

The event offers several semiconductor Front-End manufacturing highlights, including the 18th Fab Managers Forum, which is themed “Improving Productivity for Mature Fabs.” Speakers from IMEC, Infineon AG, and Bosch will present on Internet of Things, Automation Level in Fabs, and Smart Connected Sensor Devices. The prospect for future 450mm wafer processing, as well other technical and business challenges in semiconductor and related micro and nano-electronics industries, will be addressed at SEMICON Europa.

In the two-day special program, “450mm Innovations and Synergies for Smaller Diameters,” leaders will present on progress, research, and collaboration on the future of the semiconductor manufacturing. The session includes presentations from Global 450 Consortium, European Commission, ASM Europe BV, and RECIF Technologies.

In addition, a Secondary Equipment Session, themed “Fundamental to European Competitiveness?”, features presentations from  Infineon Technologies AG, STMicroelectronics, and Robert Bosch GmbH.

Other conference programs at SEMICON Europa will explore critical issues in Fab Management, Advanced Packaging, 3DIC, Test and MEMS. In addition, SEMICON Europa this year features a special focus on Electronic Applications (Imaging Conference and Nanoelectronics for Healthcare Conference) and Electronic Components (Low Power Conference and Power Electronics Conference).

Now in its third decade, SEMICON Europa’s new location this year leverages the growing strengths of Grenoble’s technology businesses, academia and institutions  to showcase a diverse array of products, solutions and opportunities spanning the most advanced innovations in the European microelectronics industry.  For more information on exhibition opportunities, visit www.semiconeuropa.org.  For more information on SEMI Europe, visit: www.semi.org/eu.

SEMICON Europa 2014 will be held on 7-9 October in conjunction with the Plastics Electronics Conference and Exhibition (www.plastic-electronics.org) to showcase Europe’s most innovative companies, institutions and people.

SEMATECH, the global consortium of chipmakers, announced today that Kurita Water Industries Limited has partnered with SEMATECH to develop innovative technologies for low defectivity ultrapure water (UPW) applications used in semiconductor manufacturing.

“SEMATECH, along with suppliers, is working to improve preparation and cleaning techniques by both optimizing existing technologies, testing novel methods and developing new characterization technologies that will address current and projected challenges in semiconductor and wafer manufacturing processes,” said Kevin Cummings, SEMATECH’s Director of Lithography. “The collaborative effort between SEMATECH and Kurita illustrates the demand for next-generation ultrapure water systems in the semiconductor industry.”

As a SEMATECH member, Kurita will collaborate with metrology, process and manufacturing experts at SEMATECH to identify and develop UPW defect removal techniques that will improve capabilities for key process applications in semiconductor manufacturing.

“Ultrapure water plays a critical role in manufacturing today’s extremely compact semiconductor chips and, as such, SEMATECH continues to expand our expertise and capabilities in liquid-phase defectivity, including ultrapure water, chemicals and resists,” said Edward Barth, SEMATECH’s Director of Strategic Growth Initiatives. “SEMATECH will leverage Kurita’s unique ultrapure water technology to investigate methods for improving lifecycle costs and increasing efficiency of critical manufacturing process applications and equipment components.”

Gigaphoton Inc., a lithography light source manufacturer, announced today that it has completed development of an electricity-reduction technology for its flagship “GT Series” of argon fluoride (ArF) immersion lasers used for semiconductor lithography processing. Based on the continuous evolution of its leading-edge “Green Innovations” environmental technologies Gigaphoton is unveiling its “eGRYCOS (e-GIGAPHOTON Recycle Chamber Operation System)” product, which enhances laser efficiency and reduces electricity consumption by 15 percent.

The semiconductor industry has been growing faster than other sectors, and one of the key drivers is the evolving improvements in manufacturing equipment. Because of their use as light sources in leading-edge lithography applications, ArF immersion lasers require i increased output power to support new enhancements of the scanners. Current high-volume production lasers are running at 60 W output, but the latest requirement has reached output of 120 W. As industry demand for higher power grows, the electricity that lasers consume will continue to increase as well.

Gigaphoton has addressed this issue through its EcoPhoton program, and has continued to  work on developing a highly efficient laser chamber design. In a laser chamber, excimer gas flows between two electrodes; as the flow speed increases, the discharge becomes more stable, resulting in better laser performance. Gigaphoton’s redesigned chamber features a hydro-dynamically optimized gas flow channel shape, and enables the same speed of gas flow while consuming less electricity. In addition, the newly designed pre-ionization process enables uniform distribution of ions in the main discharge region, providing laser discharge that is 1.2 times more efficient (compared with existing products). As a result, “eGRYCOS” reduces electricity consumption by 15 percent (compared with existing products) without compromising laser performance.

“Gigaphoton has consistently focused on green innovations to support environmentally conscious ‘green fabs’,” said Hitoshi Tomaru, President and CEO of Gigaphoton Inc. “The ‘eGRYCOS’ product is an example of the success of our EcoPhoton program. We will continue to provide our global customers with innovative technologies that enable increased laser performance with lower energy consumption to meet the demands of today’s leading-edge lithography applications.”

By Dr. Chris Moore & Winthrop Baylies, BayTech-Resor LLC

When you say the word sapphire most people think of a brilliant blue gemstone. The members that have formed the Tablet Working Group think of sapphire as a key enabler of future growth for their respective businesses. This article discusses the rationale for forming SEMI’s Tablet Working Group and the action plan moving forward.

At SEMICON West 2014 a presentation [1] to the HBLED technical committee summarized the information available on the expected impact of sapphire on both the Tablet and Smartphone market. It was decided to form a small working group of material suppliers and other interested parties to investigate this area. The mandate of the Tablet Working Group is to determine the needs for standards as they would apply to the eclectic group of manufacturers and service companies that form SEMI. During this discussion it was decided that the group should include not only the use of sapphire in these devices but glass as well. This article will focus on why sapphire and why this effort is starting now.

To put this in perspective the Tablet Working Group is interested in the rectangular pieces of sapphire or glass used as either the cover material (camera lens cover/TP cover) or basic screen of touch devices for tablets and smartphones. Figure 1 shows multiple sapphire cover components for mobile device from Chitwing – Silian optoelectronics. Figure 1 shows sapphire components without ink and coating and sapphire components with ink and AR/AF coating.

Figure 1: A sapphire cover/screen for a smart phone and camera lens cover (courtesy of Mike Feng (mingming.feng@silianopto.com)  Chitwing - Silian) This figure shows sapphire components without ink and coating and  sapphire components with ink and AR/AF coating.

Figure 1: A sapphire cover/screen for a smart phone and camera lens cover (courtesy of Mike Feng ([email protected]) Chitwing – Silian) This figure shows sapphire components without ink and coating and sapphire components with ink and AR/AF coating.group_photo_2

The Tablet Working Group’s interest encompasses the whole supply chain from the initial starting materials though the growth of boules (which may be rectangular) or sheets, shaping of the boule/sheet, slicing, dimensioning and polishing of the surfaces, applying the necessary anti-reflection (AR) or oleo phobic  (Anti-fingerprint , AF) coating which creates the screen or cover glass. Figure 2 contains a more detailed illustration of this supply chain.

Figure 2: A basic illustration of the tablet/smart phone sapphire supply chain.

Figure 2: A basic illustration of the tablet/smart phone sapphire supply chain.

The reasons for looking at this area now are clear. As you may (may not) know there has been considerable interest and a number of articles [2,3] published on the large sapphire growth facility purported to be related to Apple in Mesa Arizona. Depending on the analyst it is believed that the original facility (there is talk of an expansion) contains 2500 furnaces. These boules are shipped overseas to be sliced, dimensioned and polished. The analysts expect that this material will be used in the next generation of iPhone. This is definitely a large investment in the future and represents a significant jump in the predicted use of sapphire material over the next few years.

Given the cost of production (which is expected to be higher than for the equivalent glass unit [4]) the question becomes: why use sapphire in a mainline consumer product? The first answer is hardness and mechanical strength. Sapphire has been used for many years in higher-end watch products because it resists scratching and is extremely durable. Videos on the net show sheets of sapphire being rubbed by concrete blocks [5] with no effect. As part of the mechanical strength it is also predicted that sapphire units will be thinner than their glass equivalents enabling even thinner device designs.

The second reason is more obscure and yet in many ways more important than the first and is a result of sapphire’s optical and electrical properties. It has been reported that touch / camera lens cover screens and sensors made from sapphire are more durable and reliable in its function. Since all of the devices discussed here are by their nature touch screen-driven this becomes a significant factor in final device performance.

With this background we can start explaining why the interest by some SEMI members to examine this manufacturing area. SEMI itself is a collaborative of material suppliers, production equipment manufacturers, metrology system makers, automation suppliers, device producers and service support companies. Given the level of investment predicted for sapphire in the Tablet/Smart phone area one can see that all of these areas will be affected. At least one furnace manufacturer has pinned a large portion of their company’s future on the sapphire industry and it is expected that others will follow. Thus the equipment producers are already moving down this path with significant investment in both equipment and process development. As usual at this stage of development in a new market segment there are very few standards that exist for both the material and its testing. More important, since there is no standard guidance, the end user has less information on how to define sapphire product specification. This non-standard fabrication from material to final product would cost more than standard process.

The Apple business model for sapphire production is highly vertically oriented. However, it is expected that many of the other suppliers of Tablets and Smart phones will contract out the growth and manufacturing of their cover/screen needs resulting in a significant growth market. Although some analysts predict the eventual displacement of glass from this area in all but the lowest-end tablet and smart phone products, many still look at the economic factors which favor glass. However, it is clear that the economics of sapphire screens will be greatly affected by the scale of production now being envisioned.

Thus we have a potentially large sapphire market which is currently in its early growth stage. SEMI and its Standards groups have effectively participated many times in markets of this type including flat panel displays, photo-voltaic devices, and the emerging work of the HBLED committee.

One of the questions asked is why this work would be under the auspices of the HBLED Technical Committee. The original presentation [1] was discussed as part of the HBLED Substrate Taskforce which is the group responsible for generating the first standards [6] for the sapphire wafers used in the HBLED manufacturing process. Since the group has an interest in sapphire the initial thoughts were that this area could be looked at as developing standards for “substrates” which are now rectangular as opposed to round.

As the presentation was discussed in the technical committee meeting it was clear that the definition of the “substrate” was only part of the potential work to be done. Thus it was decided to form a working group to look at the potential for standards work in the Tablet/Smart phone area. It was also clear that SEMI expertise in materials, automation and metrology standards filled a niche not being addressed by the IEC standards group. At no point did any of the volunteers present want to take on work that was already being done or outside the normal area SEMI would cover. The discussion also highlighted work other than standards which may be of benefit for SEMI but this is beyond the scope of the working group.

The Tablet Working Group will hold its first phone conference in September. Current working group members include material suppliers like Silian ( a pioneer in sapphire) and Corning, metrology suppliers and other interested parties. The first face to face meeting will be at the fall Standards meeting in San Jose. If you have interest in joining the group please contact Michael Tran of SEMI staff or Chris Moore at [email protected]  or Win Baylies at  Win.Baylies @ BayTech-Resor.com.

[1] Tablet Substrates SEMI Standards Presentation https://sites.google.com/a/semi.org/hbled/hb-led-wafer-tf/july-10-2014

[2] Analyst article on Apple/Mesa AZ http://seekingalpha.com/article/2167493-gt-advanceds-sapphire-operations-in-arizona-are-likely-fully-ramped-and-ready-to-deliver-the-goods-to-apple?isDirectRoadblock=false&app=1&uprof=45

[3] Analyst article on Sapphire Composite Cover Screens for Mobile Devices and Point-of-Sale Scanners  http://seekingalpha.com/article/2235313-gt-advanced-technologies-next-frontier-sapphire-composite-cover-screens-for-mobile-devices-and-point-of-sale-scanners?app=1&uprof=45

[4] Analyst article on Glass Demand for Higher-Generation Glass Substrates will Drive Corning’s Display Volume – http://seekingalpha.com/article/2230553-ignore-the-sapphire-threat-corning-is-on-a-roll

[5] Internet video Aero Gear’s Flight Glass SX Sapphire Crystal vs a Concrete …

www.youtube.com/watch?v=Gh17UvUQxwM

[6] SEMI HB-LED standards (www.SEMI.org/standards)

HB-1-0814 Specification for Sapphire Wafers for Use for Manufacturing High-Brightness Light Emitting Diode Devices

HB-2-0613 Specification for 150 mm Open Plastic and Metal Wafer Cassettes Intended for Use for Manufacturing HB-LED Devices

HB-3 -1113 Mechanical Interface for 150 mm HB-LED Load Port

HB-4-0913 Specification of Communication Interfaces for High Brightness LED Manufacturing Equipment (HB-LED ECI)

 

Pixelligent Technologies announced today that it has been selected for a Department of Energy (DOE) solid-state-lighting award to support the continued development of its OLED lighting application. The details of the award can be viewed on the DOE SSL website. Pixelligent and its partner OLEDWorks were selected as one of only nine awardees nationwide for this $1.25 million DOE award.

“This is the second OLED lighting award we have received from the DOE in partnership with OLEDWorks, which clearly demonstrates our leadership position in developing the next generation materials required to accelerate the commercialization of OLED lighting,” said Craig Bandes, President & CEO of Pixelligent Technologies.  “We are proud to have been selected by the DOE for this highly competitive grant that, when combined with our internal investments, will provide the resources required to optimize our OLED lighting application,” said Gregory Cooper PhD, Founder & CTO of Pixelligent Technologies.

The goal of this project is to develop a novel internal light extraction design that improves the light extraction efficiency of OLED lighting devices by more than 200%, without negatively impacting the device voltage, efficacy, or angular color dependence.

“This federal grant reflects the type of common sense investments we should be making to help our economy rebound by boosting U.S. manufacturing and high-tech innovation,” said Congressman Ruppersberger of Maryland’s Second District. “The fact that one of Baltimore’s own companies was selected and will be bringing jobs back to the city is icing on the cake. Pixelligent is an impressive and growing company, and I am proud that they have chosen the Second District to call home.”

North America-based manufacturers of semiconductor equipment posted $1.35 billion in orders worldwide in August 2014 (three-month average basis) and a book-to-bill ratio of 1.04, according to the August EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.04 means that $104 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in August 2014 was $1.35 billion. The bookings figure is 5.0 percent lower than the final July 2014 level of $1.42 billion, and is 26.5 percent higher than the August 2013 order level of $1.06 billion.

The three-month average of worldwide billings in August 2014 was $1.29 billion. The billings figure is 2.0 percent lower than the final July 2014 level of $1.32 billion, and is 19.5 percent higher than the August 2013 billings level of $1.08 billion.

“The SEMI Book-to-Bill ratio has been at or above parity for 11 consecutive months, and both current month bookings and billings continue to trend well above 2013 levels,” said Denny McGuirk, president and CEO of SEMI. “Strong equipment spending growth for the year is observed across the fab and test and assembly segments.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill

March 2014

$1,225.5

$1,297.7

1.06

April 2014

$1,403.2

$1,443.0

1.03

May 2014

$1,407.8

$1,407.0

1.00

June 2014

$1,327.5

$1,455.0

1.10

July 2014 (final)

$1,319.1

$1,417.1

1.07

August 2014 (prelim)

$1,293.3

$1,346.2

1.04

Source: SEMI, September 2014

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the SEMI Equipment Market Data Subscription (EMDS).

You can’t fix what you can’t find. You can’t control what you can’t measure. 

BY DAVID W. PRICE and DOUGLAS G. SUTHERLAND

This is the first in a series of 10 installments which will discuss fundamental truths about process control—inspection and metrology—for the semiconductor industry. By fundamental, we imply the following:

  • Unassailable: They are self-evident, can be proven from first principles, or are supported by the dominant behavior at fabs worldwide
  • Unchanging: these concepts are equally true today for 28nm as they were 15 years ago for 0.25μm, and are expected to hold true in the future
  • Universal: They are not unique to a specific segment of process control; rather they apply to process control as a group, as well as to each individual component of process control within the fab

Each article in this series will introduce one of the 10 fundamental truths and discuss interesting applications of these truths to semiconductor IC fabs. Given the increasing complexity of advanced devices and process integration, process control is growing in importance. By understanding the fundamental nature of process control, fabs can better implement strategies to identify critical defects, find excursions, and reduce sources of variation.

The first fundamental truth of process control for the semiconductor IC industry is:

You can’t fix what you can’t find. You can’t control what you can’t measure.

While it’s true that inspection and metrology systems are not used to make IC devices—they do not add or remove materials or create patterns—they are critical for making high-yielding, reliable devices. By finding defects and measuring critical parameters, inspection and metrology systems monitor the hundreds of steps required to manufacture a device, ensuring the processes meet strict manufacturing specifications and helping fab engineers identify and troubleshoot process issues when there is an excursion. Without inspection and metrology, it would be near impossible for fabs to pinpoint process issues that affect yield. However, it’s not enough to simply “find” and “measure” — a fab’s process control strategy needs to be capable and cost-effective.

Capable inspection and metrology strategies find and measure the defects and parameters that affect device yield. Cost-effective inspection and metrology is performed at the lowest total cost to the factory, where total cost is the sum of the cost of lost yield plus the cost of process control.

First, make it capable

If you can’t find it, you can’t fix it. At the heart of this truth is the understanding that, above all else, a fab’s inspection and metrology strategy must be capable. It must highlight the problems that are limiting baseline yield. It must also provide actionable information that can enable fabs to quickly find and fix excursions (FIGURE 1).

We emphasize this need for capability first because we have observed that some fabs are too quick tosacrifice capability for cost reductions. No strategy is cost-effective if it doesn’t accomplish its fundamental objective.

Below are specific questions that can help fab management evaluate the capability of its process control strategy:

  • Are you finding all sources of your defect-limited yield? Are you finding these in-line or at end-of-line?
  • Does your defect Pareto have sufficient resolution of the top yield-limiters in each module to direct the most appropriate use of factory engineering resources?
  • Have you fully characterized all of the important measurements and defect types (size range, kill ratio, root cause, solution)?
  • Do you understand the most probable incursion scenarios? What is the smallest excursion that you absolutely must detect at this step? How many lots are you willing to have exposed to this excursion before it is detected?
  • Are you inspecting and measuring at all the right steps? Can you quickly isolate the point of formation for excursions? Can you quickly disposition potentially affected lots?
  • Does a particular defect signature become confused by defects added at subsequent process steps? Or do you need separate inspections at each step in order to partition the problem? 
  • Do you have overlapping inspections to guard against the high-frequency, high-impact excursions?
  • What is the alpha risk and beta risk for each inspection or measurement? How are these related to the capture rate, accuracy, precision, matching and more?

Process control Fig 1b Process control fig 1a

 

FIGURE 1. You can’t fix what you can’t find. And you can’t control what you can’t measure. Left: P-MOS SiGe critical dimension measurement. Right: Fin patterning particle leading to a Fin Spire defect at post dummy gate etch. Source: KLA-Tencor

Then, make it cost-effective

Once a capable strategy is in place, then a fab can start the process of making it cost-effective. The best known method for optimizing total cost is usually adjusting the overall lot sampling rate. This is generally preferred because the capability remains constant.

In some cases, it may be possible to migrate to a less sensitive inspection (lower cost of ownership tool or larger pixel size); however, this is a dangerous path because it re-introduces uncertainty (alpha/beta risk) that reduces a fab’s process control capability. This concept will be discussed in more detail in our next article on sampling strategies.

Finally, it is worth pointing out that it is not enough to implement a capable strategy. The fab must ensure that what was once a capable strategy, stays a capable strategy. A fab cannot measure with a broken inspection tool or trust a poorly maintained inspection tool. Therefore, most fabs have programs in place to maintain and monitor the ongoing performance of their inspection and metrology tools.

By optimizing process control strategy to be capable and cost-effective, fabs ultimately find what needs to be fixed and measure what should be controlled—driving higher yield and better profitability.

Fast and predictive 3D resist compact models are needed for OPC applications. A methodology to build such models is described, starting from a 3D bulk image, and including resist interface effects such as diffusion. 

BY WOLFGANG DEMMERLE, THOMAS SCHMÖLLER, HUA SONG and JIM SHIELY, Synopsys, Aschheim, Germany, Mountain View, CA and Hillsboro, OR. 

With further shrinking dimensions in advanced semiconductor integrated device manufacturing, 3D effects become increasingly important. Transistor architecture is being extended into the third dimension, such as in FinFETs [1], multi-patterning techniques are adding complexity to lithographic imaging in combination with substrate topography.

Even on planar wafer stacks, process control gets more and more challenging for the 1X nm technology node, as features are being scaled down while exposure conditions remain at 193nm immersion lithography with 1.35 NA. Image contrast decreases, especially at defocus, resulting in high susceptibility for resist loss height and tapered sidewalls; resist profiles may deviate significantly from ideality. Although imaging conditions can be well controlled at nominal exposure conditions, the effect on the process window is usually substantial, as the useful depth of focus as become comparable to the resist film thickness. These dependencies are illustrated in FIGURE 1.

FIGURE 1. Extending 193nm immersion technology to the 1x technology node reveals new patterning challenges.

FIGURE 1. Extending 193nm immersion technology to the 1x technology node reveals new patterning challenges.

Especially random 2D layout structures exhibit weak image areas, where often severe resist top loss or footing occurs, which can results in critical defects within the subsequent etch process. An example for such a weak spot is shown in FIGURE 2a, taken during the early phase of process development [2]. The left clip shows a top-down SEM image of the pattern in resist, taken after the development step. It does not provide any indication for a potential defect in this area. Conventional 2D models represent well the bottom contour of the resist profile. Overlaying the model contour (red line) with the SEM image shows a very good correlation with reality, again giving no motive to apply any layout corrections. However, after etch a bridging hot spot is revealed, as can be seen on right SEM image. A more detailed analysis of the weak spot area using rigorous simulations indicates a low image contrast and severe resist loss of about 60% at the critical location, as shown in FIGURE 2b. Degenerated 3D resist profiles are one of the main root causes for post-etch hotspots at advanced technology nodes.

FIGURE 2. “Weak lithography spot” often becomes only visible after etch if 2D models are used for correction and verification.

FIGURE 2. “Weak lithography spot” often becomes only visible after etch if 2D models are used for correction and verification.

In case those “weak litho spots” in a layout are known, localized corrections to mask features can be applied to prevent yield loss. However, the diversity of random logic structures in advanced designs makes is mandatory that compact models are available which reflect the 3D nature of the resist profiles at any location within the chip, and that this information is being utilized during optical proximity correction and verification, on full chip scale. Rigorously tuned compact models provide an efficient approach to achieve this goal, as we are going outline in the subsequent sections.

Efficient generation of 3D resist compact models

The fundamentals of 3D resist simulation are well captured by rigorous lithography process simulation which is based on a first principle physical modeling approach [3 – 6]. The corresponding simulation results do not only provide an accurate representation of the expected 3D resist profile for arbitrary device patterns within a random layout context. Rigorous models are also capable of predicting the impact of process variations such as focus or dose shifts, wafer stack or illumination condition changes, to only name a few, onto the lithographic performance. This predictive power is achieved by properly separating the various contributions to pattern formation inside the models, for instance addressing optical effects and resist effects individually. Due to their physical nature, the accuracy of optical simulations is only limited by the quality of the input data charactering the optical conditions in the exposure tool. As chemical processes in the photo resist are rather complex, the corresponding models utilize a small set of free, physically or chemically motivated parameters. Only a few experimental data points, e.g. from SEM metrology, are required to calibrate those free parameters, ensuring a good match between experiment and simulation over a wide application space. However, this predictive simulation power comes at the expense of run time – the enormous demand for computational resources does not allow rigorous models at to be applied on a full chip scale.

Standard full chip mask synthesis applications such as optical proximity correction (OPC) or verification are based on the deployment of conventional 2D compact models, i.e. models which represent the resist contours visible in a top-down views. Compact models are optimized for performance. Their accuracy, i.e. the match between model and experiment, is usually achieved by optimizing a large set of fitting parameters, inputting an even larger metrology data set based on CD-SEM measurements. Expansions to a models application space, e.g. to cover additional feature types, are enabled by extending the training data set for model fitting. However, this approach has limitations, as the effort for gathering additional metrology data might become prohibitive, which is rather cogent in the case of 3D metrology.

However, as outlined above, 3D models are required to capture hotspots which are being introduced through local resist height loss. An obvious extension into the third, vertical dimension could be to build individual 2D models at different image depths, representing resist contours of a 3D profile at discrete resist heights. The application of any of the individual 2D models to downstream OPC/LRC tools is straight-forward. However, the relevant image depths need be determined in advance due to the discrete nature of the methodology itself. The critical resist heights can be predetermined, based on etch process results. In practice, a bottom model along with one or two models at critical heights are usually sufficient to detect sites where etch results become sensitive to resist profile. Then the models are directly calibrated on those critical resist heights [7].

One major challenge to support this compact model calibration approach is the preparation of the corresponding metrology data. Conventional, single plane 2D models already require a significant amount of top-down CD-SEM data based on a feature set large enough to represent the entire design space. However, only very rough estimations can be made about the actual resist profiles. This is not sufficient for a reliable 3D model calibration.

Several techniques are available to experimentally characterize the three-dimensional shape of a resist profile, such as atomic force microscope (AFM) or CD-SEM cross section measurements. Common to all these methods is that they are very complex, elaborate, and costly, and therefore not suitable for high volume metrology data collection.

Alternatively, a carefully calibrated rigorous simulator model can be used to generate virtual 3D resist profile data by outputting CD values at specific heights, for specific features. Due to the underlying physical modeling approach, only significantly less experimental data are required for resist model calibration, compared to compact model building [8]. A typical calibration data set consists of CD-SEM top down measurements on a small set of 1D structures, covering critical CDs and pitches, through process window. In addition, a few 3D reference data points, e.g. from AFM, cross section measurements, or etch finger- prints are used to tune the absolute resist height of the profiles in order to match experiment and simulations in all dimensions. This approach not only removes the potential risk of measurement inconsistency between 2D and 3D metrology results, but also opens the door for extensive data collecting with minimum fab efforts.

The CD data sets, either experimentally determined virtually generated for a number of discrete heights, is then fed to compact model calibration at multiple imaging planes. The calibration can be independent for each height. It is often found that fitting a separate threshold for each resist height enables a better match between input data and compact model results. This is mainly due to the fact that vertical resist physics, such as z-diffusion, out-diffusion at boundaries are not included in the traditional compact modeling approach. Differences are compensated through a variable threshold. In addition, other resist models parameters may also be varied to compensate the z-direction physical effects. As a result, the common physicality of the model is compromised, as over-fitting takes place.

In order to demonstrate these dependencies, rigorous simulations based on a calibrated resist model were used to generate reference CD data for over 500 gauges at 9 height positions in the resist film. The gauges represent real fab process covering both 1 dimensional and 2 dimensional layout patterns. The process settings between compact model (ProGen) and rigorous model (S-Litho) are matched exactly. FIGURE 3a shows the results of a compact model calibration in which threshold and common resist model param- eters were kept constant for all sampling heights. The example profile (left image) shows a clear mismatch between the two modeling approaches, which results in an overall matching error with a root-mean-square (RMS) value of 2.9nm for the entire data set (right image).

FIGURE 3. Matching 3D resist compact model profiles to rigorous reference data.

FIGURE 3. Matching 3D resist compact model profiles to rigorous reference data.

These limitations have been overcome by adopting more physical modeling approaches, as used in rigorous simulators, while keeping the model form compact for full-chip applications. To that end, the bulk image is calculated by using one set of retained Hopkins kernels. Optical intensity can be assessed at any image depth without accuracy compromise. Based on an accurate bulk image, the model has been extended to capture effects present in chemically amplified resists. For instance, acid generation, acid-base neutralization, and lateral as well as vertical diffusion are taking into account. Specific boundary conditions at the resist interfaces are used to account for surface effects. The model is formulated in a continuous form so that a model slice at any image depth is readily available for use after calibration. While the calibration data is collected at discrete image planes, all planes are calibrated simultaneously using one set of resist parameters to guarantee physical commonality among them. Moreover, the calibration is done stepwise carefully to ensure the optical part to account for optical effects and resist model to account for resist effects.

The corresponding results are shown in FIGURE 3b. The compact modeling approach now takes vertical diffusion effects into account, including out-diffusion at resist top and bottom, which ensures an excellent match for individual profiles (left image) as well as for the entire data set, resulting in an rms value of 0.5nm.

Compact resist model portability

The integration of physical effects into compact modeling does not only enable the extension of resist simulation into the third, i.e. the vertical dimension, as described in the previous section. Characteristics such as “portability” or “separability,” usually assigned to rigorous models only, become now available within compact modeling as well. Rather than lumping optical and resist effects into a single set of model fitting parameters, the optical set is characterized individually, and resist effects are modeled individually, and therefore separated from the optical contributions to the modeling result. The more clean the separation, the more accurate is the modeling of the resist system response to slight modified optical condition, i.e. conditions different from the ones present during calibration.

Typical simple changes to the optical setup are the variation of focus and exposure dose. FIGURE 4 shows the 3D profile results for two representative features nominal CD of 60 nm (Figure 4(a)) and a wide line with a nominal CD of 200 nm (Figure 4(b)). The calibration 4, center images), with profiles being sampled at various heights. In order to test compact model prediction, we have applied a negative focus offset (Figure 4, left images), and a positive focus offset (right images), and compared the compact model results to profiles determined by rigorous simulation, which served as a reference. The profile changes through focus are very well captured by the compact model, especially the resist top loss at positive defocus (Figure 4, right images). These results are already a first demonstration of predictive power which comes with rigorously tuned compact models. In similar experiments, we have also successfully shown that this modeling concept can be utilized to investigate unintended printing of sub resolution assist features by analyzing the 3D resist response [9], and to source variations [10].

FIGURE 4. Rigorously tuned 3D resist compact models can predict the impact of process variation on profiles without additional data fitting.

FIGURE 4. Rigorously tuned 3D resist compact models can predict the impact of process variation on profiles without additional data fitting.

3D resist model based proximity correction

An accurate and predictive 3D resist compact model can be deployed in mask synthesis verification, or lithographic rule check (LRC), to detect weaknesses in resist profiles. For severe hot spots, simple OPC retargeting is not sufficient to mitigate issues caused by degraded resist profiles. In such a case, the appli- cation of rigorously tuned 3D compact models within optical proximity correction (OPC) offers an efficient approach to automatically repair hotspots within the mask synthesis flow. ProGen models exhibit the unique property of being consistently applicable in combination with different mask correction approaches, for instance conventional OPC as well as inverse lithog- raphy technology (ILT).

FIGURE 5a shows such a weak spot on an ILT mask where the correction is based on a 2D resist compact model, just the contours representing the bottom of the resist profile (black contour). However, the 3D rigorous simulation results reveals severe resist pinching at the top of the resist bulk, as displayed in Figures 5b. Looking at the bottom contour alone, such a hotspot would not have been detected. The red contour in Figure 5a represents the corresponding 3D compact model result extracted at the resist top, confirming the rigorous simulation result. Consequently, in order to achieve a more robust mask solution, we are now taking information from the entire resist profile into the ILT cost function to compute the corresponding correction. The results are shown in Figure 5(c), including bottom resist contour (black) and top resist contour (red) for the modified mask. Although the resist profile sidewall that the location of the weak spot still show some taping, the situation has significant improved over the 2D model based correction. This is confirmed by the rigorous simulation results in Figure 5(d), which does not show indications for resist pinching anymore.

FIGURE 5. Successful OPC correction of an ILT mask, based on 3D resist compact model input.

FIGURE 5. Successful OPC correction of an ILT mask, based on 3D resist compact model input.

The above OPC results conducted by ILT using 3D resist models again imply that resist profile weakness can be corrected in a mask synthesis process with the help of one predictive, accurate 3D resist compact model. As a result, wafer yields will be greatly improved.

Summary and outlook

In this work, we have outlined the concept of using a rigorous simulation approach to tune and improve compact modeling capabilities. Characteristics such as “productivity,” “portability” or “separability,” usually known only within the context of physical models, can be transferred to compact models and therefore made available for full chip mask synthesis applications. We have successfully demonstrated this approach by establishing rigorously tuned 3D resist compact models. Those models combine the performance benefit of compact models, required for full chip mask synthesis applications, with the 3D modeling capabilities and predictivity of rigorous models. We have demonstrated that the rigorously tuned resist model can be carried to a different lithography process setup, e.g. a different illumination source without suffering any accuracy degradation. Those models can be deployed in downstream mask synthesis applications such as optical proximity correction or verification without further modifications. As an example, we have performed a 3D resist model assisted mask correction, using ILT, to mitigate potential post etch hotspotsThe concept of “rigorously tuned compact models” can be easily extended to address other simulation challenges, even beyond the litho process, as shown in FIGURE 6. In fact, it has already been used to improve mask topography simulation capabilities in compact models, or extend resist modeling properties to capture effects which are characteristic to negative tone development. We are currently working on utilizing TCAD physical etch simulation to tune etch compact models, which will take simulated 3D resist profiles as input. A combination of TCAD etch tools and rigorous litho simulation can be used to generate compact models which take underlying wafer topography into account.

FIGURE 6. Extending the concept of “rigorous tuning” to process simulation beyond traditional lithography.

FIGURE 6. Extending the concept of “rigorous tuning” to process simulation beyond traditional lithography.

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RF Micro Devices, Inc. today announced the preliminary results of its special meeting of shareholders held earlier this morning to approve its agreement and plan of merger and reorganization with TriQuint Semiconductor, Inc.

RFMD shareholders voted to approve the merger agreement and to approve, by non-binding advisory vote, the compensation arrangements for RFMD’s named executive officers in connection with the transaction. TriQuint’s stockholders are scheduled to vote on the merger agreement and other matters at a special meeting to be held later today.

“Today’s shareholder vote is a significant endorsement of our vision to create the new leader in RF solutions,” Bob Bruggeworth, president and CEO of RFMD, said. “With the closing of this transaction, we will bring under one roof the industry’s broadest portfolio of critical enabling technologies, with expertise in mobile devices and complex infrastructure and global aerospace/defense applications.”

RFMD and TriQuint anticipate the closing of the transaction will occur in the second half of calendar 2014 subject to the receipt of regulatory approval and other customary closing conditions.

RFMD is a designer and manufacturer of high-performance radio frequency solutions.