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Liquid-crystal-display television (LCD TV) panels enjoyed unexpected growth in the first half of this year, tied to enthusiastic TV viewing because of the World Cup and other factors that benefited the market, according to a new report from IHS Technology.

Global LCD TV panel shipments during the first six months of 2014 rose 3 percent from the same period a year ago, as shown in the attached figure. Although growth this year was much less than the 9 percent expansion logged during the first six months of 2013, achieving any increase at all was unforeseen.

2014-08-06_LCD-TV_Panels

“What a surprising result this was, as the television industry doubted that shipments could increase during this time,” said Ricky Park, director for large displays at IHS. “It was unclear whether any growth would occur because of signs earlier in the year that appeared to be discouraging. However, the market has righted itself, to everyone’s delight.”

Among the variables fueling the market, perhaps none were more dazzling than the month-long, glittery affair known as the World Cup. Starting in June, the world’s premiere soccer event drove up demand for televisions, especially in Europe and South America.

Sports extravaganzas long have been reliable drivers of television sales—and by extension, the LCD TV panels that make up the sets. And for events of global interest like the World Cup or the Olympics, staged once every four years, keen anticipation usually helps propel the market upward.

Still, the athletics spectacle alone was no guarantee of growth. But other factors also kicked in, helping create an overall favorable environment for the global LCD TV trade in the first half. These included signs of a continuing economic recovery in North America, one of the world’s two largest markets for LCD TVs alongside China; a subsidy program initiated by the Mexican government for its citizens to buy new LCD TVs; and the continued phasing out of bulky, tube-type analog televisions, now obsolete in many areas of the world.

These findings are available in the report entitled, “LCD Supply and Demand Market Tracker – Q2 2014,” from the Displays service of IHS Technology.

But strong demand is blunted by production problems

Despite the stronger-than-expected demand for the January to June period, a drop in yields and a loss in capacity due to production line modifications caused a shortage of supply of LCD TVs. The effects were felt especially in the ultra-high-definition television (UHD TV) segment of the industry.

Issues related to quality have cropped up, for instance, in the production of so-called PenTile RGBW UHD panels, which are aimed at the 40-inch segment of the UHD space. A Samsung-patented technology, PenTile panels add a subpixel with no color filtering material that allows the backlight through, resulting in white (W) being added to the traditional red, green and blue (RGB) subpixels. The technology makes brighter images possible with the same amount of power used for RGB.

The production headache is becoming a problem, Park added, because the price of PenTile RGBW UHD TVs was supposed to be coming down in order to better compete with non-UHD sets. With four times the resolution of 1080p sets, UHD TVs are also priced far higher than conventional high-definition television models.

Also facing trouble was the production method known as multi-model on a glass (MMG). Low production efficiencies resulted in reduced capacity for MMG, especially in the advanced production lines for eighth-generation fabs.

On top of those problems, a growing share of the manufacturing base that once had enjoyed maximized glass efficiency—lines producing TV panels in sizes of 39.5, 42.5, 48 and 48.5 inches—experienced deteriorating yields.

Production issues of a different nature are likely to occur in the second half, IHS believes, extending current manufacturing woes. A substantial loss in production capacity is expected during the remainder of the year because panel makers in China and Taiwan are slated to use different electrode materials from those currently deployed, ostensibly to improve their UHD products. The makers affected include AU Optronics, Innolux and BOE Optoelectronics.

Change is also afoot at Korean suppliers Samsung Display and LG Display.

Samsung Display will reduce the thickness of its front-pane glass to 0.5 millimeters as the company increases the production of curved TVs. LG Display, meanwhile, reportedly is converting part of an eighth-generation line to oxide thin-film transistor technology in order to produce organic light-emitting-diode (OLED) panels, a rival technology to UHD LCDs that the maker hopes will start picking up among consumers.

All the same, TV prices are not expected to dip in the months to come in spite of the ongoing production problems, which will serve to constrict the supply of LCD TVs.

Semiconductors providing wireless connectivity in health and fitness devices are set for solid double-digit growth in 2014 and beyond, especially as a clutch of wireless technologies make their way into a growing number of wearable devices, according to a new report from IHS Technology.

Shipments this year for wireless semiconductors in health and fitness will reach a projected 61.2 million units, up 11 percent from 55.0 million in 2013. The expected strong expansion for this year continues the robust growth of 2012 and 2013. And the market shows little signs of slowing, with shipments in 2018 climbing to 95.78 million units, as shown in the attached figure.

Wireless_Semiconductor_Shipments_JPEG

The overall health and fitness market covered by the forecast includes the sports and fitness segment on the one hand, as well as the adjacent market for health and wellness on the other. While overlaps exist between the two segments, there are also subtle differences.

For instance, data and activity sharing by wireless means is more common in sports and fitness as consumers happily disclose the results of their improving fitness levels. In contrast, sharing is not as widespread in health and wellness, where disease management is largely private and carefully guarded by the affected individuals.

Bluetooth Smart is leader of the pack

Yet the fitness market as a whole is particularly receptive to wireless connectivity.

“Because most health and fitness devices are mobile, wireless connectivity is important,” said Lee Ratliff, principal analyst for connectivity at IHS. “And because these wireless mobile devices are in most cases also wearable and thus require a small form-factor, they cannot be power hogs and must support low-energy consumption to have the best chance of succeeding in the consumer market.”

Wireless connectivity mainly serves two purposes, Ratliff noted. Especially in sports and fitness applications, wireless connectivity is often used to provide a link to remote sensors when wired connectivity is too cumbersome. Examples here include linking heart-rate chest straps to wrist-worn heart-rate monitors, or linking wheel-speed sensors to cycling computers.

A second use is for data uploading, with wireless connectivity employed to upload fitness and performance data to PCs, smartphones, tablets or online communities for analysis and sharing.

Among the various wireless technologies now available on the market for health and fitness, Bluetooth Smart is the most successful. As a low-power technology, Bluetooth Smart enables even the smallest wearable products—such as foot pods, the size of one’s thumbnail—to operate for years on a battery the size of a coin cell. Bluetooth Smart also leverages its enviable position in mobile phones and tablets: It is the only major low-power wireless technology able to communicate with all the chief mobile platforms, including Apple iOs, Google Android, Microsoft Windows 8 and the BlackBerry operating system.

Moreover, the dongle-free connectivity of Bluetooth Smart gives it an edge over other rivals. No other technology features both low-power consumption as well as seamless connectivity, Ratliff said.

One wireless technology specifically designed for the health and fitness market and popular with heart-rate monitors, ANT/ANT+, is a low-power technology that, however, does not enjoy the same broad support in mobile platforms. A PC or dongle is also required for ANT/ANT+, unlike Bluetooth Smart. Still, ANT/ANT+ enjoys a significant market share and seems to have a defensible position, especially in products designed for serious fitness enthusiasts and in cycling electronics.

Keen consumers help spur market

A big driver of growth in health and fitness devices is the desire among consumers to track and analyze personal data, in pursuit of what is known in industry circles as “the quantified self.” Consumers can then share such data via social media and online communities, often via apps like RunKeeper of Runtastic.

Other drivers for the market include the increased use of wearable devices; decreasing component costs; an aging demographic concerned about preserving health; and the rising use of telehealth, or remote healthcare systems.

Shipments of consumer health and fitness devices with integrated wireless connectivity will grow to an estimated 75.7 million units in 2018, up from 23.0 million units in 2011.

These findings are available in the report, “Low-Power Wireless Market Tracker – Q2 2014,” from the Information Technology service of IHS.

Tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. 

BY SHRINIVAS SHETTY, DAVID M. OWEN and SCOTT ZAFIROPOULO Ultratech, Inc., San Jose, CA 

Control of overlay in multi-layer devices structures has always been important in semiconductor fabrication. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. As devices shrink, the overlay require- ments become more and more stringent (FIGURE 1). The tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. The overlay budget includes contributions from the lithographic scanner, the reticle and the wafer. The wafer represents the largest source of overlay variability during high-volume manufacturing. Therefore, the development of an inspection strategy to control within-wafer and wafer-to-wafer variability may provide the key to meeting the challenges associated with future generations of devices.

Traditional wafer warpage or distortion measurements have typically used point-by-point measurements to generate low-density maps of the wafer geometry with a few hundred data points across the wafer. Depending on the specific technique, a higher density map may be possible at the expense of throughput or limiting the measurement to a small portion of the wafer. The trade-off of point density and throughput has meant that the use of wafer distortion characterization for overlay control has been limited to off-line process development and not to improve yields.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

The Superfast system based on the Coherent Gradient Sensing (CGS) interferometer uniquely provides high-density front-side pattern wafer maps (>3,000,000 data points) with fast data acquisition (seconds per wafer). The high throughput along with small foot print leads to a low cost of ownership relative to competing technologies.

This article discusses using deformation data from the front-side of a patterned wafer on the Superfast, we are able to understand the relationships between surface displacements, stress and overlay. It also reviews a case study evaluating the role of millisecond annealing parameters on overlay and stress.

Superfast (CGS) technology description

The CGS interferometer is a type of lateral shearing interferometer. The interference is generated in a self-referencing manner using two parallel diffraction gratings. This self-referencing approach eliminates the need for an independent reference beam from, for example, a flat mirror and ensures excellent fringe contrast regardless of the reflectivity of the surface under investigation. This is a key differentiator to accurately measure patterned wafers.

The interferometer essentially compares the relative heights of two points on the surface that are separated by a fixed distance, called the shearing distance. Physically, the change in height over a fixed distance provides slope or tilt information and the fringes in a CGS interference pattern are contours of constant slope. The slope data derived from the interference patterns is integrated numerically to generate the surface shape or topography.

Application to thin film stress measurement

The Superfast inspection system is designed for semiconductor manufacturing based on the CGS interferometer. The Superfast tool features a collimated probe beam of >300mm in diameter that is expanded from a relatively low power HeNe laser. The probe beam illuminates the entire wafer at once and the wafer is supported on three lift pins, which are then subtracted from the final analysis. The beam that reflects off of the wafer surface is distorted in accordance with the local height variations of the wafer. The distorted beam is steered through the two parallel diffraction gratings to generate an interference pattern that is imaged on to a CCD array. As a result, the wafer surface is mapped with high resolution (>3,000,000 data points) with measurement times of seconds.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

Data integrity on patterned wafers is further enhanced through the implementation of phase shifting. Phase shifting is achieved by moving the gratings in the direction parallel to the shearing direction. Phase shifting provides several advantages and for the measurement of patterned wafers. The most notable being that fringe contrast in the interference fringes, that modulate with phase shifting can effectively be separated from pattern contrast, which is static with phase shifting. Phase shifting along with the inherent self-referencing nature of the CGS technique results in relatively high measurement integrity on patterned wafers without the need for dedicated or distinct targets, pads or other specialized features in the layout. Typical results are shown in FIGURE 2.

Compared to other techniques, Superfast has several distinct advantages.

  • Front Side Pattern Wafer Measurement: Core CGS 3G technology has been used to measure front-side of pattern wafers for over a decade.
  • High Data Density: Superfast generates high density maps of surface displacements that feature more than 3,000,000 points of data. In this manner, detailed within-die, die-to- die and wafer-to-wafer process variations that lead to overlay errors can be characterized.
  • High Throughput/Low Cost: The Superfast data set consists of interferometric images of the full wafer. These images can be captured rapidly using CCD camera, providing system throughputs of 100-150 wafers per hour.
  • Flexible Implementation: Superfast is capable of evaluating overlay at any step in the process flow and does not rely on dedicated overlay targets. In this manner, Superfast provides the ability to catch potential overlay problems due to process excursions upstream of lithography, thereby reducing material- at-risk and the need for subsequent scrap or rework. 
FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

Case study: millisecond anneal characterization

This section describes a case study to illustrate the application of Superfast technology to characterize a millisecond anneal process. Four wafers of a full-flow 65nm device were annealed using Laser Spike Annealing (LSA). The device contained silicon germanium with 20% Ge. The four wafers were processed at peak annealing temperatures of 1235 or 1270oC and annealing times of 200 or 400 microseconds. Process-induced deformation information was collected by measure pre-anneal and post-anneal wafer topography using the Superfast system. After millisecond annealing, the wafers were processed through to contact patterning. Overlay data was collected post-lithography for all four wafers. The overlay was measured at 9 sites per shot for 28 shots. Surface displacement data was extracted at the same nominal locations on the wafer and displacement residuals were computed using linear inter-field and intra-field correction.

The displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction are shown in FIGURE 3. Inspection of Fig. 3 reveals that the vector maps for the 1235oC temperature conditions (Figs. 3a & 3b) as well as the 1270oC / 200μs condition (Fig. 3c) all exhibit similar features such that the displacement vectors are generally in the same direction at a particular location in those three vector maps with the same relative vector magnitudes within-wafer. On the other hand, the vector map for the 1270oC / 400μs anneal (Fig. 3d) shows a fundamentally different distortion characteristic, indicating perhaps a change in deformation mechanism associated with the higher thermal budgets. This data suggests that wafer distortion measurements may provide a relatively efficient way to study transitions in mechanisms that occur under different processing conditions.

The correlation between the surface displacement residuals and the overlay residuals is shown in FIGURE 4. The data in Fig. 4 is based on the |mean|+3 sigma values of both quantities as evaluated at the locations shown in the vector maps of Fig. 3. There are several features of the plot in Fig. 4 that are notable. First, the corre- lation between overlay residuals and displacement residuals is excellent with a correlation coeffi- cient, r=0.985. Second, the extrapolation of the best-fit straight line to a displacement value of zero indicates a corresponding finite and positive overlay value of ~0.2. This result is not unexpected, since it is anticipated that other factors such as pattern placement error, lens errors and wafer distortion from other processes will contribute to the total overlay error. As such the overlay axis intercept provides an estimate of those other factors. Third, the slope of overlay versus displacement line is <1. A slope of less than 1 is consistent with the concept discussed in section 3, that the non-uniform stress component of the displacement field is related to the force acting along the interface or potential for mis-alignment. In this respect, it represents perhaps the maximum expected mis-alignment and the resulting overlay error will be some fraction of the ‘potential’ (i.e. slope <1). In addition, the slope value indicates that surface displacement is a more sensitive metric than overlay in that for the same process variability, surface displacement will change more rapidly than overlay.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

Summary and conclusions

The tightening of overlay budgets at advanced technology nodes has led to a greater importance in understanding and when possible controlling wafer distortion. This paper has provided a description of a novel measurement and analysis approach to quickly and efficiently evaluate the effect of process-induced deformation on surface displacement and its relation to overlay errors. The millisecond annealing case study showed excellent correlation between the displacement residuals and overlay residuals with the correlation coefficient of 0.985. Utilizing the fundamental advantages of the CGS technology, the superfast is well suited for front- side patterned wafer topography measurement. The system allows for rapid measurement of wafer distortion and surface displacement with very high system throughputs. Data maps consisting of >3,000,000 data points can be acquired in seconds on patterned wafers without the need for special targets or dedicated structures.

Reducing plasma-induced damage is key to advancing the scaling limits.

BY MIKHAIL BAKLANOV, JEAN-FRANCOIS DE MARNEFFE, LIPING ZHANG, IVAN CIOFI and ZSOLT TOKEI, imec, Leuven, Belgium 

As semiconductor technology scales below the 20nm node, the capacitance between nearby metal lines increases and this results in loss of speed and cross-talk of the device. To control this unwanted increase in capacitance, insulating layers of porous low-k dielectrics are integrated through plasma etching. Porous organosilicate glasses (or OSGs) are the most popular dielectric materials, but their integration is very challenging. During plasma processing (such as patterning, surface cleaning and resist strip), the porous low-k material suffers from plasma-induced damage which degrades its k value and causes high leakage currents. The damage occurs through depletion of the methyl groups (Si-CH3) which are very sensitive to the active species (radicals, ions and photons) present in the plasma.

FIGURE 1. X-TEM picture of a cryo-etch damascene structure.

FIGURE 1. X-TEM picture of a cryo-etch damascene structure.

A new cryogenic etch method

To bypass these damages, imec researchers have developed a cryogenic low-k etching method. By applying cryogenic temperatures (below -70°C), etch-by products condense and seal the open pores against radical diffusion. Cryogenic etching allows IC manufacturers to reach scaling levels of 20nm and beyond, without compromising speed and device cross-talk. The new method is a good alternative to pore stuffing by sacrificial polymers, which today is intensively studied as a possible way of reducing plasma damage. Pore stuffing is certainly interesting, but has several challenges, namely its impact on the process flow and the possible deformation of the low-k film.

Setting up the experiments

Damage reduction by cryogenic etching was studied in more detail by applying the new method to different OSG films (different dielectric constants and pore structures), and by using different temperatures and etching chemistries. The researchers used a plasma-enhanced chemical vapor deposited (PECVD) OSG-2.0 material with a k value of 2.05 (referred to as ALKB), and a spin-on deposited OSG-2.3 material with a k value of about 2.3 (referred to as NCS). In the experiments, the temperature of the wafer could be varied between -150°C and 40°C by using a liquid nitrogen circulation system and a heating element. Different etching gasses were used, namely SF6, SiF4, O2 and mixtures of these gasses. They used zero bias power to simulate the etching condition along the trench sidewall, and 150W bias power to gain information on the trench bottom.

FIGURE 2. k value (at 100MHz) extracted from capacitance measurements for OSG-2.0 films etched by pure SF6 plasma (a) and SiF4/O2/SF6 plasma (b) at different substrate holder temperatures. Black bars represent the recipe with high bias power to simulate bottom etching, gray bars represent the recipe with 0W bias power to simulate sidewall condition. These results confirm the reduced dielectric degradation at cryogenic temperatures.

FIGURE 2. k value (at 100MHz) extracted from capacitance measurements for OSG-2.0 films etched by pure SF6 plasma (a) and SiF4/O2/SF6 plasma (b) at different substrate holder temperatures. Black bars represent the recipe with high bias power to simulate bottom etching, gray bars represent the recipe with 0W bias power to simulate sidewall condition. These results confirm the reduced dielectric degradation at cryogenic temperatures.

Outcome and protection mechanism

When a SF6 plasma was used, almost no methyl groups depletion (visible as a smaller decrease of the Si-CH3 peaks) was observed when the wafer temperature was below a certain critical level. This observation holds for both bias conditions, and is a first indication of a lower plasma-induced damage. Further investigations reveal that alcohol-like etch by-products are formed at cryogenic temperatures. These reaction products retard the oxidation of the methyl groups, condense on the low-k surface, diffuse into the pores and fill the interconnected pores. These deposited etch by-products protect the low-k films from plasma damage. The etch condensate remains at room temperature, and can be easily removed by high temperature annealing without additional damage to the low-k material. K-value extraction based on capacitance measurements confirms the reduced dielectric degradation at cryogenic tempera- tures. The plasma-induced damage can even be further reduced by adding SiF4 and O2 into the gas discharge. When using this SiF4/O2/SF6 gas mixture, an additional SiOxFy-like passivation layer is deposited which can efficiently protect the dielectric surface.

FIGURE 3. Cross-section transmission electron microscopy (X-TEM) image of a cryo-etch damascene structure. The integrated k value was measured to be 2.38, while the pristine k value was 2.31. The resulting Delta-k is 0.07, which is the lowest Delta-k that has ever been achieved for ultralow-k materials.

FIGURE 3. Cross-section transmission electron microscopy (X-TEM) image of a cryo-etch damascene structure with SBA 2.2 ultralow-k material. The integrated k value was measured to be 2.38, while the pristine k value was 2.31.
The resulting Delta-k is 0.07, which is the lowest Delta-k that has ever been achieved for ultralow-k materials.

A threshold temperature, depending on pore size and porosity

The researchers also found that these phenomena occur below a critical wafer temperature and that this temperature depends on the porosity and pore size of the low-k material. While for the ALKB material (open porosity 46% and pore diameter 3.0nm), carbon depletion is suppressed at temperatures lower than -70°C, a temperature lower than -120°C is needed to suppress carbon depletion within the NCS material (open porosity 35% and pore diameter 2.0nm). This dependence is explained by the Kelvin equation predicting that the vapor condensation in pores happens at critical relative pressures which depend on the pore size.

Pattern transfer and future outlook

We are currently developing a modified approach, in which initial reactants are condensed instead of etch by-products. First results are very promising for industrial take up, since etch temperatures can be increased up to -50°C.

Also, the pattern transfer capabilities of cryogenic etching are being investigated. This includes a study of the mechanism of hard-mask preservation at cryogenic temperatures. The final goal is an accurate and complete pattern transfer, up to the bottom of the OSG film.

Acknowledgement

It is our great pleasure to thank our colleagues from GREMI Orleans (France) and Oxford Instru- ments (UK) for the joint experiments and for the possibility to use their cryogenic etch equipment.

References

1. M.R.Baklanov, F.Iacopi, S.Vanhaelemeersch. Patent US 8,540,890 B2, Sep. 24, 2013.

2. L. Zhang, R. Ljazouli, P. Lefaucheux, T. Tillocher, R. Dussart,Y. A. Mankelevich, J.-F.de Marneffe, S. de Gendt and M. R. Baklanov. ECS Sol. St. Lett., 2, 2, N5- N7 (2013) and ECS J. Sol. St. Sci. Tech., 2 (6) N131- N139 (2013).

3. M. R. Baklanov, L. Zhang, R. Dussart, J.-F. de Marneffe. IEEE International Interconnect Technology Confer- ence (IITC), Kyoto, June 2013. Invited talk

4. M. R. Baklanov, L. Zhang, J.-F.de Marneffe, R. Dussart, A. Goodyear. Materials for Advanced metallisation (MAM’20)

MIKHAIL BAKLANOV is a principal scientist at imec, JEAN-FRANCOIS DE MARNEFFE is a senior scientist, imec, LIPING ZHANG is a PhD researcher at imec and KU Leuven, IVAN CIOFI is a senior scientist, imec, and ZSOLT TOKEI is program director nano interconnects, imec.

By Paula Doe, SEMI

Investors are still looking for differentiated technologies that solve high-value problems in semiconductor manufacturing, or that bring semiconductor technology to disruptive applications in other fields, particularly in the medical and environmental sectors, said the leading venture capitalists gathered at the Silicon Innovation Forum at SEMICON West 2014.

“As financial investors have moved to fund more ‘flapping bird’ apps instead of hardware, strategic investors have moved more to early-stage hardware opportunities,” noted Robert Maire, president, Semiconductor Advisors.

Tallwood Ventures general partner George Pavlov concurred that his financial investment firm was making fewer hardware investments because the technology is maturing and there are fewer opportunities, as well as the lower margins and lower exit prices. “The app maker gets $1 a shot, which is more than the chip maker,” another VC put it more bluntly. That means that semiconductor investments need creative strategies to reduce risk, such as one recent deal that involved three strategic investors all interested in helping the startup succeed, including a customer and a supplier. “It’s also important to have a capitalist at the table to assure that the company’s interest comes first,” Pavlov noted, which may involve making the difficult moves like rebalancing leadership teams or reconstituting the Board of Directors.  Financial investors can also come in early with an experienced team that can help a company find the right strategic partners they need and introduce them.

Strategic investors are getting more involved with early-stage companies to reduce risk even if it means collaborating with the competition. “More and more we are collaborating in investments, and we will see more in the future, in both big and small companies, depending on the size of the problem, when fundamental industry interests are aligned,” said Sean Doyle, director, Intel Capital. “We see greater pull from financial investors to have strategic investors involved from the beginning.” More handholding is needed even before investment. Kurt Petersen, a member of the Band of Angels, noted that three of the group’s members spent two years mentoring a company before it was ready even for angel investment. In fact, a MEMS company may need a strategic investor to even convince a foundry to take it on.

“More than half the investments we’ve made in the last year have been with other strategic investors,” concurred Eileen Tanghal, general manager of Applied Ventures, adding that investing with Intel and Samsung for customer input was especially useful.

Semiconductor startups to watch: The VCs’ current favorites

So where are these investors putting their money in the semiconductor sector these days?  Primarily it’s either towards technologies with potential to solve next-generation semiconductor manufacturing challenges, or towards extending conventional semiconductor technology to new fields, from medicine to agriculture. The strategic investors from the venture arms of Samsung, Intel and Applied Materials all cited innovative materials solutions as the investments about which they were currently most excited, particularly Inpria for its high-resolution metal oxide photoresists, SBA Materials for its liquid-phase self assembled porous ultra low-k dielectrics, and Voltaix (recently acquired by Air Liquide) for its unique precursor gases for germanium and other chemistries. “We’re making more investments in equipment and materials because it is becoming incredibly difficult to advance the technology,” said Dong-Su Kim, senior director, Samsung Ventures Investment Corp.

The VCs saw a wider range of investment opportunities in applying silicon technology to other fields, especially if time-to-market and development costs can be reduced by re-using existing technology.  Peter Moran, general partner, DCM, cited RayVio as a good example, making high power UV LEDs specifically for sterilizing surfaces, with both cost and performance that have no competition from traditional wet or heat methods.  Another of his favorites is battery maker Enovix, which leverages  existing thin-film photovoltaics technology and invovates the battery structure itself for a battery that could potentially store 3X the charge per area. The financial VC worked with strategic investor  Cypress who brought specific manufacturing and scaling expertise from its Sunpower experience, while Intel brought its experience in identifying where, globally, was best to build the manufacturing plant.  Moran also noted that DCM previously did not consider devices that sold for less than a dollar, but it is now looking at lower cost devices as long as they are differentiated and high volume, such as ingestible sensors that track if people have taken their pills.

“The most opportunity is in proliferating silicon technology into other fields, especially in the medical field,” concurred Tanghal, citing Applied Venture’s investments in Oncoscope’s optical screening for pre-cancerous cells to significantly improve the accuracy of biopsies compared to the usual random sampling, Twist Bioscience’s platform for large-scale synthetic gene manufacturing, and  MTPV Power Corp.’s chips that convert heat to electricity.  Applied Ventures is also looking at ongoing opportunities for capturing more value from the inflection point of the emerging Internet of Things, such as supplying the materials for, or the service of, making implantable or ingestible coatings.

The MEMS field continues to come up with new kinds of electromechanical structures for new tasks.  Peterson said he was particularly excited about Chirp Microsystems for its ultrasonic gesture recognition, Next Input with its force-sensitive touch screen technology, and Lumedyne Technologies for its completely new, high accuracy, inertial sensor approach.

VC panels choose Amorphyx and Aledia for best startup pitches

The panel of leading investors selected two companies offering disruptive materials/process technologies — and leveraging a collaborative infrastructure — for the best pitches from among 25 selected startups at the event. Aledia says its microwire LEDs grown on 8-inch silicon should cost 2x-3x less than conventional LEDs grown as thin films on sapphire. The ~1µm diameter pillars, with the active quantum well layers grown vertically in concentric layers, provide more light emitting surface area from less material in less time in the MOCVD reactor.  Their small area on the wafer likely helps ease the lattice and thermal mismatch issues compared to blanket GaN on silicon.  Co-founder, president and CEO Giorgio Anania said the company has figured out how to grow regular, high quality pillars through holes in a mask, though lumens/watt remains low and is not the current focus of improvement. Based on the CEA campus in Grenoble, the startup plans to grow only the pillar layer, then send the wafers out to a mainstream CMOS foundry for the rest of the processing.

The other winner, Amorphyx, offers a fast switching, low cost backplane solution for displays, using a kind of tunneling effect through a near-perfect amorphous sapphire insulating layer in a metal-insulator-metal device. The company is working at ITRI in Taiwan with a production collaborative it put together  three Asian companies, aiming at start joint production in 2015. “This should save $100 of the cost of a $400 display,” claimed CEO and President John Brewer.

Among the other interesting startups pitching to the investors at the event was MEMS microphone startup Baker-Calling, with an innovative simplified design for an AlN piezoelectric MEMS microphone, using four separate triangular plates free to expand and contract so they are less sensitive to film stess than the usual capacitive membranes. CEO Matt Crowley reported the company has sampled prototypes to its strategic investor, and is now bringing up the process at a foundry.

Okeanos Technologies showed its microfluidics desalinization technology, which CEO Tony Frudakis reported uses half the energy to remove salt from water compared to the usual reverse osmosis, because the tiny volumes react better, using an electrochemically mediated process that strips off ions as they pass through the small channel.  However, each pass removes only about 10% of the salt, so multiple cells would be needed to remove all the salt from significant volumes of water.

Inpria leverages grant money for years to take university research towards commercial

The venture arms of Applied Materials, Intel and Samsung have all recently invested in Inpria, and kept citing it as an example of semiconductor development they were excited about for its potential solution to the key problem of resolution of next generation photoresist. Replacing the long, tangled, polymer molecules of traditional photoresist with the smaller inorganic molecules enables cleaner edges and reduces collapse of 7nm and 10nm features.  CEO Andrew Grenville reported that the line-width roughness with this resist is half that of conventional polymer products (0.7nm vs 1.5nm) on 10nm lines and spaces.

Grenville told the tale of the company’s earlier years of leveraging its capital as it developed the metal oxide cluster technology from Oregon State University, starting with NSF/SBIR funding, then a grant from Oregon’s Onami, then joint development funding with potential users. Inpria first developed the material using shared equipment of the Onami university network, then the SEMATECH microexposure tool at Laurence Berkeley national lab, and then in joint development programs at imec’s consortium in projects with equipment suppliers and customers – for about five years before the technology was developed enough for angel investors and Applied Materials. This year strategic investors Intel and Samsung joined Applied in further funding, which then attracted more from the Oregon Angel Fund, with deep semiconductor experience and connections. “We expect we will be interesting for a financial investor in a couple of years,” said Grenville. “It takes leveraging, leveraging, leveraging for capital-efficient development…though the proof will come in 2015 when we go into the fabs.”

The next Silicon Innovation Forum at SEMICON West will be held on July 14, 2015. In addition, SEMICON Europa 2014 (October 7-9) will offer an Innovation Village with a Silicon Innovation Forum.


By David W. Price and Douglas G. Sutherland

Introduction to the Series:

This is the first in a series of 10 installments which will discuss fundamental truths about process control—inspection and metrology—for the semiconductor industry. By fundamental, we imply the following:

  • Unassailable: They are self-evident, can be proven from first principles, or are supported by the dominant behavior at fabs worldwide
  • Unchanging: These concepts are equally true today for 28nm as they were 15 years ago for 0.25µm, and are expected to hold true in the future
  • Universal: They are not unique to a specific segment of process control; rather they apply to process control as a group, as well as to each individual component of process control within the fab

Each article in this series will introduce one of the 10 fundamental truths and discuss interesting applications of these truths to semiconductor IC fabs. Given the increasing complexity of advanced devices and process integration, process control is growing in importance. By understanding the fundamental nature of process control, fabs can better implement strategies to identify critical defects, find excursions, and reduce sources of variation.

The first fundamental truth of process control for the semiconductor IC industry is:

You can’t fix what you can’t find. You can’t control what you can’t measure.

While it’s true that inspection and metrology systems are not used to make IC devices—they do not add or remove materials or create patterns—they are critical for making high-yielding, reliable devices. By finding defects and measuring critical parameters, inspection and metrology systems monitor the hundreds of steps required to manufacture a device, ensuring the processes meet strict manufacturing specifications and helping fab engineers identify and troubleshoot process issues when there is an excursion.  Without inspection and metrology, it would be near impossible for fabs to pinpoint process issues that affect yield. However, it’s not enough to simply “find” and “measure”—a fab’s process control strategy needs to be capable and cost-effective.

Capable inspection and metrology strategies find and measure the defects and parameters that affect device yield. Cost-effective inspection and metrology is performed at the lowest total cost to the factory, where total cost is the sum of the cost of lost yield plus the cost of process control.

First, Make it Capable:

If you can’t find it, you can’t fix it.  At the heart of this truth is the understanding that, above all else, a fab’s inspection and metrology strategy must be capable. It must highlight the problems that are limiting baseline yield.  It must also provide actionable information that can enable fabs to quickly find and fix excursions.

Fig 1 Fig 2

 

Figure 1.  You can’t fix what you can’t find.  And you can’t control what you can’t measure. Left:  P-MOS SiGe critical dimension measurement. Right:  Fin patterning particle leading to a Fin Spire defect at post dummy gate etch. Source: KLA-Tencor 

We emphasize this need for capability first because we have observed that some fabs are too quick to sacrifice capability for cost reductions. No strategy is cost-effective if it doesn’t accomplish its fundamental objective.

Below are specific questions that can help fab management evaluate the capability of its process control strategy:

  • Are you finding all sources of your defect-limited yield? Are you finding these in-line or at end-of-line?
  • Does your defect Pareto have sufficient resolution of the top yield-limiters in each module to direct the most appropriate use of factory engineering resources?
    • Have you fully characterized all of the important measurements and defect types (size range, kill ratio, root cause, solution)?
    • Do you understand the most probable excursion scenarios?  What is the smallest excursion that you absolutely must detect at this step?  How many lots are you willing to have exposed to this excursion before it is detected?
    • Are you inspecting and measuring at all the right steps?  Can you quickly isolate the point of formation for excursions?  Can you quickly disposition potentially affected lots?
    • Does a particular defect signature become confused by defects added at subsequent process steps? Or do you need separate inspections at each step in order to partition the problem?
    • Do you have overlapping inspections to guard against the high-frequency, high-impact excursions?
      • What is the alpha risk and beta risk for each inspection or measurement?  How are these related to the capture rate, accuracy, precision, matching and more?

Then, Make it Cost-Effective:

Once a capable strategy is in place, then a fab can start the process of making it cost-effective. The best known method for optimizing total cost is usually adjusting the overall lot sampling rate.  This is generally preferred because the capability remains constant. In some cases, it may be possible to migrate to a less sensitive inspection (lower cost of ownership tool or larger pixel size); however, this is a dangerous path because it re-introduces uncertainty (alpha/beta risk) that reduces a fab’s process control capability. This concept will be discussed in more detail in our next article on sampling strategies.

Finally, it is worth pointing out that it is not enough to implement a capable strategy. The fab must ensure that what was once a capable strategy, stays a capable strategy. A fab cannot measure with a broken inspection tool or trust a poorly maintained inspection tool. Therefore, most fabs have programs in place to maintain and monitor the ongoing performance of their inspection and metrology tools.

By optimizing process control strategy to be capable and cost-effective, fabs ultimately find what needs to be fixed and measure what should be controlled—driving higher yield and better profitability.

About the Authors:

Dr. David W. Price is a senior director, and Dr. Douglas Sutherland is a principal scientist at KLA-Tencor Corp.  Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Check out other Process Watch articles: “Exploring the Dark Side,”“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

By Brian Cronquest, Vice President, Technology & IP, MonolithIC 3D Inc.

Hughes Metras, Leti’s VP of Strategic Partnerships North America, introduced the lead talk at their SemiconWest 2014 Leti Day about monolithic 3D technology as the “solution for scaling.” Hughes presented the Leti device technology roadmap which showed monolithic 3D (M3D) as an alternative to scaling from the 2Xnm nodes to well past 5nm. Here’s the important piece of that roadmap, which highlights the partnership with Qualcomm (ST and IBM helped with some of the work as well):

Fig 1

 

The lead talk was given by device scientist Olivier Faynot, Leti’s Device Department Director.  He titled his talk “M3D, a disruptive approach for further scaling,” and began with why the industry needs a solution for scaling.

Most in the industry are in agreement that scaling past the 22nm node, while still quite technically feasible, has priced itself out of most markets. Olivier discussed the what (transistor costs are no longer decreasing) and the why (litho cost escalation and connectivity inefficiencies of energy and delay). And then he made the statement: “if we just keep the current (2Xnm) technology, we can go farther in cost scaling.” [note: see the following blogs and comments for more info on this crucial topic:  Tech Design Forums summary “3D and EDA need to make up for Moore’s Law, says Qualcomm” and Zvi-Or-Bach’s EETimes blogs Qualcomm Calls for Monolithic 3D IC and  28nm – The Last Node of Moore’s Law.]

Oliver showed a summary of a DAC2014 paper and a Qualcomm/GeorgiaTech DAC2014 paper Power/Performance/Area analysis of M3D for an FPGA:

Fig 2

 

The solution is to build the stack sequentially, in a monolithic fashion. Olivier described their monolithic 3D, or sequential 3D, process flow where the lower-level (first layer) of transistors and its interconnect are conventionally made, then inter-level metal is crafted to help the vertical interconnection, and then a second layer of monocrystalline silicon is layer transferred and oxide-oxide low temperature bonded to the top of the inter-level metal dielectric. This is a blanket layer so there are no alignment issues such as those suffered by the thick layer and pre-made (TSV) parallel processing flows. The layer that is transferred in M3D is very thin (10-200nm final), so that direct alignment thru that thin layer to the lower level alignment marks can be made with conventional equipment and achieve conventional alignment tolerances (single digit nanometers).

Now upper-level transistors are formed utilizing SPER (Solid Phase Epitaxial Regrow) for junction doping at 475-600°C and other lower (<400°C) temperature processing for gate stacks, etc. The upper-level and inter-level vertical interconnect is then processed, again with full alignment capability to the lower layer. Note that the lower level transistor Ni salicides are stabilized with platinum co-deposition and fluorine/tungsten implantation to enable their survival at the 475-600°C SPER thermal exposure.

Fig 3

 

Oliver also talked about using laser annealing to activate implanted dopants and repair damages during upper-level transistor processing. He called the laser (pulsed and short wavelength) option of solving the thermal challenge of monolithic 3D as the “crème brûlée” of methods and they were ‘seeing good results.’ Hopefully we will see published data soon. For more information on SPER and laser processing please see my recent blog Monolithic 3DIC: Overcoming silicon defects.

Fig 4

 

Oliver was also asked in the Q&A if stress was a big issue. He replied that stress was not an issue, rather, the biggest challenges were integration ones (how to form a low temp top transistor, stability of the local interconnect level, and the bottom transistor salicide stability). Olivier was asked in the Q&A what the observed performance differences were between the upper-level and lower-level transistors. He replied” Currently we are achieving 95% (of the lower for the upper). We believe we can make 100%.”

Leti has a 14nmPDK ready to go for those who want to design a test circuit in their monolithic 3D flow. They have ELDO, HSPICE, Virtusoso, Calibre, StarRC, etc. files available.

Fig 5

 

Not too surprisingly, the Qualcomm logo showed up on some of the Leti presentation slides. Back in December 2013, Leti signed an agreement to work with Qualcomm – Qualcomm to Evaluate Leti’s Non-TSV 3D Process. ST and IBM have also been working with Leti in various aspects, for example, IBM & Leti used COMPOSE3 to simulate a monolithic InGaAs nFET monolithically over a SiGe pFET on SOI.

CEA-Leti has been busy working on processing flows to enable monolithic 3D devices since before 2009. Perrine Batude won the 2009 Roger A. Haken Best Student Paper Award for the IEDM 2009 paper entitled, “Advances in 3D CMOS Sequential Integration,” where she showed results for a sequentially processed P over N (no metal between transistors layers) testchip Batude’s 2011 IEDM paper showed a 50nm 3D sequential structure on 10nm channel silicon:

Fig 6

 

CEA-Leti also opened a complete 300mm fab extension dedicated to 3D-integration applications, both parallel and monolithic, with an inauguration event in January 2011. As well, back in December 2013, Soitec and CEA renewed their long-standing partnership for an additional five years.

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. I would like to invite you to the IEEE S3S Conference: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference will be held October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

See you there!

China’s massive investments in light-emitting diode (LED) manufacturing capacity are paying off, with a Chinese company entering the top ranks of the global market for the first time ever, according to IHS Technology.

China’s MLS Electronics Co. Ltd. in 2013 rose to the No. 10 rank in the worldwide market for packaged LEDs, up from 14th place in 2012. With the other top 10 players based in South Korea, Japan, the United States, Germany and Taiwan, as presented in the attached figure, this represents a first for China’s burgeoning LED industry.

2014-06-18_LED_Rank_Final

“Since 2011, most of the new LED production capacity that has been added worldwide has occurred in China,” said Jamie Fox, principal LED analyst for IHS. “Because of this, it was inevitable that Chinese companies eventually would penetrate the ranks of the top 10 LED suppliers. MLS was first to join the global elite, having established itself as the clear leader in the Chinese market by capitalizing on strong domestic demand. For the major suppliers, MLS’s ascent into the market’s upper ranks represents a clear signal that Chinese firms soon will become major competitors in the global LED business.”

These findings come from the IHS LED Intelligence Service.

China’s LED market lights up

MLS is one of many Chinese LED suppliers that have sprung up amid the surge in production. However, the other firms do not even rank among the top 20 global suppliers. China’s LED supply base is massive and highly fragmented, with thousands of small manufacturers located across the country.

“Despite leading the domestic market, MLS accounted for less than 10 percent of Chinese LED revenue in 2013,” said Alice Tao, China LED analyst at IHS. “The next five largest LED suppliers in China represented only about 20 percent of the market.”

With the rise of LED manufacturing capacity in China, concerns have risen relating to overcapacity. Some of the equipment purchased for metal-organic chemical vapor deposition (MOCVD) manufacturing—the most important process step in LED production—is now sitting idle in China. Observers have fretted that the overcapacity could result in the shutdown of some Chinese suppliers.

However, only a few of the smaller Chinese vendors so far have closed their LED operations. Most of the top companies remain active in the market, with some posting strong profit margins.

An insular market goes global

MLS and the smaller Chinese suppliers mostly compete among themselves for a share of the large domestic LED market. The international portion of sales for these companies is very small.

At the same, the extremely low prices in the Chinese market make the country inaccessible to overseas suppliers. Because of this, foreign LED makers don’t encounter Chinese competitors very often.

But that situation will change rapidly. IHS expects the LED revenues of Chinese vendors to grow steadily over time, as the country’s economy continues to grow strongly. Because of this, Chinese LED suppliers will begin to sell more internationally and come into competition with foreign rivals.

Barriers to entry

Both intellectual property and quality are concerns for international customers that are considering Chinese suppliers.

However, several factors suggest these concerns could be alleviated over time. These factors include patent expirations, China’s established history in other industries, the sheer volume of manufacturing capacity in the country and the fact that many LED lamps are assembled in the nation.

Top-tier LED suppliers such as Nichia, Osram, Lumileds and Cree so far have seen only a small impact from Chinese vendors on their sales. This is especially true in the market for general lighting in regions such as Europe and the Americas. Such will not necessarily be the case by the end of the decade.

For instance, MLS has started 2014 on a strong note, and may have even ranked among the IHS top 10 LED suppliers in the first quarter.

One out of every four dollars spent worldwide on light-emitting diode (LED) drivers in 2013 was used for lighting applications, illustrating the growing importance of illumination in the LED business, according to IHS Technology.

LED driver revenues from lighting applications last year totaled $305 million, representing 25 percent of the total driver market of $1.2 billion, as presented in the attached figure. The LED lighting market will continue to boom in the coming years, causing revenue for associated drivers to nearly triple to $893 million in 2019. This will amount to 43 percent of the $2.1 billion LED driver market.

2014-06-19_LED_Driver

“Lighting represents the fastest-growing segment of the LED market, and is accounting for a larger share of market revenue—as well as of overall driver sales,” said Jamie Fox, principal LED analyst for IHS.

The lighting segment mainly consists of lamps and luminaries, with flashlights, architectural illumination and other applications representing a smaller share of the market. Lamps accounted for most of the lighting units shipped in 2013, and for 50 percent—or $151 million—of the revenue for all lighting ICs. This share is set to increase.

The information in this release is derived from the report entitled “LED Driver ICs — World” from the Lighting & LEDs service at IHS.

Driving to growth

An LED driver is an integrated circuit (IC) that manages and controls the electrical current for an LED.

LED driver ICs play an important role in energy savings and are used to support most high-brightness LEDs. Drivers are regarded as an important, if not essential, feature in high-quality LED lighting products.

Beyond the lighting segment, there are also significant sales of driver ICs to diverse applications such as signage, mobile handsets, TVs, notebooks, monitors and tablets, as well as automotive applications.

Price pressure lightens up

LED drivers aren’t subject to the same brutal price erosion that’s impacting the LED market itself. As a result, LED driver revenue will rise by double-digit percentages in 2014, 2015 and 2016.

Furthermore, unit sales of dimmable LED lamps are outgrowing those of non-dimmable lamps. The average price of drivers for non-dimmable lamps is much higher than dimmable lamps, helping maintain strong revenue growth.

Texas Instruments drives to the top

Texas Instruments maintained its position as the leading supplier of LED driver ICs in 2013, followed by STMicroelectronics.

In the signage segment of the market, Taiwan’s Macroblock remained the leader. Meanwhile, Western semiconductor giants played prominent roles in other segments, including companies such as On Semiconductor, Maxim, NXP, Skyworks, ams and Power Integrations.

While suppliers overall focus on different markets, most of the companies that are expected to continue growing will remain directed toward a lighting market that already accounts for a quarter of the total business, and will continue to grow as LED lamp sales increase rapidly during the next few years.

The global market outlook for AC-DC and DC-DC power supplies is set for healthy expansion starting this year until at least 2018, with revenue during these four years projected to grow by $3.5 billion, according to a new report from IHS Technology.

Market revenue will expand to $25.1 billion in 2018, up from $21.6 billion in 2014, as presented in the attached figure.

The hefty four-year increase is an improvement compared to the previous three years from 2010 to 2013, when revenue grew by less than $1.0 billion. Growth this year is anticipated at 4.6 percent, with expansion to be as robust or even strengthen in 2015 and 2016.

“The markets for most applications that use a power supply are now growing again after a couple of gloomy years, with emerging applications such as power supplies for light-emitting diode (LED) lighting and media tablets leading the way,” said Jonathon Eykyn, power supply and storage component analyst for IHS. “Demand for power supplies for these two applications alone is projected to grow by more than $2.5 billion from 2014 to 2018, but other power supply markets—such as telecommunications, data communications and industrial—are also projected to provide growth opportunities to power supply vendors in the coming years.”

Aside from emerging applications driving growth, many projects that had been cancelled or postponed because of economic concerns in the past are now being restarted to coincide with new projects and technology rollouts, further stimulating the market. Also fueling significant expansion in the demand for power supplies is the continued growth of data centers to cope with the rise of cloud computing and the Internet of Things. Thanks to such drivers, revenue for power supplies to the server, storage and networking markets is projected to climb 24 percent from 2014 to 2018.

Growth is also solid in the markets for cellphone power supplies, with revenue forecast to ascend more than 8 percent in 2014. However, growth will slow after this year as more phones begin to ship without a bundled charger.

Meanwhile, the power supplies market for desktop PCs and notebooks is calculated to decline by around 2 percent every year from 2014 to 2018. This is because the traditional computing markets of desktop PCs and notebooks are set to deteriorate as consumers continue to favor more mobile solutions, such as media tablets and even cellphones.

All of these changes are influencing the state of the power supply market. In particular, market share rankings for 2013 were turbulent with six of the top 10 manufacturers changing positions and two new companies entering the elite tier. Overall, Delta Electronics retained its position as the world’s largest supplier of merchant power supplies, followed by Emerson and Lite-On.

The two suppliers that grew the most in market share in 2013 were Salcomp and Mean Well, whose combined revenue rose more than 30 percent and added 1.3 percent to their share of market compared to 2012.

“These suppliers are well-entrenched within the fast-growing cellphone and LED lighting markets,” Eykyn said. “It’s clear from these results that other manufacturers will have to continue to diversify their portfolios in order to remain competitive.”

These findings can be found in the forthcoming report, The World Market for AC-DC & DC-DC Merchant Power Supplies from the Power & Energy service of IHS. The full report from IHS includes analysis of the opportunities for commodity AC-DC, as well as non-commodity AC-DC and DC-DC power supplies across 22 applications, with forecasts through 2018. It also presents market-share estimates with 13 separate splits.