Tag Archives: letter-semi-tech

By Paula Doe, SEMI

For medtech applications to flourish, sensors need a supporting infrastructure that translates the data they harvest into actionable insights, says Qualcomm Life director of business development Gene Dantsker, who will speak about the future of digital healthcare in the Medtech program at SEMICON West. “Rarely can one device give a complete diagnosis,” he notes. “What’s missing is the integration of all the sensor data into prescriptive information.”

The maturing medtech sector has developed to the point where sensors can now capture massive amounts of data, conveniently collected from people via mobile devices. The sector now has higher compute capacity to process the data, and improving software can produce actionable insight from the information. The next challenge is to seamlessly integrate these components into legacy medical systems without disrupting existing workflow. “Doctors and nurses don’t have time for disruptive technology – a new system has to be invisible and frictionless to use, with one or fewer buttons, no training and truly automatic Bluetooth-like pairing,” he says. “So device makers need to pack all system intelligence into the circuits and software.”

Getting actionable healthcare information from sensors requires integration into the existing medical infrastructure. Source: Qualcomm Life

One interesting example is United Healthcare’s use of the Qualcomm Life infrastructure to collect data from the fitness trackers of 350,000 patients. The insurance company then pays users $4 a day, or ~$1500 a year, for standing, walking six times a day and other behaviors that clinical evidence shows will both improve patient health and reduce healthcare costs. “It’s a perfect storm of motivations for all stakeholders,” he says.

Next hot MEMS topics: Piezoelectric devices, environmental sensors, near-zero power standby

With sensor technology continuing to evolve, look for coming innovations in MEMS in piezoelectric devices, environmental sensors and near zero-power standby devices, says Alissa Fitzgerald, Founder and Managing Member of A.M. Fitzgerald and Associates, who will provide an update on emerging sensor technologies in the MEMS program at SEMICON West.

Piezoelectric devices can potentially be more stable and perhaps even easier to ramp to volume than capacitive ones, with AlN devices for microphones and ultrasonic sensors finding quick success. Now the maturing infrastructure for lead zirconate titantate (PZT) is enabling the scaling of production of higher performing piezo material with thin film deposition equipment from suppliers like Ulvac Technologies and Solmates and in foundry processes at Silex and STMicroelectronics, she notes.

In academic research, where most new MEMS emerge, market interest is driving development of environmental sensors and zero-power standby devices. With demand for environmental monitoring growing, much work is focusing on technologies that improve the sensitivity, selectivity and time of response of gas and particulate sensors. Research and funding is also focusing on zero or near-zero power standby sensors, using open circuits that draw no power until a physical stimulus such as vibration or heat wakes them up.

MEMS, however, likely won’t find as much of a market in autonomous vehicles as once thought. “While the automotive sensor market will need many optical sensors, MEMS players are competing with other optical and mechanical solutions,” says Fitzgerald. “And here the usual MEMS advantage of small size may not matter much, and the devices will have to meet the challenging automotive requirements for extreme ruggedness.”

By Deb Vogler

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.

Diverging viewpoints on EUVL readiness for 5nm

Mike Lercel, Director of Strategic Marketing at ASML

ASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”

Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.

ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”

Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of America

Renwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”

Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America

When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers’ public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i’s better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it’s too early to say.

Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It’s unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”

Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIES

Levinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).

Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.”

Mask development for 5nm

Christopher C. Progler, CTO & Strategic Planning at Photronics

Progler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.”

More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.

“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.”

Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; Source: GLOBALFOUNDRIES

Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.”

How does the industry get to 3nm?     

ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”

Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”

At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame.

Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. “We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.

At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.

Originally published on the SEMI blog.

By Michaël Tchagaspanian, Vice President of Sales and Marketing, Leti

Digital disruption begets innovation. Challenges equal opportunities. Those were clear messages during Leti Innovation Days recently in Grenoble, France. Over two days at the annual event, which this year coincided with Leti’s 50th anniversary, speakers and exhibitions highlighted challenges of the digital revolution and presented specific current-and-anticipated solutions for industry, healthcare and energy and the environment.

Coinciding with the launch of the administration of French President Emmanuel Macron, who has already talked of France becoming “a start-up nation”, Leti also noted the importance of creating and supporting startups that will help consumers, companies and countries address the challenges and opportunities of the digital revolution.

Citing challenges in the energy sector, Thierry Lepercq, executive vice president of research, technology and innovation at the international French energy company ENGIE, warned of potential energy blackouts and financial problems for traditional energy providers due to the growing penetration of alternative energy sources, the switch from fossil fuels – and energy sharing by households.

These developments, which ENGIE calls “Full 3D” – decarbonization, decentralization and digitalization – have destabilized traditional power systems and providers.

For example, a German residential battery-storage supplier allows residents to store energy at home and swap it on the grid, cutting out traditional electricity providers. Lepercq also noted that the rapid growth in the use of electric vehicles can load the grid with demand that was not anticipated even a few years ago. But the digital revolution also has prompted entrepreneurial responses. EV-Box, the Dutch company that has deployed more than 40,000 vehicle-charging stations in 20 countries, is gathering usage data, which will help officials understand the vehicles’ demands on the grid.

ENGIE acquired EV-Box this year as a strategic step towards operating in a completely new global energy paradigm.

Driving toward a new economy

Last month, Intel released a study that predicted autonomous vehicles will create a “Passenger Economy” – with mobility-as-a-service – that could grow to $800 billion in 2035 and to $7 trillion by 2050.

With autonomous vehicles, the car will no longer be a “stand-alone vehicle”, but “something that reacts with the environment”, said Mike Mayberry, corporate vice president and managing director of Intel Labs. Intel has opened advanced vehicle labs in the U.S. and Germany to explore the various requirements related to self-driving vehicles and the future of transportation. That includes sensing, in-vehicle computing, artificial intelligence, connectivity, and supporting cloud technologies and services.

When a panel discussion on driverless cars was asked when these vehicles will be in general use, Jean-François Tarabbia, CTO of Valeo, the automotive supplier to automakers worldwide, said “the better question is ‘why’”. And that depends in part on the industry’s ability to demonstrate vehicle safety. He said that traffic jams could be reduced by 30 percent with autonomous cars. Still, the cars will require a driver inside who will do something other than driving until he or she is needed to operate the vehicle.

Pierrick Cornet, brand incubator at Renault Nissan, said autonomous cars also will have to accommodate owners who occasionally want to drive their vehicles. For carmakers like Renault Nissan, the challenges are managing the cost and weight of the vehicles, which are loaded with batteries, as well as computing and sensing gear – and making them able to charge quickly.

Fabio Marchiò, automotive digital general manager at STMicroelectronics, noted that cars are the least-used appliance/machine in the household. He agreed with Tarabbia that safety and consumer resistance are primary roadblocks for the vehicles, but added that government regulations could slow down their widespread use.

Moore’s Law obtains

Outlining some of Intel’s R&D programs, Mayberry brushed aside frequent predictions that Moore’s Law has run its course. He said Intel expects Moore’s Law to be in effect at least through the next decade, because of the industry’s continued evolution to smaller technology nodes with new IC technologies.

In addition to focusing on enabling Moore’s Law going forward, Intel’s research on components and hardware includes developing novel integration techniques. But Intel Labs also is focused on enabling future product capabilities and “imagining what’s next”.

As part of that effort, Intel Labs has partnered with Princeton University to decode digital brain data, which is scanned using functional magnetic resonance imaging (fMRI). The goal is to reveal how neural activity gives rise to learning, memory and other cognitive functions such as human attention, control and decision-making.

Leti and Intel agreed last year to collaborate on strategic research programs, including the Internet of Things, high-speed wireless communication, security technologies and 3D displays.

Quantum computing

Also peering into the more-distant future, Leti CEO Marie Semeria noted development of Leti’s Si-CMOS quantum-technology platform.

“The quantum topic has recently become central, thanks to the huge advances made in solid-state implementation, both in superconducting systems and in silicon technologies,” she said. “Interest in silicon-based technologies is huge because of their reliability and their capability to reproduce industrial standards along with the low-noise characteristics and low variability of CMOS devices.”

Noting that the University of New South Wales recently demonstrated a promising two-qubit logic gate based on the silicon-28 isotope, Semeria said Leti had demonstrated the compatibility of such circuits with state-of-the-art CMOS processes.

“From an architectural point of view, it is clear that the future quantum computer will be hybrid. It will combine a quantum engine with a classical digital computer,” she explained. “The program that will run on such a machine will need to combine at least two computing models: a classical part, to prepare data and process results, and a quantum one. A tight connection between the two programming models will be necessary.”

With its history of pioneering in technology and its culture of spinning out new companies to further develop and commercialize innovative technologies, Leti is poised to help France achieve Macron’s goal: “I want France to be a ‘start-up nation’, meaning both a nation that works with and for the start-ups, but also a nation that thinks and moves like a start-up.”

Leti has launched 64 startups, including 13 in the past four years.

Digital innovations in healthcare

Jai Hakhu, president & CEO of HORIBA International Corporation (U.S.), explained how the digital revolution is creating in vitro diagnostics business potential by enabling delivery of preventive healthcare services in even remote regions of the world. In one of HORIBA and Leti’s joint projects, they are developing a hematology, microfluidics-based, lensfree, point-of-care and home-testing system that can be used in underdeveloped countries.

The collaboration is helping realize HORIBA’s vision of providing preventive self-testing anywhere in the world.

Leti’s start-up Avalun has developed a portable medical device for multiple-measurement capabilities using point-of-care testing. Other recent healthcare-related startups include Diabeloop, which is in the final stages of testing an artificial pancreas, and Aryballe Technologies, which is developing olfactory and gustatory sensors.

Routes to innovation

Those new companies were among the presenters at Leti’s immersive exhibition, “Routes to Innovation”, which was the focus of day two of the event. Entrepreneurs and Leti scientists offered more than 60 demonstrations of patented technologies, to show with concrete examples how Leti’s technological know-how and industrial transfer expertise can help French and international companies innovate and become more competitive.

The three “Digital Revolution” topics included “Micro-Nano Pathfinding”, showing how the diversity of Leti’s digital technologies are available to all economic sectors; “Cyber Physical Systems”, and “Business-Model Disruption”.

The “Environmental Transition” demos covered “Sustainable Activities”, “Monitoring Our World’ and “More with Less”. The “New Frontiers for Healthcare” demos covered “Prevention, Independence, Well Being”, “New Therapies” and “Analysis & Diagnosis”. 

Collaborating for technological sovereignty

During the event, Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner announced a wide-ranging collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.

The two institutes will initially focus on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in the Internet of Things, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries.

‘Smart everything everywhere’

Over the two days, a record number of guests, including CEOs, CTOs, journalists and special guests and speakers heard and saw examples of Leti’s advanced technology platforms, its commitment to research excellence and its vision for applying innovative technologies to challenges of the digital era.

Max Lemke, head of the Components and Systems Unit at the European Commission, noted that Leti’s contributions extend beyond microelectronics to cyber-physical systems, 5G, the Internet of Things, photonics and post-CMOS technologies. By supporting the digital transformation of industry, Leti plays a leading role in “smart everything everywhere”, Lemke said.

“Leti is excellently positioned to continue doing forward-looking research” on components and systems to build the foundation for Europe’s future competitiveness, and to play an instrumental role in supporting French and European industry in their digital transformation, he said.

By Pete Singer

Semiconductor manufacturers use a variety of high global warming potential (GWP) gases to process wafers and to rapidly clean chemical vapor deposition (CVD) tool chambers. Processes use high GWP fluorinated compounds including perfluorocarbons (e.g., CF4, C2F6 and C3F8), hydrofluorocarbons (CHF3, CH3F and CH2F2), nitrogen trifluoride (NF3) and sulfur hexafluoride (SF6). Semiconductor manufacturing processes also use fluorinated heat transfer fluids and nitrous oxide (N2O).

Of these, the semiconductor industry naturally tends to focus its attention on CF4 since it is one of the worst offenders, with an atmospheric half-life of 50,000 years. “CF4 the hardest to get rid of and it’s one of the worst global warming gases,” said Kate Wilson, VP Marketing, Subfab Solutions – Semiconductor Division of Edwards. “We tend to use that as an indicator of how much of the other global warming gases, as well, are being emitted by the industry. If we’re dealing with that (CF4) well, we tend to be managing the rest of the gases pretty effectively.”

According to the Environmental Protection Agency (EPA), estimating fluorinated GHG emissions from semiconductor manufacture is complicated and has required a significant and coordinated effort by the industry and governments. It was historically assumed that the majority of these chemicals were consumed or transformed in the manufacturing process. It is now known that under normal operating conditions, anywhere between 10 to 80 percent of the fluorinated GHGs pass through the manufacturing tool chambers unreacted and are released into the air.

In addition, fluorinated GHG emissions vary depending on a number of factors, including gas used, type/brand of equipment used, company-specific process parameters, number of fluorinated GHG-using steps in a production process, generation of fluorinated GHG by-product chemicals, and whether appropriate abatement equipment has been installed. Companies’ product types, manufacturing processes and emissions also vary widely across semiconductor fabs.

The good news is that many companies in the semiconductor manufacturing industry have successfully identified, evaluated and implemented a variety of technologies that protect the climate and improved production efficiencies. Solutions have been investigated and successfully implemented in the following key technological areas:

  • Process improvements/source reduction
  • Alternative chemicals
  • Capture and beneficial reuse
  • Destruction technologies (known as abatement)

In 2011 the industry set new targets for 2020, which it summarizes as:

  • The implementation of best practices for new semiconductor fabs. The industry expects that the implementation of best practices will result in a normalized emission rate (NER) in 2020 of 0.22 kgCO2e/cm2, which is a 30 percent NER reduction from the 2010 aggregated baseline.
  • The addition of “Rest of World” fabs (fabs located outside the World Semiconductor Council (WSC) regions that are operated by a company from a WSC association) in reporting of emissions and the implementation of best practices for new fabs.
  • NER based measurement in kilograms of carbon equivalents per area of silicon wafers processed (kgCO2e/cm2), which will be the single WSC goal at the global level.

“We’re finding as we get down to the lower levels and different things come up as the highest priority in the fab where we’re moving into more and more lower usage processes, which are requiring abatement now in order to get those levels down to meet the targets of 2020 in the industry,” Wilson explained.

The main area for potential improvement now is etch, especially in older 200mm fabs where etch processes may not have been fitted with PFC abatement devices. This is particularly true for etch processes making extensive use of CF4. “The area where we still have the most gaps is clearly etch,” Wilson said. In CVD processes, most of the benefit was done by material shifts rather than actual abatement, although we clearly do need to abate the other gases in those processes. For the etch side, there are still quite a few customers that really only do the toxic emission abatement rather than the global warming gas emission abatement. But we do see, across almost all of our customer base, people have either fairly recently moved to fully abating all the PFC type gases or will be shortly.”

Wilson said some other gases have been coming up more recently in terms of things like N2O, which people are putting more focus on now as it’s becoming a larger part of the fab footprint of global warming materials.

For PFC abatement, Edwards offers the Atlas range of products, which destroys PFCs by burning them. This is followed by a wet scrub of the byproducts. This works quite well, but Wilson cautions that in can be tricky for some processes, such as chamber cleans with NF3. “If the burn is not correct and you get too hot, there’s actually the potential to create PFC’s. And so, it is quite critical to have well-controlled burn technology to make sure that you don’t actually cause issues where we didn’t have them before.”

Wilson said another area where they have seen some issues with PFCs being created is with processing of carbon-doped materials, such as low-k dielectrics. “When they do the chamber clean, they’re cleaning off predominately silicon dioxide but there’s carbon in there so that can create PFCs and CF4 as well so there’s a requirement to look at abatement in those areas,” she said.

Another piece of good news is that no company in the supply chain is waiting for legislation to be enacted before they act themselves. “Right from consumers to the consumer manufacturers, the car manufacturers, consumer electric manufacturers, our direct customers, the equipment manufacturers plus the major players within semiconductor and flat panel display, it seems that at every level there’s a commitment that this is the right thing to do,” Wilson said. “At every level people are pushing to get the requirements more stringent and it’s almost not about legislation anymore, it’s about everybody actually thinks it’s a good idea and they want to do it.”

Across all process areas in the fab effective abatement technologies reduce the GHG emissions significantly.  The reductions per process area are shown in the diagram.

Across all process areas in the fab effective abatement technologies reduce the GHG emissions significantly. The reductions per process area are shown in the diagram.

By Ed Korczynski 

Global industry R&D hub IMEC defines the “IMEC 7nm-Node” (I7N) for finFETs to have 56nm Contacted Gate Pitch (CGP) with 40nm Metal Pitch (MP), and such critical mask layers can be patterned with a single exposure of 0.33 N.A. EUVL as provided by the ASML NXE:3400B tool. To reach IMEC 3nm-Node (I3N) patterning targets of ~40 CGP and ~24 MP, either double exposure of 0.33 N.A. EUVL would be needed or else single-exposure of 0.55 N.A. EUVL as promised by the next-generation ASML tool. All variations of EUVL require novel photoresists and anti-reflective coatings (ARC) to be able to achieve the desired patterning.

The Figure shows that IMEC has led tremendous progress on the photoresists, with best resolution in a single 0.33 N.A. EUVL exposure of 13nm half-pitch (HP) line arrays. The most important parameter for the photoresist is the sensitivity target of 20 mJ/cm2, but at that dosage the best materials seen today have unacceptably high line-width roughness of >5nm three-sigma.

“If you’re talking about lines of 16nm width, for 3-sigma you want to be less than 3nm line-width-roughness,” explained Steegen during the 2017 IMEC Technology Forum. “Smoothing techniques are post-develop technologies that basically reduce line-width-roughness. We are working with many partners, and all are making progress in reducing line-width roughness though post-develop techniques.”

Top-down SEM images of the best achieved EUVL resolutions using 0.33 N.A. stepper and Chemically-Amplified Resist (CAR) or metal-oxide Non-Chemically-Amplified Resist (NCAR) formulations, along with post-development “smoothing” technologies to improve the Line-Width Roughness (LWR) to meet target specifications. (Source: IMEC)

Top-down SEM images of the best achieved EUVL resolutions using 0.33 N.A. stepper and Chemically-Amplified Resist (CAR) or metal-oxide Non-Chemically-Amplified Resist (NCAR) formulations, along with post-development “smoothing” technologies to improve the Line-Width Roughness (LWR) to meet target specifications. (Source: IMEC)

The Figure also shows that IMEC has been working with vacuum deposition companies on atomic-layer deposition (ALD) or chemical-vapor deposition (CVD) processes to ideally take off 2 nm of sidewall roughness. Plasma energy may be capacitively- or inductively-coupled to a vacuum chamber to allow for either PEALD or PECVD processing. Such precise atomic-scale processing may be composed of “dep/etch” sequences of one/few atomic layer depositions followed by light plasma etching such that the nominal line-width would not necessarily change. However, this approach necessitates that the wafer leave the lithography track and move to a separate vacuum-tool.

To save on cost and time, LWR smoothing may be accomplished to some extent today in the litho track by specialized spin-on materials. Companies that supply lithography resolution extension (EXT) materials such as spin-on hard masks (SOHM) and anti-reflective coatings (ARC) have looked at ways spin-on materials can improve the LWR of post-developed resist lines. This can be combined with “shrink” materials that add controlled thicknesses to sidewalls of holes, or with “trim” materials that subtract controlled thicknesses from the sidewalls of lines. Generally, some manner of complex chemical engineering is used to create a film that either forms or breaks bonds when thermally driven by a bake step, and after image transfer to underlying SOHM layers the shrink/trim material is typically stripped in a solvent such as propylene glycol methyl ether acetate (PGMEA).

EUVL photoresists may be based on metal-oxide nano-particles, instead of on extensions to the Chemically-Amplified Resist (CAR) formulations that have been mainstays of ArF/ArFi lithography for decades. Inpria Corp.—the 10-year-old-start-up supported by industry—has ultimately developed a tin-oxide family of blends that are shown as the Non-Chemically-Amplified Resist (NCAR) in the Figure. NCAR metal-oxide resists show similar LWR at similar exposure doses to CARs. However, the metal-oxides in the NCAR can often replace SOHM materials, saving cost and complexity in the resist stack.

IMEC’s work on EUVL with ASML steppers leads to the belief that the source power will increase to allow throughput to rise from today’s ~100 wph to ~120 wph by the end of this year. However, those throughputs assume 20mJ/cm2 resist-speed, and masks may require 30 mJ/cm2 target exposures even with post-develop smoothing steps.

[DISCLOSURE: Ed Korczynski is also Sr. Technology Analyst with TECHCET Group, and author of the Critical Materials Report: Photoresists and Extensions and Ancillaries 2017”.]

When it comes to defects and contamination in the semiconductor manufacturing industry, most people tend to think of small, sub-nm defects at the transistor level. As important as those are, there are plenty of things that can go wrong and be seen at the macro level. Scratches, fingerprints, hot spots, spin defects, edge chips, poly haze, missing patterns, etc. are usually visible with the naked eye, perhaps aided by a green light or a microscope.

Fabs often do manual visual inspections, but it tends to be fairly random, only sampling a few wafers at a time. “You put some wafers on the screen, and you look sporadically at five, ten points on a few of the wafers,” notes Reiner Fenske, founder, CEO and president of Microtronic (Hawthorne, NY). “If you find something, typically it’s very difficult to feed that information forward. You might take a picture, but then where does that picture go?” It’s also difficult to compare defects, such as scratches, with previously seen defects. “How many scratches did you have last week? Does that scratch look like the one that you had last night?” Reiner asks.

An automated macro inspection tool – such as the newly released Microtronic EAGLEview 5, which will be running wafers at North Hall Booth #5467 at Semicon West this week — solves those problems, without requiring any recipes and quickly scanning every wafer in the cassette, noting and logging various defects. The EAGLEview 5 represents a big upgrade over the company’s previous offering. “There’s really a dramatic difference in terms of defect detection, defect resolution, defect sensitivity, and there’s no hit to throughput, so we’re still looking at 3,000 wafers a day, which is incredibly fast,” said Mike LaTorraca, Microtronic’s Chief Marketing Officer. Errol Akomer, Applications Director at Microtronic, adds that in addition to the higher resolution, it’s a much cleaner signal. “The signal-to- noise ratio is much better — there’s a 5X improvement in that as well,” he said. Internally developed software algorithms also results in less nuisance defects and increased defect detection.

With these new capabilities, LaTorraca said they’ve created a bridge between micro and macro, and manual and automated. “We can take manual microscope images and put them into the same software that runs on EagleView. We can start to integrate defect information and the actual defect images from the manual microscope world into our tool, and that gives the fab owners a much more unified approach, a better, more comprehensive view, to make better decisions,” he said.

EAGLEview 5 is equipped with advanced imaging technology, analytical software, robotics and a 4-cassette multi-size (100mm-300mm) wafer platform. EAGLEview ProcessGuard Client Software provides defect visualization, digital guard-banding, wafer randomization/slot positional analysis, together with integration with manual microscopes for fab-wide defect tracking and reporting.

Every wafer is automatically OCR read, imaged, 100% inspected and stored for any step throughout the manufacturing process providing a comprehensive, centralized record – or ‘waferbase’ – that is also compatible with the fab’s manual microscope inspection data providing a more integrated, wholistic view of both micro and macro defects.

EAGLEview 5 acts as a hub for defect management across the fab by integrating manual microscope inspection, high resolution EAGLEview wafer images. EAGLEview 5 replaces legacy manual/micro wafer inspection by automating and standardizing wafer inspection processes. Blindly sampling 5 sites on a wafer is no longer needed. The newly developed ProcessGuard microscope interface software records micro defect classifications. This coupled with on-board commonality analysis allows root cause to be determined for micro defects and breathes new life into existing microscope inspection strategies. EAGLEview was originally designed to be comparable to naked eye 1x green light inspection.   EAGLEview 5 shifts the line between a macro green light inspection and microscope inspection.

“You can put all the micro defects into our database in the same ways you did the macro, so you classify your macro defects and you classify all your micro defects,” Fenske explained. “Now you have a record of what, where, how many, and because we collect all the history of where the lot went to, which tools it went through, we can then use that information to do commonality studies to figure out which tool caused the problem. With the microscope, there hasn’t been that type of integration, so we can now take all of those legacy things everyone needs to use and actually give them a new life.”

By Pete Singer

In order to increase device performance, the semiconductor industry has slowly been implementing many new materials. From the 1960s through the 1990s, only a handful of materials were used, most notably silicon, silicon oxide, silicon nitride and aluminum. Soon, by 2020, more than 40 different materials will be in high-volume production, including more “exotic” materials such as hafnium, ruthenium, zirconium, strontium, complex III-Vs (such as InGaAs), cobalt and SiC.

These new materials create a variety of challenges with regard to process integration (understanding material interface issues, adhesion, stress, cross-contamination, etc.). But they also create new challenges when it comes to material handling.

“As we go through technology node advancements, people are looking at the potential of different materials on the wafer,” notes Clint Haris, Senior Vice President and General Manager of the Microcontamination Control Division at Entegris (Billerica, MA). “They’re looking at different chemicals that are required to clean those materials to reduce defects and improve their operational yield, and what we’re increasingly seeing is that fabs are concerned with the fact that contamination can be introduced in the fluid stream anywhere in that long process flow.”

Haris said that part of their mission at Entegris is to make sure that the entire supply chain – from the development of a chemistry at the supplier to its use on a wafer in a fab – is working in harmony, particularly with regard to any materials that might “touch” the chemicals. “Not only do you want to filter and purify things throughout the whole fluid flow,” he said, “but you want to have that last filtration right before the fluid touches the surface of the wafer.”

The goal of filtration is, of course, to remove contaminants and particles before they reach the wafer, but the exact purity required can be a moving target. “Today we’re seeing a lot of these materials and liquids, which have a parts per trillion purity level, but there’s a desire to move to parts per quadrillion,” Haris said. That’s the equivalent of one drop in all the water that flows over Niagra Falls in one day.

In addition to the filtration challenge of achieving that level, there’s the question of do the analytical tools exist to actually measure contaminants at that level. The answer – not yet. “It’s actually a real issue where some of the metrology tools cannot meet our customers’ needs at those levels, and so one of the things that we’ve done is we’ve developed some techniques internally to enhance the capability of metrology,” Haris said. “We also work on how we prepare our samples so you can detect contamination at those levels.” Because that level of detection is so difficult — in some cases impossible – Haris said fabs are increasingly putting additional filters at the process tool and at the dispense nozzle to “protect against the unknown.”

Earlier this year, Entegris introduced Purasol™, a first-of-its-kind solvent purifier that removes a wide variety of metal microcontaminants found in organic solvents used in ultraclean chemical manufacturing processes. Using tailored membrane technology, the purifier can efficiently remove both dissolved and colloidal metal contaminants from a wide variety of ultra-pure, polar and non-polar solvents. “One of the main things that our customers are seeing is a concern with metal contamination in the photo process that can result in particular defects (see Figure), such as bridge defects,” Haris explained. Increasingly, fabs are moving from just filtration (removing particles) to purification (removing ions and metals), he added.

Illustration of metal contamination inducing defects on lithography process.

Illustration of metal contamination inducing defects on lithography process.

Entegris also recently acquired W. L. Gore & Associates’ water and chemical filtration product line for microelectronics applications. “This is a Teflon-based product line, which is used in ultrapure water filtration for semiconductor fabs, but it’s also a product that we’re selling into some of the fine chemical purification markets for some of the chemistries that are brought into the fabs,” Haris said. “We are focused on new product development and M&A to enhance our capability to support our customers as they overcome these contamination challenges..”

By Dave Lammers

Integrating data from various sensors in semiconductor fabs is a key focus in the industry now, and the sub-fab is an increasingly important part of the equation. As process steps become ever more sophisticated and expensive, keeping pumps and other sub-fab equipment running optimally involves integrating multiple pieces of data into useful information.

Paul Rawlings, president of the SEMI Service Division at Edwards, Ltd., said while the semiconductor industry has a history of analyzing tool data and relating it to end processes, more progress is needed in considering the entire fab as an ecosystem.

“The sub-fab equipment also has a bearing, not just in terms of how efficiently we are using data to manage the sub-fab efficiently, but also in terms of improving overall fab performance and yields,” Rawlings said.

Edwards is developing “a structured approach to the kinds of data that we have, and how we use it,” Rawlings said, including a database of best known methods (BKMs) which includes the optimum configurations for pumps, abatements and other systems.

Edwards currently is launching EdCentra, a fault detection and classification (FDC) software platform aimed at the sub-fab. It provides a comprehensive solution to vacuum security, to take one example, by combining equipment monitoring, data acquisition, and analysis of operational data.

EdCentra, Edwards Sub-Fab FDC platform, provides process-critical vacuum and abatement equipment information, complementing Fab-based platforms and supporting industry efforts to create integrated Fab data-management systems.

EdCentra, Edwards Sub-Fab FDC platform, provides process-critical vacuum and abatement equipment information, complementing Fab-based platforms and supporting industry efforts to create integrated Fab data-management systems.

Besides monitoring the performance of the equipment, the EdCentra sub-fab information management system has built-in predictive capabilities. And it complements another Edwards tools, which records service activities.

When a pump is taken back to an Edwards service center, it is stripped down and serviced. “Then we update all of that on to our central database on the lifetime and the performance of our equipment. We have an ecosystem there,” he said.

The company’s overall goal, Rawlings said, is to connect what have been “fairly separate systems,” maximizing up-times in part by comparing the performance of different tools in the same area.

By extending the data analysis ecosystem, Edwards can increase up-times and refine service scheduling. “The data is there. When we connect these systems, that’s where we get all of the benefits from the data. It’s no longer about taking data at individual points along the life cycle. It’s about connecting the data across the journey of the equipment and then looking for optimization, adjustments, and maybe upgrades on the equipment,” he said.

Engineers and data scientists throughout the semiconductor industry are developing more fab-level techniques, using multi-variate analysis of data coming off the tools, as well as other inputs.

For Edwards, that involves looking at data coming from pressure gauges, temperature sensors, the power spectrum, and, increasingly, the very useful information derived from vibration monitoring.

“What we are finding is that by looking at the combinations of data, that’s when things become really interesting. Rather than just relying on one or two points of data on the equipment, we’re starting to build up a library of different parameters. Then we are looking to see how we combine those to give us the most accurate predictions of tool lifetime,” he said.

Edwards is working closely with two fabs to develop data-sharing protocols that allow for optimum monitoring of the sub-fab equipment. “We are looking at it both from their point of view, and ours, discussing different ways of processing the data and the analysis of the performance of the equipment.”

Because of the huge amounts of data involved, Rawlings said “we only transmit data, if you like, that moves. It’s not worth sending data at 10+ Hertz when that particular parameter is not moving. It’s only worth sending that data when a change occurs.”

The work with customers is done within strict limits to ensure data security. “Clearly, you would never want to share any data that could give any indication of what customers do in their fabs and we go to great lengths to safeguard this” he said.

One encouraging sign is that, industry wide, cloud security is becoming more effective, reducing concerns about moving data to the cloud. “The way that end-user data is segregated, the built-in security, is resulting in a little bit more openness in terms of using this data,” Rawlings said.

That said, it is still a difficult area to work with customers. “I won’t mention names, but there are a few folks where we are engaged, so we can move to the next level of validation. I think it’s going to be an area of development over the next few years, as we really focus on the right parameters to measure to predict lifetimes.”

A lot of sub-fab equipment is affected by the processes, more than the basic mechanics of the equipment. It is fairly rare to have a bearing failure on a pump, for example. What is more likely is that the pump will have some process-related issues, such as corrosion or condensate build-up from materials in the fab.

“We spend a lot of time studying the process materials, temperature settings, and those kinds of things to extend equipment lifetimes, but there’s obviously always a limit to what can be achieved. What we are now doing is looking at how the different types of sensors that we have, both already on the equipment, and other ones that we’re developing, can give us the best combination, the best ways of predicting lifetimes. That’s an area that we’ll be working hard on over the next few years for our customers,” Rawlings said.

How low can we go?

July 11, 2017

By Ed Korczynski

In the advanced CMOS technology programs ongoing in the Belgium city of Leuven, imec works to extend the building-blocks of integrated circuits (IC). On the day before the opening of SEMICON West 2017, the invitation-only imec Technology Forum provided an update on the emerging opportunities in semiconductor technology and smart electronics systems. An Steegen, Executive VP Semiconductor Technology & Systems, provided the update on how small we can scale CMOS devices over the next 5-10 years. Taller finFETs will likely be used along with nano-wire FETs (NW-FET) by industry, and researchers see ways to cost-effectively combine both in future optimized System-on-Chips (SoC).

“Existing finFET technology can scale to the 5nm-node,” explained An Steegen at ITF 2017 in Antwerp, Belgium. “However, at the 3nm-node it looks like the nano-wire is comparable in performance to the finFET, but it has an additional advantage in that the nanowire is a better electro-statically controlled device so it enables gate-length scaling more than the finFET. So the contacted gate pitch (CGP) of a nano-wire can scale further than a finFET, because below ~40 nm CGP a finFET loses electro-static control which a nano-wire does not.”

While it is given that a nanowire has better electro-static control compared to a finFET, the basic trade-off is that of reduced drive current. The Figure shows that IMEC sees the possibility of System-Technology Co-Optimization (STCO) of future system-on-chip (SoC) designs using hybrid semiconductor technologies. imec’s basic process flow for NW-FETs starts with forming fins and so could be relatively easily integrated with finFETs for co-integrated hybrid CMOS.

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

“Today, this SoC is processed in one technology which means it’s sub-optimal for certain blocks on the SoC,” explained Steegen. “So imagine a future where you can choose the preferred technology for each block. I would choose finFETs for those blocks that need drive current, while I would choose nano-wire-FETs for those blocks that need more density and lower power. I would for example choose a magnetic RAM to replace my cache memory. I can optimize each sub-block for a preferred technology. Now I can do more, like sprinkle in low-energy devices like tunnel-FETs or spin-devices or 2D-materials as low-energy switches.”

Super-vias and Rutherails

Design-Technology Co-Optimization (DTCO) is imec’s term for new interconnect technologies to allow for simpler or more-compact designs. IDTCO process-scaling boosters are needed to stay with the pace of aggressive design rule targets. “We’re working on super-vias that connect more than one metal to the other and can jump a number of levels, and buried rails to support finFETs in standard-cell libraries,” explained Steegen during ITF2017.

Super-vias could be cobalt plugs that connect more than two metal levels within on-chip multi-level interconnects. The cobalt plugs would be nominally 20nm diameter and 105nm deep, and connected to a dual-damscene upper metal line. Low-k dielectric of k=2.55 uses thin silicon carbon nitride (SiCN) for definition between the damascene levels.

Ruthenium rails (Rutherails) would be buried in a front-end dielectric layer to provide electrical contacts below finFETs for 42nm CGP and 21nm MP needed for imec 3nm-Node (I3N) devices. Ruthenium rails 30nm deep and 10nm wide do not need complex barrier layers and should provide sufficient current flow for either finFETs or NW-FETs.

imec is also working on materials R&D to extend the performance of 3D-NAND. Steegen said,

“At imec we are working on improving the performance of that Flash device by introducing high-mobility channels, also by engineering the dielectric trapping layer with a barrier that can help improve the erase window and also the retention.”

Brewer Science Inc. today announced from SEMICON West the extension of its partnership with Arkema to develop second-generation directed self-assembly (DSA) materials using high-x (chi) block copolymers. These new materials target advanced-node wafer patterning processes, because they enable even smaller feature sizes than first-generation DSA materials. As such, they provide a cost-effective solution to achieving device nodes down to 5nm and beyond, thereby enabling the continuation of Moore’s law.

“There have been very high expectations that DSA would solve all patterning issues,” said Darron Jurajda, Business Unit Manager, Brewer Science Inc. “Like all worthwhile technologies, there are many challenges to be solved before going into production. Leveraging our earlier DSA collaboration with Arkema offers the best path for implementing the next generation of materials. Together, we look forward to unlocking DSA’s full potential in accordance with industry timelines for manufacturing.”

High-chi block copolymers will further extend DSA’s advantages, achieving feature sizes that meet the requirements for 5nm and beyond. Extending their partnership allows these companies to build on their knowledge base, giving them a head start on developing high-chi materials.

As feature sizes shrink more aggressively with each node, it has become cost prohibitive to create them using existing patterning processes, such as EUV, self-aligned double patterning and self-aligned quad patterning. This presents a challenge for foundries and integrated device manufacturers preparing to ramp to 7nm and 5nm processes. DSA provides an alternative solution to achieving fine feature patterning; can be explored for minimal investment; and is cost efficient in final production. Development of high-chi materials also expands the opportunity for implementing DSA in other applications, including photonics, membrane applications and other areas of microelectronics.

The original collaboration between the two companies combined Brewer Science’s know-how in patterning and process integration with Arkema’s leading-edge expertise in block copolymer development to develop polystyrene-polymethyl methacrylate DSA materials, which are now production-ready to manufacture sub-22nm features.