Tag Archives: letter-semi-tech

Tanaka Holdings Co., Ltd. today announced that Electroplating Engineers of Japan, Limited, which operates the Tanaka Precious Metals’ plating business, has developed, and launched from July 15, the RAD-Plater cup-type ultra-compact plating laboratory equipment for semiconductor wafers, which achieves equivalent films to mass-production machines.

The RAD-Plater is ultra-compact laboratory equipment for manufacturing 2 to 8 inch semiconductor wafers. Measuring 800 mm wide and 700 mm deep, it is smaller than mass production machines and can operate on only compressed air and the 100 volt power of general equipment. In addition to gold, silver, palladium, copper and nickel, it can use a wide variety of plating solutions including alloys and lead-free solutions, and at 10 liters or less of solution, it uses about half the plating solution required by dip-type machines, which also reduces experimentation costs. The RAD-Plater uses an EEJA-manufactured Stir Cup and delivers mass-production level plating quality through uniform and bubble-less film thickness and superior filling of deep vias. It also enables reduced plating time by using a high current density achieved with an increased ion supply. Even though the RAD-Plater is laboratory equipment, it achieves a level of plating equivalent to that of mass-production machines, which enables early problem-solving in the development stage for mass production issues such as expected yield, and enables trouble-free rollout to the mass-production line. This is the world’s first cup-type plating laboratory equipment for manufacturing semiconductor wafers, using 10 liters or less of plating solution and handling 8-inch wafers.

Many development divisions of manufacturers with mass-production plating lines would have previously contracted out the plating solution experimentation work to equipment manufacturers and others for evaluation, but purchasing a RAD-Plater and conducting experiments in-house now enables a considerable reduction in development lead times. Other customers would have previously purchased mass-production machines to conduct their own experiments, but because the RAD-Plater comes at a cost that is one third to one quarter that of the mass-production machines, they can now achieve considerable cost reductions. EEJA provides samples of plating solution together with the RAD-Plater to research, development and trial manufacture divisions of manufacturers, universities and other education and research institutes, material manufacturers and others to improve sales of plating equipment and plating solutions for mass production. It aims to achieve RAD-Plater sales of 500 million yen per year by 2017.

RAD plater

RAD plater

Tanaka Precious Metals will be exhibiting at SEMICON West 2015 from July 14th to July 16th at the Moscone Center in San Francisco. Our engineers will be available to answer questions anytime at Booth No. 1628, South Hall.

TÜV Rheinland, a full-service testing, inspection and certification company, exhibiting at the annual SEMICON West expo, announced the expansion of services to include Environmental, Health & Safety testing and certification of Group III-V compounds in semiconductor manufacturing environments. A Nationally Recognized Testing Laboratory (NRTL), TÜV Rheinland will have representatives on hand at the expo to discuss services ranging from mobile EMC testing, Canadian and US certification marks (cTUVus) for the North American market, and safety assessments based on SEMI standards.

“Over the years, SEMICON has become our best opportunity to meet with current and potential clients, and to truly absorb the latest developments in the semiconductor industry. This space changes so quickly, and new discoveries can alter manufacturing and safety requirements. We participate each year to be able to provide our clients with the absolute latest in safety and compliance certification services,” said Jonathan Kotrba, Business Field Director, Commercial of TÜV Rheinland.

Assessing hazardous compounds in semiconductor manufacturing

Because silicon transistor scaling appears to be reaching its limits under current technology, attention is turning to the group III–V compound family of materials to fabricate semiconductors. Group III-V compound semiconductor wafers are compounds formed by elements from columns III and V of the periodic table. Examples include Gallium arsenide (GaAs) wafers, Aluminum arsenide (AlAs), Indium arsenide (InAs), and Indium Gallium Arsenide (InGaAs), among others.

When arsenic, phosphide, and the other group III-V materials are bound or embedded in the solid wafer, they do not pose an inhalation risk. However, if evaporated during processing, like wafer heating, etch, or laser ablation, arsine gas or arsenic compounds may be driven off the wafer and are more likely to affect people. Arsenic containing compounds may deposit on unprotected clothes or cleanroom garments, and if not properly segregated, migrate within the facility and even be brought home on employees’ clothes.

TÜV Rheinland can test to SEMI S2 and S8 standards to assess potential health risks accompanying semiconductor manufacturing, and can certify an OEM in compliance with national standards, or can develop an action plan to help bring a facility up to standard so there are no certification barriers to market.

In-Situ EMC testing: Compliance solutions, delivered

There are situations when heavy equipment cannot be moved to an offsite lab even with our state-of-the-art Electromagnetic Compatibility (EMC) testing facilities conveniently located throughout North America.  For these clients, TÜV Rheinland maintains a fleet of dedicated mobile labs with specialized equipment to test at a client’s location. All test equipment is brought to the customer in climate-controlled box trucks owned by TÜV Rheinland, never a third-party shipping or trucking firm. In most instances, on-site testing takes no more than three days, from arrival to departure.

The right mark for the North American market

The US and Canadian governments have clearly defined regulations which products—especially electronics equipment—must satisfy before they can be approved for sale. TÜV Rheinland of North America is accredited as a NRTL by OSHA (The Occupational Safety and Health Administration) in the United States, and by SCC (Standards Council of Canada) in Canada.

The cTUVus certification mark issued by TÜV Rheinland tells both consumers and business partners that an OEM’s products have been thoroughly tested and specifically certified to comply with the electrical and fire safety regulations. With a single cTUVus mark, customers can demonstrate compliance for both the US and Canadian markets.

Inside every new smartphone, tablet or other digital gizmo are microchips with more circuits — and more processing power — than manufacturers could make a year or two before.

And behind each advance in microchips are innovations, such as one emerging next week from a Twin Cities firm, that consumers never think about or see.

Subodh Kulkarni, chief executive of Golden Valley-based CyberOptics, displayed a new sensor that measures humidity in chip-making.

Subodh Kulkarni, chief executive of Golden Valley-based CyberOptics, displayed a new sensor that measures humidity in chip-making.

At SEMICON West 2015, Golden Valley-based CyberOptics Corp. will unveil a sensor product that lets chipmakers measure the vibration, leveling and humidity inside the machines turning plain silicon wafers into chips. It’s an advance from a previous product that combined two measurements.

For chipmakers, that means slightly less time in a production run needs to be spent taking measurements, and more time can be devoted to making chips. It’s a jump in efficiency that is one of the reasons that digital gadgets keep getting better and cheaper.

For CyberOptics, it’s an addition to a lineup of semiconductor sensors that is the fastest-growing product segment in the company, which has about $45 million in annual sales. “What we are good at is taking different types of sensors and putting them together,” said Subodh Kulkarni, the company’s chief executive.

CyberOptics was started in the 1980s by a University of Minnesota electrical engineering professor named Steven Case, who recognized the role that laser-based sensors could play in lining up circuit boards. Its products were originally used by makers of computers and other electronics items for the assembly of circuits onto boards. It still makes those kinds of sensors, which have advanced to where they measure in 3-D and at eye-blinking speeds.

The company moved into the chip manufacturing industry in 2004 when it first combined a miniature sensor with a Bluetooth wireless transmitter and placed it on a substrate the size of a silicon wafer. That sensor device could then be run through a chipmaking machine to measure its accuracy and performance, sending data wirelessly in real time.

Since chipmakers need to check several attributes, such as whether wafers are being kept level or whether there is dust or other particles in the machine, they needed to run separate sensors through, consuming time that would otherwise be used for actual production.

The company’s new product adds humidity sensors into the multi-sensor package. Keeping track of humidity inside the machines that make chips has become more important as the distance between circuits has shrunk, the innovation that allows more circuits to be put on a chip.

Ever smaller chips

Just this week, IBM announced a breakthrough in making computer chips even smaller, creating a test version of the world’s first semiconductor that shrinks the circuitry to a separation of 7 nanometers. By contrast, today’s fastest computers and servers use microprocessors with circuits of 14- and 22-nanometers. The width of a human hair is about 10,000 times bigger. A strand of human DNA is 2.5 nanometers.

At such tiny widths, moisture inside the machine that is making a chip can create oxidation that renders the silicon wafer useless. While the IBM innovation is several years from becoming a commercial process, each step toward smaller circuits means that the machines and processes to make them need to be better.

“This is all good for us because, when transistors were hundreds of nanometers, you didn’t need to measure things that precisely,” Kulkarni said. “But as the chips get more sophisticated, the manufacturers can no longer afford to use the existing crude tools to do measurements and sensing.”

CyberOptics sold about $8 million worth of advanced sensors for chipmaking last year. It doesn’t break out profitability of such products but, in a filing to securities regulators, it said that its newest products, including semiconductor sensors, “have more favorable margins compared to products we have sold in the past.”

Semiconductor equipment manufacturer ClassOne Technology today announced a configuration for optimizing Through Silicon Via (TSV) and Through Wafer Via (TWV) processes on its affordable Solstice electroplating systems. The Solstice family, introduced last year, is designed to provide advanced yet cost-efficient plating for MEMS, Sensors, RF, Interposers and other emerging technologies for ≤200mm wafers.  Flexibly configurable, the Solstice for TSV/TWV combines chambers for the critical blind via pre-wet operation with advanced copper plating on the robust and reliable automation frame that is the heart of the Solstice.

“In recent months customer requests have skyrocketed for TWV, whether alone or in combination with forming redistribution layers (RDL),” said Kevin Witt, ClassOne’s Chief Technology Officer. “Many of our smaller-wafer customers seek the advantages of 2.5 and 3D packaging needed for their next generation products; and cost-effective TSV or TWV processing is mission critical. The new Solstice configuration addresses their needs effectively and elegantly with a plating tool that is affordably priced for 200mm and smaller substrates.”

Witt explained that the new Solstice TSV configuration, which has already been sold to customers, employs a unique, high-efficiency but simple vacuum pre-wet chamber followed by copper via electroplating. This combination of capabilities enables the ClassOne tool to routinely produce fully-filled or lined vias with widths ranging from 5 to 250 micron having aspect ratios as high as 9:1. Traditionally, this level of performance has been challenging even for plating systems costing twice as much as Solstice. The Solstice can also be configured to perform additional downstream processing such as resist strip and seed layer etch making it a cluster tool that delivers a suite of critical processes, reducing cycle time and saving money. This technology makes it possible to process TSV alone or TSV and redistribution layers simultaneously to provide a complete solution on a single tool.

“New customers always have the same reaction when they first see our Solstice platers in action,” said Byron Exarcos, President of ClassOne. “They’re always amazed that tools this affordable deliver such advanced processing. The new Solstice TSV configuration is one more example of what is making Solstice the preferred solution for electroplating on smaller wafers!”

Designed for high-performance, cost-efficient ≤200mm electroplating, Solstice systems are priced at less than half of what similarly configured plating tools from the larger manufacturers would cost — which is why Solstice has been described as delivering “Advanced Plating for the Rest of Us.” Solstice can electroplate many different metals and alloys in a spectrum of processes, on transparent or opaque substrates. ClassOne now offers three Solstice models: the LT for plating process development, the S4 for mid-volume production, and the S8 for high-volume, cassette-to-cassette production, with throughput of up to 75 wph.

Solstice S8 Plating System

Rudolph Technologies, Inc. and DISCO Corporation of Tokyo, Japan, announced a collaborative partnership to deliver leading-edge hardware and software solutions to optimize the wafer saw unit processes. These comprehensive solutions will enable their customers to consistently improve the quality and productivity of their advanced packaging products. The complete wafer saw solution includes: DISCO’s fully automatic dicing saw for high-throughput, dual-cut processing, DISCO’s ablation laser saw and stealth dicing saw, Rudolph’s NSX inspection system for post-saw inspection, Rudolph’s new Equipment Sentinel fault detection and classification (FDC) software for real time monitoring and feedback of DISCO’s dicing tools, and Rudolph’s Discover Enterprise yield management software for sophisticated wafer-to-process tool correlations.

The evolution of semiconductor device materials for advanced packaging has resulted in more stringent dicing process requirements. Process deviations and excursions during die singulation can result in chips and cracks that impact the long-term reliability of devices. The agreement between DISCO and Rudolph, which took effect June 1, 2015, will drive a new level of innovation in saw processing, including improved kerf control, chipping minimization and overall cost-of-ownership enhancement resulting in solutions that will accelerate advanced packaging adoption.

“With the increasing use of complex materials in today’s semiconductor devices, dicing is an increasingly critical process step. DISCO is committed to providing the highest quality wafer saw solutions to address our customers’ most demanding challenges. We continue to invest in our industry-leading wafer dicing equipment, leveraging advanced sensors and data acquisition technologies to provide even greater insight into the performance of our equipment,” explains Noboru Yoshinaga, executive operating officer, general manager, sales division at DISCO. “Through our collaboration with Rudolph we are able to turn data into valuable knowledge for our customers, making DISCO tools easier to ramp, monitor and control.”

“For the past year, our collaboration with DISCO has allowed us to understand and address the increasing challenges faced by our mutual customers resulting in a close partnership capable of providing comprehensive solutions to improve device reliability and data reporting, while at the same time lowering their costs and decreasing ramp times,” states Mike Plisinski, Rudolph’s executive vice president and chief operating officer. “Demand for turnkey solutions is increasing and we are committed to continuing to develop and build on this success to meet that growing demand.”

According to Thomas Sonderman, vice president and general manager of Rudolph’s Software Business Unit, “Our new, automated FDC software, Equipment Sentinel, offers advanced packaging manufacturers significant benefits that, to date, have not been fully exploited by the industry. For example, the bi-directional correlation of equipment sensor data with diced product data gives users a comprehensive, easy-to-understand view of their process, allowing them to use predictive analytics to take immediate action, thus reducing product jeopardy and improving the overall effectiveness of their manufacturing operations. The savings that result from avoiding a single failure at a critical process step can easily justify the return on investment for this type of process control solution.”

Equipment Sentinel, which was announced today, combines key wafer-level data with high-fidelity tool signal and event data into a single framework, giving users a comprehensive, easy-to-understand view of their processes and equipment. Currently installed at multiple beta sites worldwide, fab personnel will use Equipment Sentinel software to extract the maximum value from the voluminous amounts of data generated in today’s semiconductor operations.

“Many applications have been developed over the years to address advanced tool monitoring and control for semiconductor manufacturing, but they are typically focused on either wafer or equipment state information, not both,” said Sonderman. “Equipment Sentinel integrates these formerly independent data streams into a powerful monitoring and control engine to enable timely actionable intelligence, greatly enhancing optimization capabilities with predictive analytics in the fab.”

Rudolph’s new Equipment Sentinel software can efficiently identify and isolate the cause of abnormal operating conditions and implement corrective actions to reduce product jeopardy and increase overall equipment effectiveness.

“The ability to quickly detect, isolate and correct actual tool excursions provides unparalleled value to a manufacturing operation. In many cases, the detection of a single critical incident more than offsets the total cost of this type of system,” added Sonderman. “Equipment Sentinel is capable of acquiring, processing and analyzing the massive amounts of data generated in today’s high-tech manufacturing environments, providing a new avenue for corrective actions to ensure the maximum return on investment for semiconductor manufacturers.”

Stop by the Rudolph booth #5580 for more information.

Nano-electronics research center imec announced today at SEMICON West that it has demonstrated concept and feasibility for pore-sealing low-k dielectrics in advanced interconnects. The method, based on the self-assembly of an organic monolayer, paves the way to scaling interconnects beyond N5.

The need for ultra-porous low-k materials as interconnect dielectrics to meet the requirements dictated by the ITRS (International Technology Roadmap for Semiconductors) poses several challenges for successful IC integration. One of the most critical issues is the indiffusion of moisture, ALD/CVD metal barrier precursors and Cu atoms into the porous low-k materials during processing (low-k pore diameter larger than 3nm, up to 40% porosity). This leads to a dramatic increase of the material dielectric constant and leakage current, and to the reduction of the voltage for dielectric breakdown.

Imec has developed a method to seal the pores of the low-k material with a monomolecular organic film. The method not only prevents diffusion of moisture and metal precursors into the low-k material, it also might provide an effective barrier to confine copper within the copper wires and prevent copper diffusion into the low-k material.

Self-assembled monolayers (SAMs) derived from silane precursors, are deposited from vapor phase on 300mm wafers into low-k during chemical vapor or atomic layer deposition and subsequent Cu metallization. The dielectric constant (k) of the resulting sealing layer is 3.5 and a thickness lower than 1.5nm was achieved. This is key to limit the RC delay increase enabling beyond 5nm technology nodes. As a result, a ca. 30% capacitance reduction was observed after SAM pore-sealing was applied. Moreover, a clear positive impact on the low-k breakdown voltage is observed upon sealing.

imec

Imec’s research into advanced interconnects includes key partners as GLOBALFOUNDRIES, Intel, Micron, Panasonic, Samsung, SK Hynix, Sony, and TSMC.

By Jeff Dorsch, Contributing Editor

The short answer to that headline’s question is “no.” Longer term, in going beyond the 5-nanometer process node, silicon may finally reach the end of its usefulness to the semiconductor industry.

SEMI estimates the worldwide semiconductor materials market grew 3 percent in 2014 to $44.3 billion, compared with 2013’s $43.05 billion. The 2014 total was composed of $24.0 billion in wafer fabrication materials and $20.4 billion in packaging materials. Taiwan last year remained the world’s largest consumer of semiconductor materials, accounting for $9.58 billion in sales, an 8 percent increase from the prior year’s $8.91 billion.

SEMI’s Silicon Manufacturers Group reports silicon wafer area shipments increased 11 percent in 2014 to 10,098 million square inches, as against 9,067 MSI in 2013. Revenues, however, grew only 1 percent year-to-year, to $7.6 billion from $7.5 billion, still far below the 2007 peak of $12.1 billion.

Researchers around the world are constantly investigating materials that could be the successor to silicon. Molybdenum disulfide shows promise. Graphene, the “wonder material” with many exciting attributes, is difficult to employ as a semiconductor material due to its lack of a bandgap, although bandgaps can be found in bilayer graphene or graphene nanoribbons.

Closer at hand are silicon carbide and the III-V materials, such as gallium arsenide and gallium nitride.

Scott Balaguer, Edwards’ president of the U.S. & Europe Semiconductor Business Unit, observes, “Chemistries, gas flows and materials are constantly changing across numerous applications and design nodes. We see these innovations in both silicon and compound semiconductor technologies. A great example is the new prototype SiC line at SUNY Polytechnic Institute that General Electric is driving in Albany, New York.

“The rate and pace of 10nm development is picking up and 14nm HVM fabs continue to improve and efficiencies and achieve higher yields.

“Clearly the rate of EUV adoption has gained momentum as source performance and throughput has improved. It is not a question of if, it is just when,” Balaguer says.

Thomas Piliszczuk, senior vice president of marketing, business development, and global sales for Soitec, says radio-frequency silicon-on-insulator technology is becoming mainstream and has seen “huge growth over the past several years.” He adds, “SOI is today in 99 percent of smartphones.”

On the fully-depleted silicon-on-insulator front, the industry today is at a tipping point with strong industry support and a growing ecosystem. The low-power, significant performance, and cost benefit attributes of FD-SOI are making the technology attractive for mobile, wearable devices, and the Internet of Things, as well as automotive and networking applications, according to Piliszczuk. “FD-SOI is a cheaper solution, overall,” he says. The executive looks for it to soon become “a very high-volume market.”

“The ecosystem now sees SOI not as a niche any more, but as a robust technology for many consumer applications,” Piliszczuk concludes. Shin-Etsu Handotai and SunEdison Semiconductor have joined Soitec as SOI wafer suppliers.

EUV and immersion lithography are expected to usher in the 7nm and 5nm process nodes. What happens past N7 and N5?

An Steegen, senior vice president of process technology for imec, looks ahead to nanowires and high-mobility channels in semiconductors of the future. Those nanowires will be made of silicon or silicon germanium, she says, with germanium in the channel.

That technology will have its drawbacks, she acknowledges. “One nanowire will never beat the performance of one FinFET,” Steegen says.

IBM Research has touted the future use of carbon nanotubes in transistors.

So, don’t write off silicon for now. The old reliable material may have years of usefulness ahead, whether in compound semiconductors or on its own.

CEA-Leti today announced its first results towards the demonstration of CoolCube’s feasibility in FinFET technology on its 300mm production line, and new CoolCube circuit designs that improve the trade off between area, speed and power.

Key process steps developed on 300mm wafers show progress in closing the gap between the demonstration of a single device and taking the technology to fabrication.

CoolCube is Leti’s sequential integration technology that enables the stacking of active layers of transistors in the third dimension. Under development for eight years, it aims at fully benefiting from the third dimension, and is enabled by cutting in half the thermal budget in manufacturing transistors, while maintaining their performance.

Mobile devices, where minimal power consumption is key, are the primary market for chips manufactured with the technology. CoolCube also allows designers to include backside imagers in the chips, and co-integration of NEMS in a CMOS fabrication process also is possible.

“CoolCube enables local via density that is 10,000 times higher than ‘standard’ 3D integration, because the technology is designed to connect stacked active layers at a nanometric scale,” said Maud Vinet, Leti’s advanced CMOS laboratory manager. “In the digital area, we expect this 3D technique to allow a gain of 50 percent in area and 30 percent in speed compared to the same technology generation in classic 2D – gains comparable to those expected in the next generation. In heterogeneous integration, we expect CoolCubeTM to be an actual enabler of smart-sensor arrays by allowing a close integration of sensors, detection electronics and digital signal processing.”

Leti’s team will be in the European Pavilion, South Hall, Booth #2317, during SEMICON West.

Leti feature 1

Leti’s CoolCube is made possible by sequential integration.

By Jeff Dorsch

Chemical mechanical planarization (CMP) technology has been around for a long time. In addition to the semiconductor industry, CMP has applications in data storage, polishing the rigid disks and magnetic heads of hard-disk drives.

Those interested in learning about developments in CMP for hard drives and integrated circuits would do well to attend the CMP Technical and Market Trends session on Thursday, July 16, at 11 a.m. in the TechXPOT North area of Moscone Center’s North Hall. Representatives of Intel, HGST, Entegris, TDK, and other companies will be speaking.

While 450-millimeter wafers haven’t been much in the news this year, Thursday’s session will include a presentation by the Global 450 Consortium, with speakers from the College of Nanoscale Science + Engineering (CNSE) and SEMATECH.

CNSE is part of the SUNY Polytechnic Institute in Albany, N.Y., which also contains the Chemical Mechanical Planarization Center, a joint program with SEMATECH. Mitsubishi Chemical joined the program this spring.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

CMP includes consumable products, polishing pads and slurries. Dow Chemical is the leading vendor in polishing pads, while Cabot Microelectronics dominates the CMP slurry market.

Late last month, Applied Materials and Cadence Design Systems announced that they are collaborating on optimizing the CMP process through silicon characterization and modeling for ICs with 14-nanometer features, and beyond that process node. Cadence, one of the leading vendors of electronic design automation software and services, will provide its CMP Predictor and CMP Process Optimizer tools. Applied will employ its Reflexion LK Prime CMP system.

“From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster,” Derek Witty, vice president and general manager of Applied’s CMP Products Group, said in a statement.

Whatever your level of expertise in CMP, SEMICON West 2015 will help you polish up your knowledge of the field.

By Debra Vogler, SEMI

If you attended just about any mask making conference in the last five to seven years, you would have heard the lament about exploding data volumes and their impact on mask writing time and, by extension, mask costs. The industry is still concerned with data volumes, whether 193nm immersion or EUVL. “Data volume is significantly increased node by node and requires a faster data transfer rate,” Jongwook Kye, director of the Strategic Lithography Technology Group at GLOBALFOUNDRIES, told SEMI. “We have to support data transfer across multiple continents, and that is a bottleneck.”

So it’s not just that masks are getting more complicated – with large data volumes – but it’s how the data gets transferred from one continent to the other that is becoming more challenging. “Even if you improved the mask writing time, with a multiple e-beam mask writing tool, the problem is still the data transfer rate.” On the subject of multiple e-beam writing tools, Kye noted that they aren’t currently available, and investment in the technology has not been aggressive, so the challenges remain even as the industry goes from node 10 down to node 5. Kye will present at SEMICON West 2015 (July 14-16) in the July 15 Lithography session during the Semiconductor Technology Symposium.

Kye pointed to another sector – the Internet of Things (IoT) – as having the potential to unlock solutions for the data volume/data transfer rate conundrum. “The IoT folks want to solve the data collection problem that arises from having trillions of sensors,” said Kye. “Once the infrastructure is there [to collect sensor data], those solutions can be transferred in some manner to fit the data transfer needs of the mask writing industry.”

One key factor that has changed over the years is that now, edge placement error (EPE) is the most important parameter of concern for lithography, noted Kye (Figure 1). “In traditional lithography, we tried to control overlay (OL) and CDU (critical dimension uniformity),” said Kye. “These days, the OL and CDU are no longer independent parameters, so we unify them together in one word and call it edge placement error.”

Christopher Progler, VP and CTO at Photronics, Inc., told SEMI that, today, EUV masks are being produced that are suitable for wafer technology development and production in limited applications. One relatively new development – pellicles for EUV masks – has taken a major step forward. “The ecosystem is rapidly responding to this new requirement,” noted Progler. “Despite this progress, however, EUV represents a very different mask technology overall when compared to even the most advanced 193nm masks. This presents the industry with new challenges and learning cycles on the path to delivering high yielding production EUV masks.” All in all, however, Progler observed that EUV mask infrastructure continues to advance with progress in a number of critical areas including blank defects, patterning modules, cleaning and validation.

“EUV mask defects will be handled using essentially a multi-sensor approach of inspection and characterization methods knitted together to form sound decisions on an EUV mask for use in particular applications,” Progler told SEMI. He anticipates that eventually, a high-speed, full-field actinic mask inspection tool will be delivered. “Such capability can be enabling for broad adoption of EUV masks, and therefore, EUV lithography.” Progler, however, believes that parallel plans are needed, “One that optimizes and calibrates the multi-sensor approach, and also the collaborative development of the full-field actinic inspection system.”

Addressing the need for greater speed over and above those of single-beam writing tools, Progler told SEMI, “There are a number of mask writer programs underway that would employ a writing engine instead comprised of an array of beams, thereby enabling faster writing time and improved flexibility for real-time pattern correction.” He noted that Photronics has been engaged in an equipment development program at IMS nanoFabrication alongside other industry partners to bring about this type of technology solution.

Rounding out the industry’s “to-do” list for EUVL, the mask industry also faces a challenge in the area of “so-called mask matching.” “Mask matching comprises methods to ensure two masks really are functionally identical for the given use,” Progler told SEMI. “So, driving integrated inspection/metrology/characterization solutions that ensure two masks work equivalently in a given application will continue to evolve.”

In addition to Kye (GLOBALFOUNDRIES) and Progler (Photronics), presenters from Nikon Research, ASML, Canon Nanotechnologies, Sematech and CEA Leti will be featured at the “Making Sense of the Lithography Landscape” (a Semiconductor Technology Symposium session) at SEMICON West 2015, which will be held July 14-16 at Moscone Center in San Francisco, Calif.