Tag Archives: letter-wafer-business

ProPlus Design Solutions Inc. and MPI Corporation today announced a strategic partnership agreement and immediate availability of a characterization and modeling solution that integrates ProPlus’ SPICE modeling and noise characterization solution with MPI’s advanced probing technologies.

The integrated solution offers seamless support of the MPI probe stations to perform automated measurement of DC, CV and noise characteristics, enabling MPI users easy access to the most accurate ProPlus SPICE modeling and noise characterization offerings. The advanced probing technologies developed by MPI are optimized for the latest ProPlus 9812DX noise analyzer with improved grounding and shielding technologies critical to wafer-level noise characterization.

Under the partnership agreement, ProPlus users are able to integrate MPI’s advanced semi-automatic probe stations in their characterization and modeling flow for better noise measurement quality. The close collaboration also proved that probe card wafer-level noise characterization is possible using the 9812DX noise analyzer. Previously, these measurements were performed using manipulators and easily introducing RF interferences and oscillations. The advanced probe card technology specially developed for noise measurement provides better data quality and stability, as well as improves flexibility of wafer-level noise characterization for higher throughput.

“ProPlus Design Solutions continues to invest on improving the technologies that made wafer-level noise characterization possible 20 years ago,” remarks Dr. Zhihong Liu, chairman and chief executive officer of ProPlus Design Solutions. “We brought it to the next level with a specially designed probe card for a tightly integrated noise system thus delivering the fastest and most accurate noise characterization of the highest quality. We’re pleased to work with MPI on this effort.”

“The collaboration with ProPlus Design Solutions has enabled a seamlessly integrated wafer level low-frequency noise measurement capability with guaranteed system configuration and performance,” says Dr. Stojan Kanev, general manager of Advanced Semiconductor Test Division at MPI Corporation. “We now offer the most advanced high throughput noise characterization and modeling system. MPI’s exceptional shielding technology provides world class 1/f noise measurement capability. Customers may now rest assured these systems are validated to provide reliable and accurate noise measurement capability while enjoying a reduced cost of test.”

The integrated solution has been adopted by leading semiconductor companies. ProPlus and MPI Corporation will demonstrate the joint solution globally throughout 2018.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced it has received an order from the University of Tokyo for its EVG810LT plasma activation system for compound semiconductor research. Installed at the university’s Takagi & Takenaka Laboratory, the EVG810LT augments the laboratory’s research focused on developing novel MOSFET and electronic-photonic integrated circuits (EPICs) using III-V-on-insulator (III-V-OI) and germanium-on-insulator (GeOI) substrates. These advanced material substrates are designed to exceed the performance of conventional silicon semiconductors as well as silicon photonics, where III-V materials such as indium phosphide (InP), indium gallium arsenide (InGaAs) and germanium are bonded to silicon wafers. The EVG810LT activates a wafer surface using plasma for low-temperature direct wafer bonding, and has been utilized by other customers in high-volume manufacturing of silicon-on-insulator (SOI) wafers and backside illuminated CMOS image sensors.

“The miniaturization of semiconductor devices is reaching its physical limitations, and shrinking transistor (scaling) in line with Moore’s Law is not sufficient enough to address future demands for higher performance of LSI devices,” noted Dr. Mitsuru Takenaka, associate professor at the Takagi & Takenaka Laboratory with the University of Tokyo. “3D integrated circuits with III-V compound semiconductors or germanium stacked freely on silicon semiconductors are expected to be among the breakthroughs to enhance the performance of the LSIs after the end of Moore’s Law. In support of our efforts, we adopted EV Group’s plasma activation system, the EVG810LT, to help us achieve lower temperature and high-quality wafer bonds.”

Commenting on today’s announcement, Hiroshi Yamamoto, representative director of
EV Group Japan K.K., said, “It is a great honor that our system was selected to support the University of Tokyo’s leading-edge LSI device research. The innovative results at The Takagi & Takenaka Laboratory are expected to address the fundamental issues that the semiconductor industry currently faces. Based on our company’s Triple-i philosophy of ‘invent, innovate and implement’, EV Group has been working with universities and R&D facilities that are active in advanced fields. We will continue to provide the Takagi & Takenaka Laboratory with the technical support they need to succeed with their leading-edge research.”

The emergence of the Internet of Things (IoT), Big Data and artificial intelligence (AI) is fueling a new wave of demand for electronic devices with lower power consumption, higher performance, and greater functionality. To meet this demand, the semiconductor industry is evaluating the benefits of incorporating new materials with silicon-beyond pure silicon-based wafers. This shift is paving the way for future market growth of compound semiconductors, as well as more efficient manufacturing technologies to achieve maximum end-device performance. For example, metal-organic chemical vapor deposition (MOCVD) processes, where a thin film of II-VI or III-V material is deposited on a substrate by heteroepitaxial growth, can result in inconsistent wafer formation. This compromises the integrity of the wafer surface and ultimately impacts end-device performance. Direct wafer bonding with plasma activation is a promising solution to enable heterogeneous integration of different materials and to realize high-quality engineered substrates.

EVG will showcase the EVG810LT system at the SEMICON Japan exhibition being held December 13-15 at the Tokyo Bit Sight – Tokyo International Exhibition Center in Tokyo, Japan.

CVD Equipment Corporation (NASDAQ: CVV), a provider of chemical vapor deposition systems and materials announced today that it has completed the purchase of the Company’s planned additional facility, located at 555 North Research Place, Central Islip, NY. This new facility will be the primary manufacturing center for the Company’s wholly owned subsidiary, CVD Materials Corporation.

Leonard A. Rosenbaum, President and Chief Executive Officer stated, “With the completion of this purchase we now have the manufacturing space to accelerate our capabilities of providing materials, coatings, and surface treatments to meet our customers’ needs. We look forward to the expansion of our carbon composites and electronic material, Tantaline®, and newly acquired MesoScribe™, product lines. We also anticipate future growth, both organically and by possible future acquisitions. With the purchase behind us, we are now focusing on bringing the new facility on-line and for additional growth opportunities enabled by this additional 180,000 square foot facility.”

CVD Equipment Corporation designs, develops, and manufactures a broad range of chemical vapor deposition, gas control, and other equipment and process solutions used to develop and manufacture materials and coatings for research and industrial applications.

BY ANDREW CHAMBERS, Senior Product Manager, Edwards Ltd.

With the prospects of large 450mm wafers going nowhere, IC manufacturers are increasing efforts to maximize fabrication plants using 300mm and 200mm diameter silicon substrates. The number of 300mm wafer production-class fabs in operation worldwide is expected to increase each year between now and 2021 to reach 123 compared to 98 in 2016, according to the forecast in IC Insights’ Global Wafer Capacity 2017-2021 report.

Significant opportunities to improve safety, reliability and yield still remain in our industry, many of them to be found in the sub-fab, where the critical systems that supply vacuum and treat exhaust gases are to be found—out of sight and, too often, out of mind. Properly handling and removing noxious components in the exhaust flow clearly impacts the safety of fab personnel and the quality of the local environment. As for reliability, when the sub-fab fails the process is down. And yield—the yield of many tools depends directly on steady, high-quality vacuum. “Smart” management of sub-fab systems can improve safety, reliability, yield, and energy efficiency, all of which contribute directly to the bottom line.

For example, consider high-flow CVD processes, which are finding increasing application in high-volume production of 3D-NAND, DRAM and other devices. The process precursors and their decomposition products can present a flammability risk and, unless properly controlled, can condense as hazardous materials in process exhausts. Such condensation can cause a variety of operational problems, including process shut-downs when pipes become blocked, exhaust pipe fires when fluorine reacts with residual silicon compounds, and HF vapour releases when pipes are exposed to atmosphere during cleaning.

Several approaches may be used to address these concerns, alone or in combination. The entire exhaust assembly may be heated to maintain a thermal profile that eliminates conden- sation, though eliminating all cold spots can pose practical difficulties and constant monitoring is required. Exhaust gases may be diluted to mitigate flammability risks, but the cost of the additional diluting gas (N2) becomes prohibitive at high flows. The total cost of ownership for high dilution flows must
also include increased capital investment, operating cost and sub-fab space require- ments for additional abatement capacity.

A smart dilution strategy would continuously adjust the flow of dilution gas based on information from the process tool. Is flammable gas flowing? Is oxidant gas present? If the process gas is non-flammable, can dilution be eliminated entirely? When only a flammable gas is flowing, how much can dilution be relaxed while still maintaining the mixture below the lower flammability limit; or can it be allowed to exceed the LFL, since there is no concurrently flowing oxidant? When flammable gases flow concurrently with oxidizing gases, what dilution is required to keep the concentration of flammable gas below its LFL, with a sufficient safety margin to allow for fault scenarios? What is the best dilution for cleaning gases to optimize the safety and efficiency in their abatement? Answers to these questions and more can be found by analyzing information from the process tool and can be used in a smart dilution strategy to ensure safety, and maximize reliability and yield while minimizing cost.

Information from the process tool can also be used to control the operation of the abatement system. When only flammable gas is flowing with low or moderate dilution, the abatement system can be operated in a “low fire” mode, minimizing consumption of fuel, city water and process cooling water. When flammable and oxidizing gases flow concurrently and high dilution flow is used, the abatement can be switched into a “high fire” mode to ensure full destruction of the process chemicals.

Coupled with smart operation, smart system design can further improve safety, reliability and cost. Consider the problem of gas leaks. Leaks from process exhaust pipes can lead to fires, equipment damage and harm to sub-fab personnel. Local gas leak detectors can protect personnel but risk process shut-down and product loss. Rigorous leak checking proce- dures can reduce the risk of leaks following maintenance, but cannot prevent progressive seal degradation or leaks that occur during normal operation. A smart design integrates pumps, abatement and all connecting piping in a single unit, engineered for performance and safety and thoroughly tested at all stages of manufacturing and installation. Integration also permits exhaust integrity checking, double-containment, accurate and consistent exhaust temperature control, and tool-connected “smart” operation and provides single-vendor responsibility for maintenance and performance.

Opportunities for improvements abound, but taking advantage of them requires a smart approach based on broad experience and thorough understanding of semiconductor manufacturing processes.

SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that worldwide semiconductor manufacturing equipment billings reached US$14.3 billion for the third quarter of 2017.

Quarterly billings of US$14.3 billion set an all-time record for quarterly billings, exceeding the record level set in the second quarter of this year. Billings for the most recent quarter are 2 percent higher than the second quarter of 2017 and 30 percent higher than the same quarter a year ago. Sequential regional growth was mixed for the most recent quarter with the strongest growth in Europe. Korea maintained the largest market for semiconductor equipment for the year, followed by Taiwan and China. The data are gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 95 global equipment companies that provide data on a monthly basis.

Quarterly Billings Data by Region in Billions of U.S. Dollars
Quarter-Over-Quarter Growth and Year-Over-Year Rates by Region
3Q2017
2Q2017
3Q2016
3Q2017/2Q2017
3Q2017/3Q2016
Korea
4.99
4.79
2.09
4%
139%
Taiwan
2.37
2.76
3.46
-14%
-32%
China
1.93
2.51
1.43
-23%
35%
Japan
1.73
1.55
1.29
11%
34%
North America
1.50
1.23
1.05
22%
43%
Europe
1.06
0.66
0.53
61%
100%
Rest of World
0.74
0.62
1.13
20%
-34%
Total
14.33
14.11
10.98
2%
30%

Source: SEMI (www.semi.org) and SEAJ (http://www.seaj.or.jp)

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: the monthly SEMI Billings Report, which offers a perspective of the trends in the equipment market; the monthly Worldwide Semiconductor Equipment Market Statistics (WWSEMS), a detailed report of semiconductor equipment billings for seven regions and 24 market segments; and the SEMI Semiconductor Equipment Forecast, which provides an outlook for the semiconductor equipment market. More information is also available online: www.semi.org/en/MarketInfo/EquipmentMarket.

GLOBALFOUNDRIES and Ayar Labs, a startup bringing optical input/output (I/O) to silicon chips, today announced a strategic collaboration to co-develop and commercialize differentiated silicon photonic technology solutions. The companies will develop and manufacture Ayar’s novel CMOS optical I/O technology, using GF’s 45nm CMOS fabrication process, to deliver an alternative to copper I/O that offers up to 10x higher bandwidth and up to 5x lower power. This cost-effective solution is integrated in-package with customer ASICs as a multi-chip module, and improves data speed and energy efficiency in cloud servers, datacenters and supercomputers. As part of the agreement, GF has also invested an undisclosed amount in Ayar Labs.

Modern data centers and cloud applications require high-performance, power-hungry chips to process and analyze huge volumes of data in real time. Growth in chip I/O capabilities has not matched exponential increases in computing power, because of physical limitations in electrical data transmission. Optical I/O, which leverages optical components on the CMOS die to transmit data at rapid speeds, will be a key enabler to overcoming the limitations of today’s data center interconnects. In addition, Ayar’s technology reduces power consumption at both the network and processor level.

“GF has demonstrated true technology leadership in recognizing optical I/O as the inevitable next step as we move into a More than Moore world,” said Alex Wright-Gladstein, CEO at Ayar Labs. “This collaboration between Ayar and GF could improve chip communication bandwidth by more than an order of magnitude and at lower power, and is a validation of Ayar’s viability in the current semiconductor ecosystem. This collaboration will unlock a larger market opportunity, expanding both our and GF’s customer base. We look forward to working with GF to help solve the interconnect problems of today’s chips and create greater value for our customers than if both companies worked independently.”

“The Ayar Labs team has been designing cutting-edge silicon photonics components on GF’s technology for the past eight years and has achieved exceptional results,” said Mike Cadigan, senior vice president of global sales and business development at GF. “Our strategic collaboration builds on our relationship, leveraging GF’s silicon photonics IP portfolio and our world-class manufacturing expertise to enable faster and more energy-efficient computing systems for data centers.”

The collaboration brings together Ayar Labs’ patented IP in optical technology with GF’s best-in-class expertise in silicon photonics to co-develop optical solutions that will be fabricated using GF’s process technology. The availability of this technology, including certain Design IP cores, will enable internet service providers, system vendors and communication systems to push data capacity to 10 Tera bits per second (Tbps) and beyond, while maintaining the low energy and cost of optical-based interconnects.

Micron Technology Inc. (Nasdaq:MU) today announced that the company has appointed Derek Dicker as vice president and general manager of the Storage Business Unit.

In this role, Dicker will be responsible for leading and expanding Micron’s solid-state storage business. This includes building world-class storage solutions to address the growing opportunity in large market segments like cloud, enterprise and client computing. He will report to Sumit Sadana, Micron’s executive vice president and chief business officer.

Dicker has 20 years of experience in the semiconductor industry, including sales, marketing and executive roles at Intel, IDT, PMC-Sierra and Microsemi Corporation. Most recently, he served as vice president and business unit manager of performance storage at Microsemi, where he led a global organization and drove all general management functions.

“Derek’s deep technical expertise and experience in the storage industry make him the ideal choice to lead our storage business,” Sadana said. “His strategic mindset, coupled with his outstanding track record of business leadership, will help us fully capitalize on our leading-edge NAND technologies and solutions.”

Dicker holds a bachelor’s degree in computer science and engineering from the University of California, Los Angeles.

 

Transphorm Inc., a designer and manufacturer of highest reliability (JEDEC and AEC-Q101 qualified) 650V gallium nitride (GaN) semiconductors, announced it received a $15 million investment from Yaskawa Electric Corporation. This news comes only a few weeks after Yaskawa revealed its integrated Σ-7 F servo motor relies on Transphorm’s high-voltage (HV) GaN to deliver unprecedented performance and power density. Transphorm intends to allocate the funds to various areas of its GaN product development.

“We’ve seen the benefits of working with gallium nitride from the R&D phases through to the application development phases of our products, such as photovoltaic converters and the integrated Σ-7 F servo motor,” said Yukio Tsutsui, General Manager of Corporate R&D Center from Yaskawa. “We look ahead to further developments from Transphorm and its cutting-edge technology.”

The integrated Σ-7 F products resulting from the companies’ co-development serves one of the core target markets that can benefit most from HV GaN: servo motors. The technology is also an optimal solution for automotive systems, data center and industrial power supplies, renewable energy and other broad industrial applications.

“Transphorm has consistently prioritized the quality and reliability of our GaN platform,” said Dr. Umesh Mishra, Chairman, CTO and co-founder of Transphorm. “That focus leads to strong customer relationships with visionaries such as Yaskawa and companies that not only innovate, but also influence market growth by demonstrating GaN’s real-world impact. Receiving Yaskawa’s recent support illustrates the rising confidence in GaN while underscoring its reliability.”

SiFive announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program, and will be making RISC-V CPU IP including SiFive’s E31 and E51 RISC-V cores available on GF’s 22FDX process technology. Based on the open source RISC-V ISA, the SiFive E31 offers embedded chip designers new capabilities in high performance within strict area and power requirements, and the SiFive E51 offers a full 64-bit performance at 32-bit price, power and area.

“As the RISC-V ecosystem continues to grow, SiFive’s leading CPU IP is seeing increased adoption. Our partnership with GF is going to enable an even larger pool of system designers to build on an industry-leading process platform,” said Naveed Sherwani, CEO, SiFive. “SiFive has led the RISC-V ecosystem from early on and we are excited to continue extending RISC-V into new market segments.”

“As members of the RISC-V Foundation, we are excited to see more RISC-V IP offerings made available on our processes,” said Gregg Bartlett, senior vice president of CMOS business at GF. “SiFive’s wide range of cores makes them an ideal partner for our FDXcelerator program.”

GF’s FDXcelerator Program brings together select partners to integrate their products or services into validated, plug-and-play design solutions, giving customers access to a broad set of quality offerings specific to 22FDX technology. The program’s open framework enables members to minimize development time and cost while simultaneously leveraging the inherent power and performance advantages of FDX technology.

North America-based manufacturers of semiconductor equipment posted $2.02 billion in billings worldwide in October 2017 (three-month average basis), according to the October Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in October 2017 was $2.02 billion.The billings figure is 1.8 percent lower than the final September 2017 level of $2.05 billion, and is 23.7 percent higher than the October 2016 billings level of $1.63 billion.

“Equipment billings dipped in October, the fourth consecutive monthly decline during this record spending year,” said Ajit Manocha, president and CEO of SEMI. “In spite of this seasonal weakness, we expect equipment spending to increase by 30 percent or more this year and are positive about growth in 2018.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
May 2017
$2,270.5
41.8%
June 2017
$2,300.3
34.1%
July 2017
$2,269.7
32.9%
August 2017
$2,181.8
27.7%
September 2017 (final)
$2,054.8
37.6%
October 2017 (prelim)
$2,017.0
23.7%

Source: SEMI (www.semi.org), November 2017