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Datacenters with few other emerging applications will become a multibillion dollar market for silicon photonics by 2025. Transporting high level of data with existing technologies will soon reach its limit and photons will continue replacing step by step electrons throughout networks. Growing investments made by VCs have been identified by Yole Développements’ analysts and few startups have been created in this sector. All these indicators confirm the trend: silicon photonic technologies have reached the tipping point that precedes massive growth.

silicon photonics illustration

Yole Développement (Yole), the “More than Moore” market research and strategy consulting company releases this month the technology & market analysis titled Silicon Photonics for datacenters and other applications. Both experts Dr Eric Mounier, Sr Technnology & Market Analyst at Yole and Jean-Louis Malinge, former CEO of Kotura, now at ARCH Venture Partners combined their knowledge of the silicon photonic industry to perform a deep added-value analysis. Under this report, they examine the current status and future challenges for silicon photonics and data centers application. They detail for all applications, silicon photonic benefits as well as a comprehensive analysis of the industrial supply chain with player’s status.

What is the status of silicon photonic technologies? Could we already speak about commercial solutions? What is the market size today? What about tomorrow? How high are the current investments? Yole’s analysts offer you a snapshot of the story.

The silicon photonics market is still modest with estimated sales below US$40 million in 2015 and very few companies actually shipping products in the open market: Mellanox, Cisco, Luxtera, Intel, STMicroelectronics, Acacia and Molex are part of these leading players.

Silicon photonics has been under development for years. However now, this technology is being pushed hard by large webcom companies like Facebook and Microsoft. “Silicon photonics has reached the tipping point that precedes massive growth,” comments Dr Eric Mounier from Yole. “Indeed we estimate, the packaged silicon photonics transceiver market will be worth US$6 billion in 10 years.”

Silicon photonics is an exciting technology mixing optics, CMOS technology and advanced packaging. This combination benefits from semiconductor wafer manufacturing scalability to reduce costs.

“Silicon photonics offers silicon technology advantages including higher integration, more functionalities embedded with lower power consumption and better reliability compared to legacy optics”, analyzes Jean-Louis Malinge.

In 2020 and more, silicon photonic chips will far exceed copper cabling capabilities. Such solutions will be so deployed in high-speed signal transmission systems. In 2025 and more, the technology will be more and more used in processing such as interconnecting multiple cores with processor chips. Indeed, according to Yole’s analysts, the chip market value should score US$1,5 billion in 2025 at chip level (Estimated to be less than US$40 million in 2015). Step by step photons get closer to the chips!

Data centers are clearly the best opportunity for silicon photonics technology today. And there are also many other applications that silicon photonics can enable. These include high performance computers, telecommunications, sensors, life science, quantum computers and other high-end applications.

Two applications are particularly interesting as silicon photonics can push the integration of optical functions and miniaturization further to achieve successful products. Those applications are lidars for autonomous cars and biochemical and chemical sensors.

Lidars are costly and bulky instruments which make their integration in a car challenging. Within a promising ADAS market expected to reach US$3,9 billion in 2017 silicon photonic-based lidar will play a key role. Indeed silicon photonics allow lidar without moving elements, which can experience issues in a harsh car environment. Last august, MIT’s Photonic Microsystems Group announced a successful DARPA project using silicon photonics for lidar-on-a-chip with steerable transmitting and receiving phased arrays and on-chip Ge photodetectors.

Biochemical and gas sensors are not new, and several applications have existed for a while. Day by day, the interest in gas sensing is gaining importance due to the emergence of promising new large volume portable applications. Integration of biochemical or gas sensors into smartphones or wearables is currently on the roadmap of many companies but size, cost and sensitivity are still issues. To push optical gas sensor miniaturization further, some companies are already considering silicon photonics as an integration platform for their devices.

These non-data center applications will be about US$300 million in 2025, detail Yole’s analysts in the silicon photonics report.

Semiconductor Manufacturing International Corporation (“SMIC”; NYSE:  SMI; SEHK: 981), the largest and most advanced foundry in Mainland China, announces the official launch of a 12-inch integrated circuit (IC) production line at SMIC’s Shenzhen facility. It will be the very first 12-inch fab in South China.

In order to meet the large demand for IC chips in the IoT era, SMIC Shenzhen is building the new 12-inch IC production line in an existing building. The new line will manufacture mainstream mature technology. Construction is planned to start by the end of 2016. Some second-hand equipment for the new line has already been secured. The early production is expected to begin by the end of 2017.The total designed capacity is 40,000 12-inch wafers per month; capacity ramp will be based on customer needs.

Located in Pingshan New District, Shenzhen, SMIC Shenzhen opened the first 8-inch IC production line in South China in December 2014. Its capacity is currently 30,000 wafers per month, and it will continue to expand based on market demand.

The Chairman of SMIC, Dr. Zixue Zhou, said, “Shenzhen has the largest electronic information industrial base in China, comprising hundreds of IC design, system and equipment companies. Thanks to the attention given to the IC industry from the Shenzhen Municipal Government, SMIC Shenzhen steadily operates an 8-inch production line. By launching the new 12-inch production line, SMIC will further improve our capacity, better serve our customers, and facilitate the development of Shenzhen’s IC ecosystem.”

IC Insights will release the 2017 edition of its IC Market Drivers Report later this month.  The newly updated report reviews many of the end-use system applications that are presently impacting and that are forecast to help propel the IC market through 2020. IC Market Drivers 2017 shows that the market for automotive electronic systems is expected to display the strongest cumulative average growth rate (CAGR) through 2020, at 4.9%, highest among the six main electronic system categories (Figure 1). Safety and convenience systems are essential features that consumers look for and want in their new car.  Automatic emergency braking, lane departure/blind spot detection systems, and backup cameras are among the most desired systems.  For semiconductor suppliers, this is good news as analog ICs, MCUs, and a great number of sensors will be required for these and other automotive systems throughout the forecast.

Figure 1

Figure 1

Other electronic system and IC market highlights from the 2017 IC Market Drivers Report include the following.

•    Although the automotive segment is forecast to be the fastest growing electronic system market through 2020, its share of the total IC market was only 7.9% in 2016 and is forecast to remain less than 10% throughout the forecast period.

•    Industrial/Medical/Other electronic systems are forecast to enjoy the second-fastest growth rate (4.3%) through 2020 as wearable health devices, home health diagnostics, robotics, and systems promoting the Internet of Things help drive growth in this segment.  Analog ICs are forecast to hold 49% of the industrial/medical/other IC market in 2016.

•    Communications became the largest end-use market for ICs in 2013, surpassing the computer IC market.  Asia-Pacific is forecast to represent 67% of the total communications IC market in 2016; 70% in 2020.

•    The consumer electronics system market is forecast to display 2.8% CAGR through 2020.  The logic segment is forecast to be the largest consumer IC market throughout the forecast.  In total, the consumer IC market is expected to register a 2.3% CAGR through this same time period.

•    The worldwide government/military IC market is forecast to be $2.5 billion in 2016, but represent only 0.8% of the total IC market ($290.0 billion).  The Americas region is the largest regional market for military ICs, accounting for 63% of the worldwide military IC market this year.

•    Hit by slowing demand for personal computing devices (desktops, notebooks, tablets), the market for computer systems is forecast to show the weakest growth through 2020.  The total computer IC market is forecast to decline 2% in 2016 following a 3% drop in 2015.  Asia-Pacific is forecast to hold a 66% share of the computer IC market in 2016 and a 71% share in 2020.

Samsung Austin Semiconductor LLC (SAS) announced plans to invest more than $1 billion by the first half of 2017. Investments in its facilities will enhance current System LSI production to meet the growing demands in the industry for advanced system-on-chip (SoC) products especially for mobile and other electronic devices.

“Samsung is a bellwether for Austin. As a company that the community and state partnered with to relocate here several years ago, they have far exceeded expectations,” said Mike Rollins, President, Austin Chamber of Commerce. “Samsung remains a shining example of what happens when we create a business friendly environment. The result is a win that enhances and sustains our community’s ability to create a broad range of new jobs and economic opportunities for Austinites and their families.”

According to an Impact Data Source Economic Impact Study, SAS added $3.6 billion into the regional economy of central Texas in 2015. During that same time, SAS supported 10,755 jobs in the area and $498 million in annual salaries. Since its establishment in 1997, Samsung has invested more than $16 billion for the expansion and maintenance of its Austin facility.

“I was glad to discuss this with Samsung when our trade delegation visited Korea, and I’m thrilled that this plan is coming to fruition,” said Austin Mayor Steve Adler. “Samsung is so often a source of good news in Austin whether it’s about jobs, education, workforce development, housing or helping the homeless. Samsung is a great partner for Austin’s present, and this announcement tells us that they’ll be an even bigger part of our future.”

“We are committed to Austin and our contributions to the community,” said Catherine Morse, General Counsel and Senior Director of Public Affairs at SAS. “This is our home, and we want to ensure our community is healthy and prospering. These investments will support this, while also ensuring our customers’ growing needs are met.”

DSI announced today that ON Semiconductor has selected DSI’s Digital Supply Chain Platform (DSCP) to increase stock accuracy and improve worker productivity in its inventory processes across the global supply chain.

ON Semiconductor is a leading producer of semiconductors globally. The company chose the DSI DSCP for its unique ability to expand upon base ERP system functionality and work on- or offline through a certified, validated integration with its Oracle E-Business Suite (EBS) system. ON Semiconductor will deploy DSI’s mobile-first supply chain apps personalized by location and user, integrated with the company’s backend systems and business processes.

DSI will enable ON Semiconductor to manage parts used and product use-by dates in real time. The DSCP will automate the data capture process of moving materials while creating built-in measures that ensure the right chemicals are used on equipment. DSI’s automated validation of materials is expected to reduce costs associated with applying incorrect or expired materials.

Additionally, ON Semiconductor will gain efficiency and accuracy by filling gaps in functionality within its ERP system. The DSCP will enable ON Semiconductor’s employees to capture multiple pieces of data in a single scan and immediately update the backend system. The ability to extract multiple pieces of data in a different manner for each specific supplier will also help ON Semiconductor to speed the receiving process.

The speed with which the DSI platform scans, interprets and records the information will enable ON Semiconductor to have a single solution to improve efficiency across all its global operations, scanning 400% faster than the current solution. With this implementation, DSI will replace the company’s current solution, which was unable to perform at the required speed.

“The ability to perform whether online or disconnected was a key factor in selecting DSI,” said Fred Le Roy, Operations Manager, ON Semiconductor. “Having an app that continues to work offline protects the quality of our data and lets our personnel work efficiently in any environment.”

The speed and accuracy ON Semiconductor will be able to gain through the DSI platform will deliver benefits to production quality and efficiency as well as operational health and safety. The DSI solution enables mobile barcode scanners to work equally efficiently connected and disconnected. Switching seamlessly between both states ensures 100% data accuracy.

“Our customers choose DSI for a personalized user experience in enterprise-grade mobile apps that perform anywhere, on any device,” said Mark Goode, Chief Revenue Officer, DSI. “We look forward to working with ON Semiconductor to continue improving visibility and efficiency across its global supply chain with the Digital Supply Chain Platform.”

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics’ Process Design Kit (PDK) and Foundation Library on Samsung’s second-generation of 10nm LPP (Low Power Plus) process. Samsung also validated the Cadence reference flow using a quad-core design with the ARM Cortex-A53 processor on the 10LPP process, which was implemented with the low-power design methodology covering power-gating and memory retention, IEEE 1801 UPF2.1 power intent, and statistical on-chip variation (SOCV)-based timing closure using the Liberty Variation Format (LVF) library.

The Cadence digital and signoff tools met all of Samsung’s accuracy requirements, enabling foundry customers to quickly achieve design closure and deliver large, complex FinFET designs faster with the 10LPP process. In addition, the Cadence signoff tools have been certified for tapeout using Samsung’s certification criteria for baseline accuracy. The tools in the design flow include:

  • Innovus Implementation System: Based on a massively parallel architecture, it enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirements, such as floorplanning, placement and routing with integrated color-/pin-access /variability-aware timing closure, and clock tree and power optimization
  • Genus Synthesis Solution: Delivers improved productivity during register-transfer level (RTL) design and highly correlated, optimal quality of results (QoR) in final implementation
  • Quantus QRC Extraction Solution: Offers best-in-class accuracy versus foundry baseline; faster, scalable cell-level and transistor-level extraction; multi-patterning; multi-coloring; and a built-in 3D extraction capability, Quantus Field Solver (FS)
  • Conformal Logic Equivalence Checking (LEC): Ensures the correctness of logic changes and engineering change orders (ECOs) as well as the implementation flow, while enabling the comparison of different views/abstraction levels
  • Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs
  • Tempus Timing Signoff Solution: Provides integrated, advanced process delay calculation and static timing analysis (STA) that achieves Samsung’s accuracy requirements, including those at low voltage operation
  • Voltus IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy
  • Physical Verification System: Includes advanced technologies and rule decks to support design rule checking (DRC), layout versus schematic (LVS), smart metal fill, yield scoring, voltage-dependent checks, and in-design signoff
  • Litho Physical Analyzer: Enables designers to detect and automatically repair process hotspots to improve design manufacturability and yield of digital, custom and mixed-signal designs, libraries and IP. This is part of Samsung’s foundry DFM offering.
  • Cadence CMP Predictor: Predicts the 3D topology variation and hotspots caused by chemical mechanical polishing (CMP) to improve design manufacturability and reduce topology variation. This is part of Samsung’s foundry DFM offering.
  • LDE Electrical Analyzer: Allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate analog design convergence
  • Modus Test Solution: Provides scan and logic/memory built-in self test (BIST) insertion, combined with a new physically aware 2D Elastic Compression architecture, enabling design engineers to achieve reductions in test time to minimize production test cost

“Samsung and Cadence collaborated closely on this new 10LPP process reference flow to provide our mutual customers with a fast path to design closure,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “Cadence’s digital and signoff tools have implemented methodology innovations that enable designers to access and reap the benefits of our 10LPP process.”

“Samsung’s certification of the Cadence digital tools enables customers to manage and overcome complexity and deliver advanced 10LPP designs faster,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Customers using the Cadence flow on Samsung’s latest 10LPP process can also achieve optimal power, performance and area (PPA) to meet their aggressive time-to-market requirements.”

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its Custom Compiler tool has been certified by Samsung Electronics Co., Ltd. to support their 10-nanometer (nm) LPP (Low Power Plus) process. This included providing and validating a Custom Compiler process design kit (PDK) in the industry-standard iPDK format. The kit is available on request from Samsung.

The newly developed Samsung 10LPP iPDK includes all technology information needed to create schematics and layout for customer designs using the Custom Compiler tool with Samsung’s 10LPP process. This comprehensive kit includes support for the groundbreaking Custom Compiler visually-assisted automation flow. Custom Compiler features enabled by the kit include full coloring for triple-patterning, fast placement of FinFET device arrays with the Symbolic Editor, in-design resistance and capacitance reporting during layout, and high-performance in-design design rule checking (DRC).

“We worked with Synopsys to include Custom Compiler support for Samsung’s foundry process offerings,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “This new 10LPP iPDK adds to our existing portfolio of iPDKs that are available for Synopsys Custom Compiler users.”

Unified with Synopsys circuit simulation, physical verification and digital implementation tools, Custom Compiler technology provides Samsung 10LPP process users with a comprehensive custom design solution that reduces FinFET layout time.

“Custom Compiler users include leading-edge customers that demand support for the latest process technologies,” said Bijan Kiani, vice president of product marketing at Synopsys. “Samsung and Synopsys worked together to enable Custom Compiler for Samsung’s 10LPP process, which can shorten layout time from days to hours.”

ams AG (SIX: AMS), a provider of high performance sensors and analog ICs, a provider of high performance sensors and analog ICs, has announced its fast and cost-efficient IC prototyping service, known as Multi-Project Wafer (MPW) or shuttle run, with an updated schedule for 2017. The prototyping service, which combines several IC designs from different customers onto a single wafer, offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among all shuttle participants.

ams’ best in class MPW service offers the whole range of 180nm and 0.35μm specialty processes including the recently introduced 180nm CMOS technology (“aC18”). The aC18 process supports a large number of 1.8V and 5.0V NMOS and PMOS devices (substrate based, floating, low leakage and high threshold voltage options) and fully characterised passives including various capacitors. Area-optimised high-density and low-power digital libraries with gate densities up to 152kGates/mm², updated digital and analog I/O libraries with up to 6 metal layers as well as ESD protection cells with up to 8kV HBM level complete the offering. ams’ aC18 process is ideally suited for sensor and sensor interface devices in a wide variety of applications. All 2017 MPW runs in aC18 technology will be manufactured in ams’ state of the art 200mm fabrication facility in Austria ensuring very low defect densities and high yields.

In addition to the four aC18 MPW runs, ams will also offer four MPW runs in its advanced 180nm High-Voltage CMOS (aH18) technology supporting 1.8V, 5V, 20V and 50V devices. For its 0.35μm specialty processes a total of 14 runs are offered in 2017. ams’ 0.35μm High-Voltage CMOS process family, optimised for high-voltage designs in automotive and industrial applications, supports 20V, 50V and 120V devices as well as truly voltage scalable transistors. The advanced High-Voltage CMOS process with embedded EEPROM functionality as well as the 0.35μm SiGe-BiCMOS technology S35 are fully compatible with the base CMOS process and complete ams’ MPW service portfolio.

Overall, ams will offer almost 150 MPW start dates in 2017, enabled by co-operations with worldwide partner organisations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies.

The complete schedule for 2017 has now been released and detailed start dates per process are available on the web atwww.ams.com/MPW.

To take advantage of the MPW service, ams’ foundry customers deliver their completed GDSII-data on specific dates and receive untested packaged samples or dies within a short lead-time of typically 8 weeks for CMOS and 12 weeks for High-Voltage CMOS, SiGe-BiCMOS and Embedded Flash processes.

All process technologies are supported by the well-known hitkit, ams’ industry benchmark process design kit based on Cadence, Mentor Graphics or Keysight ADS design environments. The hitkit comes complete with fully silicon-qualified standard cells, periphery cells and general purpose analog cells such as comparators, operational amplifiers, low power A/D and D/A converters. Custom analog and RF devices, physical verification rule sets for Assura and Calibre, as well as precisely characterised circuit simulation models enable rapid design starts of complex high performance mixed-signal ICs. In addition to standard prototype services, ams also offers advanced analog IP blocks, a memory (RAM/ROM) generation service and packaging services in ceramic or plastic.

Learn more about the comprehensive service and technology portfolio of Full Service Foundry at www.ams.com/foundry.

North America-based manufacturers of semiconductor equipment posted $1.60 billion in orders worldwide in September 2016 (three-month average basis) and a book-to-bill ratio of 1.05, according to the September Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.05 means that $105 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in September 2016 was $1.60 billion. The bookings figure is 8.5 percent lower than the final August 2016 level of $1.75 billion, and is 3.2 percent higher than the September 2015 order level of $1.55 billion.

The three-month average of worldwide billings in September 2016 was $1.53 billion. The billings figure is 10.2 percent lower than the final August 2016 level of $1.71 billion, and is 2.6 percent higher than the September 2015 billings level of $1.50 billion.

“Semiconductor equipment bookings continue to outpace equipment billings,” said Denny McGuirk, president and CEO of SEMI.  “Year-to-date bookings and billings data are on trend to surpass last year’s levels.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
April 2016

$1,460.2

$1,595.4

1.09
May 2016

$1,601.5

$1,750.5

1.09
June 2016

$1,715.2

$1,714.3

1.00
July 2016

$1,707.9

$1,795.4

1.05
August 2016 (final)

$1,709.0

$1,753.4

1.03
September 2016 (prelim)

$1,534.4

$1,604.1

1.05

Source: SEMI (www.semi.org), October 2016

Avalanche Technology, Inc., has entered into a manufacturing agreement with Sony Semiconductor Manufacturing Corporation to begin production of it’s Spin Transfer Torque Magnetic RAM (STT-MRAM) on 300mm wafers at various advanced geometry nodes.  Volume production is expected in early 2017 at Sony Semiconductor Manufacturing Corporation in Japan to address a wide range of applications for this disruptive non-volatile memory technology.

This partnership with Sony Semiconductor Manufacturing Corporation will help the adoption of perpendicular Magnetic Tunnel Junction (pMTJ)-based STT-MRAM and further validate the widely accepted industry belief that STT-MRAM is the memory technology of choice for a broad spectrum of applications.

“Avalanche is working on breakthrough memory products.  As a result, we are able to address a very large non-volatile memory market with a wide range of requirements.  STT-MRAM is an ideal solution for markets such as Storage, Automotive, IoT and embedded applications,” said Petro Estakhri, founder and CEO of Avalanche Technology.

“We are pleased to partner with Avalanche Technology on the production of pMTJ based STT-MRAM,” said Toshiyuki Yanase, Representative of Yamagata Technology Center of Sony Semiconductor Manufacturing Corporation.  “Working with Avalanche Technology, we look forward to manufacturing MRAM products that meet current and future demands in the memory market.”