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SJ Semiconductor Corp. (SJSemi) and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated (NASDAQ:  QCOM), jointly announced that SJSemi has begun mass production of 14nm wafer bumping for Qualcomm Technologies. In the wake of 28nm wafer bumping mass production, and with further improvement of its processing techniques and capabilities, SJSemi has become China’s first semiconductor company to enter the industrial chain with 14nm advanced process node mass production. Mass production of the 14nm wafer bumping in China is part of Qualcomm Technologies’ efforts to continuously drive the development of the Chinese integrated circuit industry, and it further reinforces Qualcomm Technologies’ commitment to China through industrial chain optimization, localized services, and superior offers to Chinese customers.

Founded in August 2014, SJSemi is a joint venture between Semiconductor Manufacturing International Corp. (SMIC) and Jiangsu Changjiang Electronics Technology Co., Ltd (JCET). In December 2015, Qualcomm Global Trading Pte Ltd., a subsidiary of Qualcomm Incorporated, participated in an additional investment in SJSemi. SJSemi realized mass production of the 28nm wafer bumping in early 2016, within two years of its inception, and it now ships 12-inch wafers in high volume every month. SJSemi has sharpened its unique competitive edge in 28nm bumping technology by achieving not only a first-class yield rate but also industry-leading key technical indicators such as contact resistance control over high-density copper pillar bumping. SJSemi will continue to expand the capacity of its 12-inch wafer bumping line, securing the supply chain for its customers. Currently, SJSemi has reached the production capacity of bumping 20,000 12-inch wafers per month.

“We are grateful to Qualcomm Technologies for its consistent support. With its assistance, we have managed to set up an advanced 12-inch bumping line with stable and efficient production to offer mass production services to our customers,” said Mr. Dong Cui, Chief Executive Officer of SJSemi. “The mass production of our 14nm wafer bumping technology is in recognition of our capabilities and strengths, and indicates our ability to offer comprehensive services to first-class global customers like Qualcomm Technologies. We expect to continuously keep pace with customer demand, further improve our technical capability, enrich our process methods, and boost our added value to the industrial chain.”

“The 14nm bumping production from SJSemi is very important to Qualcomm Technologies and has begun mass production, which demonstrates SJSemi’s world-class manufacturing capabilities in leading-edge bumping process technology,” said Dr. Roawen Chen, Senior Vice President, QCT global operations, Qualcomm Technologies, Inc. “We are pleased to work with SJSemi to expand our semiconductor supply chain footprint in China, which further shows our commitment to support China’s local IC manufacturing and better serve our Chinese customers.”

Worldwide silicon wafer area shipments increased during the second quarter 2016 when compared to first quarter 2016 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,706 million square inches during the most recent quarter, a 6.6 percent increase from the 2,538 million square inches shipped during the previous quarter. New quarterly total area shipments are 0.1 percent higher than second quarter 2015 shipments and are at their highest recorded quarterly level.

“Silicon shipment growth continues to gain momentum resulting in a quarterly volume shipment high,” said Dr. Volker Braetsch, chairman SEMI SMG and senior vice president of Siltronic AG. “Although year-to-date shipments are effectively flat relative to the same period as last year.”

Silicon* Area Shipment Trends

Millions of Square Inches

2Q2015

1Q2016

2Q2016

1H2015

1H2016
Total

2,702

2,538

2,706

5,339

5,243

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

Worldwide semiconductor capital spending is projected to decline 0.7 percent in 2016, to $64.3 billion, according to Gartner, Inc. (see Table 1). This is up from the estimated 2 percent decline in Gartner’s previous quarterly forecast.

“Economic instability, inventory excess, weak demand for PC’s, tablets, and mobile products in the past three years has caused slow growth for the semiconductor industry. This slowdown in electronic product demand has driven semiconductor device manufacturers to be conservative in increasing production,” said David Christensen, senior research analyst at Gartner. “Looking ahead, it appears the second half of 2016 may see improved demand. However, following Brexit, semiconductor inventory levels may rise in the third and fourth quarters, which could lead to reduced production volumes.”

Table 1

Worldwide Semiconductor Capital Spending and Equipment Spending Forecast, 2015-2018 (Millions of Dollars)

2015

2016

2017

2018

Semiconductor Capital Spending ($M)

64,750.8

64,278.3

66,010.5

68,523.7

Growth (%)

0.3

-0.7

2.7

3.8

Wafer-Level Manufacturing Equipment ($M)

33,248.1

32,890.9

34,842.2

37,704.3

Growth (%)

-1.1

-1.1

5.9

8.2

Wafer Fab Equipment ($M)

31,485.4

31,071.8

32,862.1

35,491.5

Growth (%)

-1.3

-1.3

5.8

8.0

Wafer-Level Packaging and Assembly Equipment ($M)

1,762.7

1,819.1

1,980.1

2,212.9

Growth (%)

4.1

3.2

8.9

11.8

Source: Gartner (July 2016)

The PC, ultramobile (tablet) and smartphone production forecast for the second half of 2016 has been lowered from 2015, as the industry slowdown continues. These reductions have resulted in a forecasted 3 percent decline for the semiconductor market. Memory revenue growth for 2016 is also revised downward compared with the previous forecast, due to a weaker pricing outlook.

“While currency exchange rates are another reason for the ongoing revenue decrease, the aggressive pursuit of semiconductor manufacturing capability by the Chinese government and related investment companies is becoming a major factor,” said Mr. Christensen. “This will dramatically affect the competitive landscape of the global semiconductor manufacturing in the next few years as China becomes a major market for semiconductor usage and manufacturing.”

This research is produced by Gartner’s Semiconductor Manufacturing program. This research program, which is part of the overall semiconductor research group, provides a comprehensive view of the entire semiconductor industry, from manufacturing to device and application market trends. Additional analysis on the outlook for the market can be found at “Forecast: Semiconductor Capital Spending, Worldwide, 2Q16 Update.”

North America-based manufacturers of semiconductor equipment posted $1.71 billion in orders worldwide in June 2016 (three-month average basis) and a book-to-bill ratio of 1.00, according to the June Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.00 means that $100 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in June 2016 was $1.71 billion. The bookings figure is 2.1 percent lower than the final May 2016 level of $1.75 billion, and is 12.9 percent higher than the June 2015 order level of $1.52 billion.

The three-month average of worldwide billings in June 2016 was $1.71 billion. The billings figure is 7.0 percent higher than the final May 2016 level of $1.60 billion, and is 10.2 percent higher than the June 2015 billings level of $1.55 billion.

“Although order activity slowed for the most recent month,” said Denny McGuirk, president and CEO of SEMI. “Billings activity for equipment companies based in North America are at their highest level since February 2011.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
January 2016

$1,221.2

$1,310.9

1.07
February 2016

$1,204.4

$1,262.0

1.05
March 2016

$1,197.6

$1,379.2

1.15
April 2016

$1,460.2

$1,595.4

1.09
May 2016 (final)

$1,601.5

$1,750.5

1.09
June 2016 (prelim)

$1,714.0

$1,713.2

1.00

Source: SEMI (www.semi.org), July 2016

tsu-jae

Dr. Tsu-Jae King Liu

Intel Corporation today announced that Dr. Tsu-Jae King Liu has been elected to serve on Intel’s board of directors.

“We are very pleased to have Dr. Liu join the Intel board and look forward to her contributions,” said Intel Chairman Andy Bryant. “She brings a wealth of expertise in silicon technology and innovation that will be valuable for Intel in many areas as we navigate a significant business transition while continuing to lead in advancing Moore’s Law and harnessing its economic value.”

Liu, 53, holds a distinguished professorship endowed by TSMC in the Department of Electrical Engineering and Computer Sciences (EECS), in the College of Engineering at the University of California, Berkeley where she also serves as associate dean for Academic Planning and Development. Liu’s previous administrative positions within the College of Engineering include associate dean for research and EECS department chair. She has also held research and engineering positions at the Xerox Palo Alto Research Center and Synopsys Inc.

Liu holds over 90 patents and has received numerous awards for her research, including the Intel Outstanding Researcher in Nanotechnology Award (2012) and the SIA University Researcher Award (2014). Currently, her research is focused on nanometer-scale logic and memory devices, and advanced materials, process technology and devices for energy-efficient electronics. She received B.S., M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1984, 1986 and 1994, respectively.

Toshiba Corporation (TOKYO:6502) and Western Digital Corporation (NASDAQ:WDC) today celebrated the opening of the New Fab 2 semiconductor fabrication facility located in Yokkaichi, Mie Prefecture, Japan.

Expanded use of flash memory in smartphones, SSDs, and other applications is driving continued growth of the global flash memory market. The New Fab 2 facility will support the conversion of the companies’ 2D NAND capacity to 3D flash memory, allowing realization of solutions offering higher densities and better device performance.

Construction of New Fab 2 began in September 2014. Following partial completion of the facility in October 2015, Toshiba and SanDisk (acquired in May 2016 by Western Digital Technologies Inc., a wholly owned subsidiary of Western Digital Corporation) worked together to implement leading-edge manufacturing capabilities for mass production of 3D flash memory, and first-phase production started in March of this year. The parties intend to further invest to expand production capacity over time, depending on market conditions.

In addition, Yokkaichi operations will leverage the site-wide integrated production system, which employs big data processing to analyze over 1.6 billion data points each day, to further improve manufacturing efficiency and the quality of 3D flash memory.

The parties are committed to working together to enhance the value they offer to customers and to continue innovation as market leaders.

Satoshi Tsunakawa, President and CEO of Toshiba Corporation, said, “Advanced technologies underline our commitment to respond to continued demand as an innovator in flash memory. We are enhancing manufacturing efficiency and the quality of our world-class facility. Building on that, we also plan investments of as much as 860 billion yen by FY2018, in line with market situation. Our commitment is firm, and we are confident that our joint venture with Western Digital will produce cost competitive next generation memories at Yokkaichi.”

Steve Milligan, Chief Executive Officer of Western Digital, said, “As a leader in non-volatile memory products and solutions, we are excited to be entering the 3D NAND era with our partner Toshiba. The New Fab 2 enables us to begin the conversion of our existing 2D NAND capacity to 3D NAND and continues our long-standing presence in Yokkaichi, Mie Prefecture, and Japan.”

By Ed Korczynski, Sr. Technical Editor

New Materials Need New Handling Approaches photo

Wenge Yang, Vice President of Corporate Marketing, Entegris

Wenge Yang is vice president of corporate marketing for Entegris, and before joining the company in 2012 he earned a Ph.D. in Materials Engineering and served in various executive roles at Advanced Micro Devices, Tokyo Electron, and two startup companies, so he has a uniquely valuable perspective on materials trends in IC fabs. Yang spoke with the Show Daily about major trends in High Volume Manufacturing (HVM), and about the topics that will be discussed in the Entegris Yield Breakfast Forum “Yield Enhancement Challenges in Today’s Memory IC Production” happening Thursday morning, July 14.

 

3D-NAND

On the memory side the biggest challenge is that investment into different memory technologies has slowed innovation in DRAM. “People will hold the R&D money away from DRAM to try to find a DRAM-killer. So most of the innovation in memory is in 3D-NAND, and obviously Samsung is leading the industry with moves to build two new production lines to try to dominate the market.”

One of the known difficulties in 3D-NAND HVM is the etching and filling of contacts to the side “staircase” structure. Today the material used for contact fill is tungsten (W), while standard WF6 gas precursor shows some limits in ability to fill these contacts and in reliability. Going to more layers generally means deeper holes to fill, so fabs are exploring new fluoride-free-tungsten using chloride chemistry precursors which promise better process results.

EUVL

“EUV lithography has been debated for many years,” reminded Yang. “Finally, it has been developed to the point that it will be used in 2018 for pilot and in 2020 for production. Logic fabs will use it for 7nm-node processing, while in foundry fabs the 5nm-node will be the insertion point.”

Inpria and many of the legacy photoresist suppliers are developing new metal-core photoresist chemistry for improved sensitivity and Line-Width Roughness (LWR) in EUVL. Yang explains that new handling technologies will be needed for such photoresists, “A new requirement in purification is needed, while the filtration requirement for particles remains. This comes along with what we call ‘metal-phobia’ at the leading edge. In the past part-per-trillion levels were not issues, while today the whole delivery path becomes an issue and customers now ask about the materials of construction of all fluid-path components to ensure that no contaminants leach out into chemistry.”

Purity uncertainties

At the leading edge, a lot of focus is on gas purity requirements of new metal-organic precursors needed for ALD/CVD. “In reality, if we talk to IDMs they say that they honestly don’t know what is the right spec. Maybe part-per-trillion is too much, but they will say that they do not want to leave risk in the process,” confided Yang. “There are cases where a customer sees something happen and they can trace the problem back to a metal contamination level in a precursor. Obviously we know that less metal should be better, but we generally lack the ability to know exactly so the spec tends to stay at the prior node level.”

“In terms of the business dynamics, it is a challenge for us to create new products that meet the evolving needs of our leading customers,” explained Yang. “However the greater challenge is the serious overhead investment needed for more on-site customer support and more analytical lab tests. Supporting today’s customers is painful today, so smaller companies may find it too difficult and expensive to stay in the market.”

On Thursday morning of SEMICON West in the Yerba Buena level of the Marriott Marquis hotel, Entegris will host the 7th annual Yield Breakfast Forum. Micron will talk about XPoint manufacturing technology it has co-developed with Intel. XMC will talk about the dynamic of China developing it’s own materials supply-chain.

By Shannon Davis, Web Editor

“There’s never been a better time to connect” was the theme of John Kern’s keynote address at SEMICON West 2016 Tuesday morning, though it was clear from his speech that connecting – or digitizing – supply chains is not just a good idea, but imperative in the current ever-changing climate of the electronics supply chain.

John Kern, Vice President of Supply Chains, Cisco Systems, speaking at SEMICON West 2016 on Tuesday morning. (Source: SEMI)

John Kern, Senior Vice President of Supply Chains, Cisco Systems, speaking at SEMICON West 2016 on Tuesday morning. (Source: SEMI)

“If you’re not investing in digitization today, it’s going to be very, very difficult for you to remain relevant over the next decade,” Kern urged his audience.

Kern, who is Senior Vice President of Supply Chains at Cisco Systems, came equipped with several compelling case studies from his team’s own experiments, to make the case for why connecting the supply chain is so vital to innovation and profitability.

The first case study that Kern presented showed Cisco’s results from monitoring energy and energy costs in a factory setting. His team deployed a network of thousands of sensors that monitored energy readings of every piece of equipment in one of Cisco’s Malaysian factories, so teams could gather data and analytics on each piece’s performance. This initiative allowed the factory team to make changes in equipment to optimize performance, which resulted in a 12% energy reduction and a 1 million USD cost savings, which amounted to a full return on investment achieved in less than 10 months.

Kern also envisions a path to tens of millions of dollars in capital savings each year with adaptive testing, an initiative that’s currently saving Cisco test engineers man hours and allowing them to return to high value work. Kern said that Cisco was able to leverage analytics capabilities of a software they owned called Auto Test, along with Cisco’s own 10-15 years of test information, to build a test system that is now capable of machine-to-machine learning.

“The tests are becoming adaptive; they’re changing themselves,” said Kern, “and they’re notifying the engineers when they’re making a change.”

In addition to the cost and time savings, Kern believes this also allows for engineers to develop higher quality products.

And these products are also reaching the market faster, thanks to a Cloud-based supplier collaboration platform Cisco is using, that is allowing all of their suppliers to see real-time changes in demand and real-time changes in supply response, eliminating the bull-whip effect in the supply chain.

“We’ve also seen substantial improvement in product lead time,” Kern said. “We’re able to solve issues [with our suppliers] in a much faster way.”

Ultimately, this is where Kern says Cisco and its supply chain is headed: to what he calls supply chain orchestration.

“We’re trying to move this from a big IT project to having literally hundreds of people in our supply chain that are equipped to change the nature of their work every day,” he said. “If they understand the technology, they’re empowered to change the nature of their work.”

“This is the path for breakthrough productivity,” he concluded. “If you’re not investing heavily in these concepts today, it will be hard for you to stay relevant in the next decade.”

Photoresist manufacturers had reason to smile as fiscal 2015 closed, with sales growing nicely to $1.37B, a 6.2% increase over 2014. That bump has to sustain them through 2020, according to a new report from Techcet Group, “Critical Materials Report: Photoresists and Extensions and Ancillaries 2016.” Total volumes for photoresist and extension materials continue to grow with wafer starts, although revenues are expected to hover around $1.4B for the next 4 years. Growth from wafer starts in partially offset by reductions in photoresist thicknesses for critical layers in leading edge devices.

Virtually all of the growth in lithography materials can be attributed to volume growth in advanced nodes. While the 5 year CAGR outlook for silicon wafer starts is -2% for the 45nm node and larger, that same outlook is +10% for the 28nm node and smaller. ArF (193nm wavelength) resists already comprise over 40% of the total market. Extreme ultra-violent lithography (EUVL @ ~13nm wavelength) remains in the forecast for 2020, but it will be limited to mix-and-match implementation at the 10nm node due to its premium cost and low throughput. Nano-Imprint Lithography (NIL) is in limited use by one Asian memory fab. Multi-patterning with 193nm immersion will remain the workhorse for all leading edge IC fabs.

The category of resolution “extension” materials to enable finer feature patterning grows out of the segment for bottom anti-reflection coatings (BARC) and spin-on hard-masks (HM), which can be combined with a top layer of photoresist in a so-called “Tri-Layer Resist” (TLR) approach. Extensions also include specialty chemical formations to “trim” lines by removing photoresist material, or to “shrink” holes by adding material to sidewalls. The extension materials market is now the fastest growing segment, already at $650M in 2015 it is forecast to reach $790M by 2020, as detailed in TECHCET’s Report.

The photoresist ancillary segment that includes strippers/removers, developers, edge-bead removers (EBR) and specialty solvents is expected to suffer a slow decline from today’s $600M to $575M by 2020, primarily due to volume reductions associated with thinner photoresists. Also, ancillaries are generally sourced in large quantities from local suppliers, and regional pricing pressures further depress revenues in this sub-market.

There are six major suppliers controlling 90% of the global resist market, with a total of eleven key manufacturers offering standard and advanced photoresist products and critical ancillaries. JSR and TOK share 53% of the market, with others at 12% or less. In addition to market analysis, critical supply chain issues and technical trends, the report includes profiles and updates for major suppliers of photoresist and related materials to the global semiconductor industry.

The health of the semiconductor industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong semiconductor market growth without at least “good” worldwide economic growth to support it. Consequently, IC Insights expects annual global semiconductor market growth rates to continue to closely track the performance of worldwide GDP growth (Figure 1).  In its upcoming Mid-Year Update to The McClean Report 2016 (to be released at the end of July), IC Insights forecasts 2016 global GDP growth of only 2.3%, which is below the 2.5% level that is considered to be the global recession threshold.

Figure 1

Figure 1

In many areas of the world, local economies have slowed.  China, which is the leading market for personal computers, digital TVs, smartphones, new commercial aircraft, and automobiles, is forecast to continue to lose economic momentum in 2016.  Its GDP is forecast to increase 6.6% this year, which continues a slide in that country’s annual GDP growth rate that started in 2010 when growth rates exceeded 10%.

IC Insights believes that the worldwide economy will be negatively impacted, at least over the next year or two, by the Brexit vote this past June.  At this point, since the U.K. is unlikely to officially be able to leave the European Union (EU) for a couple of years, the biggest negative effect on economic growth is the uncertainty of the entire situation.  Some of the uncertainty created by the vote includes:

•    Whether the U.K. will actually leave the EU.  Since the Brexit vote is not legally binding, and still needs to be approved by the U.K. government, there is uncertainty if its departure from the EU will actually happen.

•    Whether the U.K. will come apart itself.  There are rumblings about Scotland breaking away from being a part of the U.K. in order for it to remain as part of the EU.

•    What trade deals will be made by the U.K. if it does leave the EU?  As part of its exit from the EU, the U.K. will need to establish numerous new trade deals with the EU.  There is tremendous uncertainty regarding whether these deals would have a positive or negative effect on the U.K. economy.

•    Will other countries follow the U.K. and depart from the EU?  Anxiety persists over whether the EU will fall apart as other countries attempt their own exit.  Some countries mentioned as possibly following the U.K. out of the EU include the Netherlands (Nexit), France (Frexit), Italy, Austria, and Sweden (Swexit).

The other major “culprit” dragging down semiconductor industry growth this year is the very weak DRAM market.  At $45.0 billion, the DRAM market was the largest single product category in the semiconductor industry in 2015.  IC Insights forecasts that the DRAM market will register a 19% drop of $8.5 billion this year to $36.5 billion.  The DRAM market alone is forecast to shave three percentage points off of total semiconductor market growth this year. Semiconductor market growth excluding DRAM is forecast to be +2%.

Most of the DRAM market decline expected for this year is due to a rapid decline in DRAM pricing over the past 18 months.  For 2016, the average price for a DRAM device is forecast to drop to $2.55, a steep 16% decline as compared to 2015’s DRAM ASP of $3.03. Further trends and analysis relating to semiconductor market forecasts through 2020 will be covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.