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The SEMI High Tech U learning program commenced April 20-22 in Hsinchu, Taiwan. Co-hosted by SEMI, KLA-Tencor Taiwan, and National Tsing Hua University, the three-day event offered 40 high school students an in-depth interactive learning experience in Science, Technology, Engineering, and Mathematics (STEM). Since SEMI High Tech U began in 2001, it has hosted 190 career exploration programs in eight different countries with over 6,000 high school students attending. The High Tech U programs have received a tremendous response globally.

This year, Taiwan was a host country for the first time. Terry Tsao, president of SEMI Taiwan, said, “The goal of High Tech U is to help young people gain knowledge and develop interests in STEM before choosing their future academic pursuit. Not only did Taiwanese high school students have the opportunity to attend this international STEM immersion program, but they also interacted with industry volunteers who serve in the high-tech industry.” Through group activities and firsthand experience, students thoroughly explored technology, adding to their ability to understand their future career directions.

“In the U.S., KLA-Tencor has collaborated with SEMI to hold seven SEMI HTU (High Tech U) programs. The first-ever Taiwan course design, instructor training, and the local operations planning, were tailored to inspire Taiwanese students to have better understanding of their direction and passion towards the semiconductor industry and their future goals,” said Tom Wang, CEO of KLA-Tencor Corporation Taiwan. Many employees at KLA-Tencor Taiwan volunteered to be course instructors and advisors to share their professional experience at SEMI High Tech U. In addition to providing guided tours at KLA-Tencor’s learning and training center cleanroom, the volunteers also held mock interviews with the students.

Nyan-Hwa Tai, dean of Academic Affairs at National Tsing Hua University, said “Courses at SEMI High Tech U are designed to gain practical experience through a non-conventional approach, which coincides with the values of innovative exploration at National Tsing Hua University.”

In three days, the students did practical exercises, learning individually and in groups. Tsao pointed out that “During the three-day program, students demonstrated a high level of enthusiasm, confidence, creativity, and team spirit, which is commendable. This event is just the beginning; SEMI will strive to expand the High Tech U program in Taiwan and allow more students to have the opportunity to participate.”

Learn more about the SEMI Foundation and High Tech U here: www.semi.org/en/semi-foundation. For more information about SEMI, visit www.semi.org and follow SEMI on LinkedIn and Twitter.

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, today reported that worldwide semiconductor manufacturing equipment billings reached US$8.3 billion in the first quarter of 2016. The billings figure is 3 percent higher than the fourth quarter of 2015 and 13 percent lower than the same quarter a year ago. The data is gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 95 global equipment companies that provide data on a monthly basis.

Worldwide semiconductor equipment bookings were $9.4 billion in the first quarter of 2016. The figure is 2 percent lower than the same quarter a year ago and 5 percent higher than the bookings figure for the fourth quarter of 2015.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

 

1Q2016

4Q2015

1Q2015

1Q16 / 4Q15
(Qtr-over-Qtr)

1Q16 / 1Q15
(Year-over-Year)
Taiwan

1.89

2.64

1.81

-29%

4%
Korea

1.68

1.22

2.69

38%

-37%
China

1.60

1.00

1.16

60%

39%
Japan

1.24

1.40

1.26

-11%

-2%
North America

1.01

0.92

1.47

10%

-32%
Rest of World

0.51

0.43

0.43

17%

18%
Europe

0.35

0.39

0.69

-10%

-49%

Total

8.28

8.00

9.50

3%

-13%

Source: SEMI/SEAJ

ClassOne Technology, manufacturer of budget-friendly wet processing equipment, is reporting significant savings in the plating of gold in ≤200mm applications using its Solstice systems. The savings come from elimination of gold waste, faster and simpler processing, and innovative Solstice-enabled techniques that can substantially reduce gold usage.

“Many users have been spending millions of dollars on gold each year,” said Byron Exarcos, President of ClassOne Group. “It’s a major issue, especially in emerging markets such as lasers, LEDs, RF and MEMS which often require gold layers as thick as 3 to 35 microns. “That’s why they’re becoming keenly interested in Solstice to cut their gold spending.”

“One fundamental advantage of Solstice electroplating is its elimination of gold waste,” explained Kevin Witt, President of ClassOne Technology. “Previously used CVD and PVD methods deposited gold not just on the wafer but also on the entire chamber interior. That ‘oversprayed’ gold was difficult to remove and inefficient to reclaim — which led to a considerable net loss of gold. By contrast, Solstice deposits only on the wafer, so there’s no gold waste, and no need for cleaning or gold reclamation efforts.”

Witt pointed out that Solstice economies also come from its higher gold deposition speed. Plating at 150 to 300nm/min, it is roughly ten times faster than CVD and PVD methods. In addition, Solstice starts processing immediately, not requiring an hour or more for pump-down as vacuum-based tools do. All of this translates to additional savings, from higher throughput and more cost-efficient production.

Innovative Solstice layering technique can cut gold usage dramatically

The unique 8-chamber design of the Solstice S8 enables it to readily replace a solid gold layer with a multi-metal stack — and reduce gold usage very substantially.

For example, a feature that previously required a 5µm layer of solid gold can now be replaced with a “sandwich” of 0.25µm Au, 1µm Ni, 2.5µm Cu, another 1µm Ni, topped with 0.25µm Au — to achieve equivalent functionality while reducing gold usage by a factor of ten! And Solstice’s multi-chamber design enables it to deposit all five layers in a single cycle; so no additional process steps or time are required to gain very significant cost savings.

ClassOne noted that over a year, total gold savings can grow quite large. For example, in the case cited above, if the solid gold 5µm layer covers 50% of a 150mm wafer area, and if the fab is running 1500 wafers per week through a metal lift-off process and gold costs $1200 per troy ounce — even if all oversprayed gold were recovered, the user’s annual gold expenditure would be roughly $2,150,000. However, if the special Solstice multi-metal layering technique were used, the total metal cost (for Au, Ni and Cu combined) would be reduced to approximately $108,000. This would yield an annual savings of over $2,042,000, which would more than pay back the cost of a Solstice.

The Solstice S8 provides eight modular chamber positions that can be used for plating a wide range of metals as well as performing additional processes. Solstice tools are available in three different models for production and development, and they serve many cost-sensitive emerging markets that use 200mm and smaller wafers. The systems are priced at less than half of what similarly configured plating systems from the larger manufacturers would cost — which is why Solstice has been described as “Advanced Plating for the Rest of Us.”

Electronic Fluorocarbons, LLC (EFC), a provider to the semiconductor industry of Electronic Specialty Gases (ESG’s), packaged and purified to the highest specifications, announces that construction is well underway on their manufacturing and purification facility on a 15 acre greenfield site in Hatfield Township, Montgomery County, Pennsylvania.  The facility is expected to begin operations in the 3rd quarter of this year.  Upon completion, EFC will combine and move its current production facility in Ivyland, Pennsylvania, to the larger Hatfield Township site.

electronic fluorocarbons

The new location’s close proximity to major shipping ports such as Philadelphia and New York/Elizabeth will provide a strategic advantage through easier access to global markets resulting in faster order fulfillment.

This plant will have bulk capabilities, strategic customer order staging, and research and development capabilities to allow EFC to expand into new markets, adding advanced materials as well as additional Electronic Specialty Gases to its core product line.

The Hatfield Township plant will include an R&D Center, with improved analytical capabilities where EFC’s experienced scientists and engineers will have the ability to develop new product lines beginning at the bench top, through the pilot plant phase, and then scaling up to market introduction.  This center will enable EFC to research purification methodologies that will exceed currently accepted standards in the semiconductor industry, while continuing to supply high quality, cost-competitive materials in a safe and responsible manner.

“This purpose-built facility represents a major milestone for Electronic Fluorocarbons.  It positions us well to execute on technical and strategic initiatives in several high growth markets, and to provide our customers with higher capacity and improved redundancy,” said Pavel Perlov, Electronic Fluorocarbons’ CEO and Founder.

“Electronic Fluorocarbons decision to remain in Pennsylvania will create high quality jobs over the next three years.  The township, county and state will also benefit from the company’s presence here,” said Pavel.   “We look forward to working closely with the local communities as we establish and grow our manufacturing capabilities in Pennsylvania. We truly appreciate the assistance of the staff of Hatfield Township, and other local officials in siting, permitting, and financing this facility”.

GLOBALFOUNDRIES today announced the signing of a memorandum of understanding to drive its next phase of growth in China. Through a joint venture with the government of Chongqing, the company plans to expand its global manufacturing footprint by establishing a 300mm fab in China. GLOBALFOUNDRIES is also investing in expanding design support capabilities to better serve customers across the country.

“China is the fastest growing semiconductor market, with more than half of the world’s semiconductor consumption and a growing ecosystem of fabless companies competing on a global scale,” said GLOBALFOUNDRIES CEO Sanjay Jha. “We are pleased to partner with the Chongqing leadership to expand our investment in support of our growing Chinese customer base.”

The initial plan of the project includes upgrading an existing semiconductor fab to accommodate the manufacturing of 300mm wafers using GLOBALFOUNDRIES’ production-proven technologies from its Singapore site. The proposed joint venture will provide immediate access to a state-of-the-art facility, accelerating time-to-market with production planned for 2017.

“In recent years, Chongqing has followed the cluster model to vigorously develop the electronic information industry, becoming one of China’s most important locations for intelligent end products manufacturing,” said Huang Qifan, Mayor of Chongqing. “During the period of China’s thirteenth five-year plan, Chongqing will continue to develop the intelligent IC and other strategic emerging industries, and promote sustained and healthy economic development in the region. GLOBALFOUNDRIES is a world-famous IC manufacturing company, and we welcome them to participate through cooperation to achieve mutual benefit and win-win. Cooperation between the two parties will help to enhance the production of intelligent IC technology in Chongqing, further improving the electronic information supply chain in Chongqing and the rest of China.”

GLOBALFOUNDRIES continues to strengthen its sales, support, and design services offerings in China, doubling over the past year with plans for continued growth. The company’s current presence is anchored by world-class design centers in Beijing and Shanghai, which have extensive expertise in custom designs supporting a robust ASIC platform, coupled with foundry design capabilities for a variety of technology nodes. These capabilities are complemented by key regional partners in its design and IP ecosystem.

As the opening day of SEMICON West (July 12-14) approaches, the electronics manufacturing industry is experiencing disruptive changes, making “business as usual” a thing of the past. To help technical and business professionals navigate this fast-changing landscape, SEMICON West programming has been upgraded extensively ─ increased from 170 hours to 250 hours this year. New brand and deep programming provide insights into the latest megatrends and helps attendees identify new opportunities and refine sound strategic plans.

At this year’s expo, several new forums designed to enhance collaboration within shared communities of interest will debut. Lead by technical experts, top analysts, and leaders from some of the biggest names in electronics, the new forums are generating significant advance interest and buzz, key among them:

  • Advanced Manufacturing Forum: Twelve cutting-edge sessions — from What’s Next in MEMS and Sensors to Power Electronics and 3D Printing — will be presented by Samsung, Applied Materials, Texas Instruments, and more. Attendees will learn about new technologies on the horizon and how they impact semiconductor manufacturing.
  • Flexible Hybrid Electronics Forum: Flexible Hybrid Electronics is driving new processes and packages, providing innovative approaches for health-monitoring, wearables, soft robotics, and other next-generation products. Attendees will get details on thinned device processing, system design, reliability testing and modeling from experts at Qualcomm, PARC, and GE Global Research.
  • World of IoT Forum: Forecasters predict that IoT will soon become a $6 trillion market. The World of IoT Forum brings together leading suppliers, integrators, and solution providers at the forefront of innovations in mobility, network-connected devices, and automotive and healthcare applications, among others. Attendees will learn about the trends impacting the market, including big data and analytics, smart things, and MEMS and sensor manufacturing.

With so many disruptive trends driving the market, it is critical for industry professionals to have a clear view of the road ahead. With its vastly expanded technical and business programming, this year’s expo will deliver the strategic insights needed to survive and thrive. To learn more and to register, visit SEMICON West Forums.

Nanoelectronics research center imec, Holst Centre (set up by imec and TNO) and micro-electronic design house Barco Silex, belonging to the Barco group, today announced that they will collaborate to implement data security into sensors for wearable devices and Internet of Things (IoT) sensor networks. The organizations are coming together to bring data security for the IoT to the next level.

Smart wearables for lifestyle and health monitoring as well as many other personal IoT applications are evolving with a plethora of capabilities at a rapid pace. However, trust is key for a broad adoption and the implementation of a true intuitive IoT society -with sensors invisibly embedded everywhere in the environment, measuring all kind of parameters and making smart decisions- to support everyday life. The smart society can only become a reality when the sensor technology is trusted by their users and the privacy of the users’ data is guaranteed at all time. Data security for the IoT is therefore considered as one of the main challenges to solve.

Current security solutions for IoT are designed for communication within one application domain or network. To realize a higher level of security, novel concepts for authentication, onboarding and end-to-end security in heterogeneous IoT networks are needed. Imec, Holst Centre and Barco Silex’ collaboration aims to leverage the technology and design expertise of imec and Holst Centre with the security IP portfolio of Barco Silex to develop novel chip architectures for secure ultra-low power sensors, and novel security concepts for reliable heterogeneous networks. Barco Silex will deliver the needed embedded security solution including crypto IP blocks to be implemented into imec’s multisensor IC for wearables and imec’s demonstrator platform for IoT. Imec will develop novel compute and memory architectures for minimal overhead of the secure implementation on the overall cost and power consumption of the sensors. In a next step, imec will study the impact of secure communication on throughput, response time and other performance aspects of heterogeneous IoT networks.

“This collaboration is part of a roadmap on a secure and intuitve IoT. Close collaborations with security experts like Barco Silex, but also with excellent research groups from KULeuven and iMinds will offer the imec ecosystem to develop novel and complete solutions for secure wearables and heterogeneous IoT networks. The program is open for new companies to join us on this exciting journey!” stated Kathleen Philips, program director  perceptive systems for an Intuitive IoT at imec.

“We are very pleased to be part of imec’s ambitious R&D program on intuitive IoT.” said Thierry Watteyne, CEO of Barco Silex. “This exciting collaboration is the recognition of the quality and flexibility of our security solutions. In addition it will help our developers to push our embedded security platforms solutions to the next level, especially in terms of optimizing the low power-high security equation within the chip architecture.”

North America-based manufacturers of semiconductor equipment posted $1.59 billion in orders worldwide in April 2016 (three-month average basis) and a book-to-bill ratio of 1.10, according to the April Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in April 2016 was $1.59 billion. The bookings figure is 15.6 percent higher than the final March 2016 level of $1.38 billion, and is 1.3 percent higher than the April 2015 order level of $1.57 billion.

The three-month average of worldwide billings in April 2016 was $1.46 billion. The billings figure is 21.5 percent higher than the final March 2016 level of $1.20 billion, and is 4.0 percent lower than the April 2015 billings level of $1.52 billion.

“Bookings reached their highest levels in eight months and billings levels also significantly improved in April,” said Denny McGuirk, president and CEO of SEMI. “The data reflect strong investments in 3D NAND and in China.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

  Billings
(3-mo. avg)		 Bookings
(3-mo. avg)		 Book-to-Bill
November 2015 $1,288.3 $1,236.6 0.96
December 2015 $1,349.9

 

 $1,343.5 1.00
January 2016 $1,221.2 $1,310.9 1.07
February 2016 $1,204.4 $1,262.0 1.05
March 2016 (final) $1,197.6 $1,379.2 1.15
April 2016 (prelim) $1,455.0 $1,594.6 1.10

Source: SEMI (www.semi.org), May 2016

Synopsys, Inc. today announced a pre-wafer simulation solution to help semiconductor manufacturers reduce process node development time. The new solution provides a comprehensive process, transistor and circuit simulation flow that enables technology development and design teams to evaluate various transistor and process options using a design technology co-optimization methodology that starts in the pre-wafer research phase. The generation of SPICE models, design rules and parasitics from TCAD and lithography simulations allow the creation of early process design kits to evaluate the performance, power, area and cost of a new process node.

“To meet the performance, power, area and cost targets of the 10nm process node and beyond, semiconductor manufacturers need to evaluate a larger number of process options, device architectures and materials, and account for design criteria in selecting the best options,” said Dr. Anda Mocuta, Director of Technology Solutions and Enablement at imec. “The new simulation solution from Synopsys enables seamless links in the DTCO chain and helps speed up the down-selection of technology options,” added Dr. Mocuta.

In the past, the development of new process nodes was focused on the scaling and optimization of a single device architecture, the planar MOSFET, and a single material, silicon. With the introduction of FinFET in logic and 3D-NAND in memory, the complexity of new process nodes increased significantly. This complexity will only accelerate as future process nodes will need to evaluate and select among a larger number of processes, device architectures and materials.

Increasing Complexity of New Process Nodes

  • To meet the expected gains in performance, power and area with each new process node, current and next-generation lithography technologies must be evaluated from the point of view of critical pitches, pattern printability and layout constraints
  • Achieving transistor performance and power targets requires consideration of new device architectures, such as nanowire FETs and tunnel FETs, with high-mobility channel materials as an option
  • Selection among this exploding number of process, device architecture and material options is further complicated by complex interactions between design rules, interconnect parasitics, and transistor performance, and the unavailability during the early stages of research of wafer data from which to build or calibrate models

Pre-Wafer Simulation Solution Benefits

  • Combines the production-proven Sentaurus TCAD, Process Explorer and Sentaurus Lithography tools with new tools for automated variation-aware SPICE model extraction
  • Enables the creation of PDKs from simulation data so design teams can assess the impact of technology options on circuit performance and area earlier than currently possible
  • By starting design-technology co-optimization earlier, process development teams can reduce expensive and time consuming wafer-based iterations when selecting the right options to meet process node performance, power, area, cost and timeline targets

“Working closely with our customers, we have developed a pre-wafer simulation solution to help our customers deliver process nodes faster,” said Dr. Howard Ko, senior VP and general manager of the Silicon Engineering Group at Synopsys. “Our unique combination of TCAD, litho and SPICE simulation enables us to deliver a complete solution to address the challenges in technology development of advanced process nodes,” added Dr. Ko.

Soitec (Euronext), a manufacturer of semiconductor materials for the electronics industry, today announced that on May 18, 2016, Silicon Genesis Corporation (SiGen) filed a motion to terminate the investigation by the U.S. International Trade Commission (ITC) in its entirety on the basis of the withdrawal of its complaint directed to silicon-on-insulator (SOI) wafers sold and imported into the United States by Soitec.

A robust patent portfolio is a key part of Soitec’s business model, which protects both manufacturing and licensing operations. The company uses its state-of-the-art innovative technologies to enhance the performance and energy efficiency of semiconductors. Today, Soitec’s IP portfolio contains more than 3,000 patents covering multiple technologies for manufacturing engineered wafers – mainly SOI wafers – which are used in making leading-edge products. SOI technology is critical for the global electronics chip industry, with SOI based chips being used in smart phones, tablets, servers, cars and networks.

About Soitec: Soitec (Euronext) is a world leader in designing and manufacturing innovative semiconductor materials. The company uses its unique technologies and semiconductor expertise to serve the electronics and energy markets. With 3,600 patents worldwide, Soitec’s strategy is based on disruptive innovation to answer its customers’ needs for high performance, energy efficiency and cost competitiveness. Soitec has manufacturing facilities, R&D centers and offices in Europe, the U.S. and Asia.