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Schaumburg, Illinois (October 2015) –  ETEL S.A., a leading international producer of direct drive-based motion technology, announces the opening of a new research and development division earlier this year. Owned by Dr. Johannes Heidenhain GmbH and based in Switzerland, ETEL plans to extend its position as a leader in the semiconductor industry worldwide.

“We are researching positioning systems with nanometer precision, especially for wafer production, where we are already ahead of the pack,” explains Alexander Hirter, CFO of ETEL. The new facility is outfitted with the latest technology to allow for pioneering research: “Our cutting-edge technical laboratory utilizes ground with no vibration and a constant room temperature.”

Situated in Biel, Switzerland, the new ETEL R&D center was established after substantial investment and with promise to further the development of direct drive motors, position and motion controllers and motion systems with nanometer precision. “Wafer production especially needs nano-precise positioning systems.  Even today, there is no flat screen, no iPhone without a bit of ETEL in it.  And we will increase that portion in the future,” explains Denis Piaget, Managing Director at ETEL.

While the center of ETEL’s activities, including production, will remain at the headquarters in Môtiers, Switzerland, the new site will play an important additional role in ETEL’s development.

North America-based manufacturers of semiconductor equipment posted $1.60 billion in orders worldwide in September 2015 (three-month average basis) and a book-to-bill ratio of 1.07, according to the September EMDS Book-to-Bill Report published today by SEMI. A book-to-bill of 1.07 means that $107 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in September 2015 was $1.60 billion. The bookings figure is 4.1 percent lower than the final August 2015 level of $1.67 billion, and is 35.1 percent higher than the September 2014 order level of $1.19 billion.

The three-month average of worldwide billings in September 2015 was $1.50 billion. The billings figure is 4.6 percent lower than the final August 2015 level of $1.58 billion, and is 19.7 percent higher than the September 2014 billings level of $1.26 billion.

“Both bookings and billings trended slightly lower in the September three-month average compared to August,” said Denny McGuirk, president and CEO of SEMI. “While year-to-date billings through the first three quarters are above 2014 billings, uncertainty with semiconductor demand has dampened expectations with capex plans in the near-term.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars. (Source: SEMI, October 2015.)

  Billings
(3-mo. avg)		 Bookings
(3-mo. avg)		 Book-to-Bill
April 2015 $1,515.3 $1,573.7 1.04
May 2015 $1,557.3 $1,546.2 0.99
June 2015 $1,554.9 $1,517.4 0.98
July 2015 $1,556.2 $1,587.3 1.02
August 2015 (final) $1,575.9 $1,670.1 1.06
September 2015 (prelim) $1,503.9 $1,602.3 1.07

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the SEMI Equipment Market Data Subscription (EMDS).

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This forecast provides an outlook for the demand in silicon units for the period 2015–2017. The results show polished and epitaxial silicon shipments totaling 10,042 million square inches in 2015; 10,179 million square inches in 2016; and 10,459 million square inches in 2017 (refer to table below). Total wafer shipments this year are expected to exceed the market high set in 2014 and are forecast to continue shipping at record levels in 2016 and 2017.

“2015 has been a record-breaking year for silicon shipments, attributed primarily to larger diameter wafers,” said Denny McGuirk, president and CEO of SEMI. “The outlook for the next two years is measured, but continues on a modest growth path.”

2015 Silicon Shipment Forecast
Total Electronic Grade Silicon Slices* – Does not Include Non-Polished
(Millions of Square Inches, MSI)

Actual Forecast
2013 2014 2015 2016 2017
MSI 8,834 9,826 10,042 10,179 10,459
Annual Growth 0% 11% 2% 1% 3%

Source: SEMI, October 2015; * Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

For more information on the SEMI Worldwide Silicon Wafer Shipment Statistics, visit www.semi.org/en/MarketInfo/SiliconShipmentStatistics.

Slowing China economy, strong U.S. dollar, and falling DRAM ASPs all contributing to weaker IC market outlook.

IC Insights recently released its October Update to The McClean Report, which examined the effects of slowing worldwide GDP growth and a stronger U.S. dollar on the 2015 IC market forecast.

Since all of IC Insights’ figures are presented in U.S. dollars, a strengthening U.S. currency deflates foreign sales and market results while a weakening U.S. dollar serves to inflate the sales and market figures. The rare occurrence of significant strengthening of the U.S. dollar versus most of the major currencies this year is expected to deflate the 2015 worldwide IC market growth rate by at least three full percentage points. This “deflation” presents itself in the form of lower IC average selling prices (ASPs), which are forecast to register a steep 5% decline this year when reported in U.S. dollars.

Figure 1 compares the worldwide monthly IC market figures from January through August of 2015 and 2014. As shown, the beginning of this year started out very strong with the January 2015/2014 IC market showing year-over-year growth of more than 10%. In total, the 1Q15 IC market ended up 6.5% higher than the 1Q14 worldwide IC market.

The second quarter of 2015 began by registering similar monthly year-over-year IC market growth that was displayed in 1Q15, with the combined 2015 April and May IC markets up 5.6% compared to the combined April and May IC markets in 2014. However, things began to change in June as the IC market ended up 3.1% lower than the June 2014 IC market. Unfortunately, as shown in Figure 1, the 2015 July and August worldwide IC markets followed the disappointing year-over-year trend that began in June.

It should be noted that the average second half versus first half of the year growth rate in the IC market since 1990 is 9.2%. However, IC Insights is forecasting that the 2H15 IC market will be down 1.0% as compared to 1H15. If this occurs, it would be only the fifth time since 1990 that the second half of the year IC market was worse than the first half (the other years being 1996, 2001, 2008, and 2011). This weak second half market has resulted in IC Insights lowering its full-year 2015 IC market forecast from +1% to -1%.

Figure 1

Figure 1

Looking ahead to 2016, three reasons lead IC Insights to believe that the worldwide IC market will register mid-single digit growth next year:

  1. The current excess IC inventory is forecast to be under control by early next year.
  2. Worldwide GDP growth in 2016 is expected to show some improvement as compared to 2015.
  3. The U.S. dollar is unlikely to show nearly as much strength against the major foreign currencies next year as it did this year.

IC Insights will present its detailed 2015-2019 IC market forecast by product type in the November Update to The McClean Report.

 

New S$150 million joint investment is expected to create 60 jobs for highly skilled scientists, engineers and researchers.

SINGAPORE, October 19, 2015 – Applied Materials, Inc. today announced it plans to establish a new R&D laboratory in Singapore in collaboration with the Agency for Science, Technology and Research (A*STAR). The S$150 million joint investment will focus on developing advanced semiconductor technology to fabricate future generations of logic and memory chips.

The S$150 million joint lab will be housed within A*STAR’s new R&D cluster at Fusionopolis Two and will feature a 400 square meter Class 1 cleanroom with state-of-the-art semiconductor process equipment that has been custom designed and built by Applied Materials. The facility will be staffed by 60 highly skilled researchers and scientists, working together with extended research teams at A*STAR’s other research institutes.

The joint lab combines Applied Materials’ leading expertise in materials engineering with A*STAR’s multi-disciplinary R&D capabilities. A*STAR’s Institute of Microelectronics (IME), Institute of Materials Research and Engineering (IMRE), and Institute of High Performance Computing (IHPC) will contribute to research in low-defect processing, ultra-thin film materials, materials analysis and characterization, and modelling and simulation in many areas. The joint lab is also supported by The Singapore Economic Development Board, and is in line with its efforts to promote leading-edge R&D and advanced manufacturing activities. The intention is for products developed by the joint lab to be manufactured by Applied Materials in Singapore. In addition, Applied Materials plans to conduct experiments on the synchrotron at the Singapore Synchrotron Light Source (SSLS) and work with the National University of Singapore where a new beamline for semiconductor applications is to be developed. Funding for the construction of the new beamline is supported by the National Research Foundation.

Mr. Gary Dickerson, President and Chief Executive Officer of Applied Materials, Inc., said, “A*STAR and the government of Singapore have been great R&D partners for Applied Materials. We are excited to expand our collaboration to develop advanced semiconductor technology for extending Moore’s Law. Applied Materials’ leading expertise in materials engineering can help solve the challenges of producing future generations of logic and memory chips.”    

Mr. Lim Chuan Poh, Chairman, A*STAR, said, “This collaboration will catalyse the development of emerging technologies for the global electronics market and advance Singapore’s position as a key R&D hub for the industry. The joint lab reaffirms A*STAR’s multi-disciplinary R&D capabilities to drive innovation in the electronics sector, a key growth area for Singapore’s economy, and will generate further economic value through the creation of good jobs.”

“The joint lab will strengthen capabilities for Applied Materials in Singapore, as we expand from advanced manufacturing to early stage R&D and designing global products,” said Mr. Russell Tham, Corporate Vice President & Regional President South East Asia, Applied Materials, Inc. “Successful public-private partnerships, leveraging complementary strengths, help create new forms of value from Singapore and keep the local industry competitive.”

Prof. Raj Thampuran, Managing Director, A*STAR, said, “The new joint lab takes the longstanding collaboration between Applied Materials and A*STAR to the next level, and will marshal our combined strengths in research, development, innovation and industrial applications. This technology will pioneer new processes and techniques to advance the fabrication of semiconductor devices.”

The new joint lab marks Applied Materials’ second collaboration with A*STAR. In 2012, Applied and A*STAR’s IME formed a Center of Excellence in Advanced Packaging in Singapore to develop advanced 3D chip packaging technology.

This week, SEMI announced an exceptional lineup of speakers for SEMICON Japan’s keynote stage “SuperTHEATER”, which focuses on key market and technology challenges and developments, and their impact on the semiconductor supply chain. SEMICON Japan 2015, the largest exhibition in Japan for semiconductor manufacturing and related processing technology, will take place at Tokyo Big Sight in Tokyo on December 16-18.

Japan’s semiconductor industry capital expenditure rebounded in 2014 and this year 13 percent growth is forecast for equipment spending. For front-end equipment, a 33 percent increase is expected in Japan this year according to the recent SEMI World Fab Forecast report. Drivers for the increased investment are: NAND Flash, CMOS sensors, power semiconductors, and automotive semiconductors.

Attendees at SEMICON Japan will explore the key technologies and business models necessary to grow in the coming years. The SuperTHEATER will offer nine keynote forums, all with simultaneous English-Japanese translation, with global top executives. Opening Keynote presenters are:

  • Fujitsu: Masami Yamamoto, chairman and representative director
  • Tata Consultancy Services Japan: Amur S. Lakshminarayanan, president and CEO
  • Rakuten Institute of Technology: Masaya Mori, executive officer and representative

The Semiconductor Executive Forum features executives from Micron Technologies, Renesas Electronics, and Sony. The SEMI Market Forum offers presentations from IHS Global, VLSI Research, and SEMI. An IT Forum features presenters from Cisco Japan, Google Japan, Microsoft Japan, and Qualcomm. The Lithography Business Forum and Manufacturing Innovation Forum showcase speakers from Dai Nippon, KLA-Tencor, Intel, Nomura, Toshiba, and TSMC. The Digital Society Forum features speakers from Cisco Japan, Hitachi and Frost & Sullivan Japan, while the Smart Life & Smart Car Forum with have presenters from IBM Japan, Nissan Motor and Renesas Electronics. The Grand Finale Panel program features top Japanese semiconductor supply chain executives — from Toshiba, Infineon Japan, JSR, Tokyo Electron, Micron Memory Japan, and Megachips.

VeriSilicon Holdings Co., Ltd. and Vivante Corporation today announced a definitive merger agreement under which the companies will be combined in an all-stock transaction. The combined company, to be called VeriSilicon Holdings Co., Ltd., will offer robust IP-centric, platform-based custom silicon solutions and end-to-end semiconductor turnkey services.

Highlights of the transaction include:

  • Revenue for the combined company of more than $180 million for the year ended December 31, 2014;
  • Expected to be accretive to VeriSilicon’s non-GAAP earnings;
  • Establishes richer IP portfolio with the addition of licensable graphic cores (GPU);
  • Expands opportunities in the automotive market with established top OEM customers;
  • Increases exposure and content in IoT applications, as well as mobility applications, including smartphones, tablets, and connected TVs;
  • Leverages VeriSilicon’s extensive IP portfolio, design services capabilities and established direct sales channels worldwide;
  • Expands Tier 1 customer base

With the addition of Vivante’s GPU and vision image processing solutions, VeriSilicon continues to build out its Silicon Platform as a Service (SiPaaSTM) offering. Vivante has an established global customer base of over 50 licensees and has shipped more than 300 million units. Additionally, Vivante is a recognized industry leader in GPU solutions for automotive display, visualization and vision processing as well as mass market IoT applications. The combined company will hold a patent portfolio of more than 75 issued and pending U.S. patents and maintain operations in eight countries.

“This transaction creates an extensive semiconductor IP portfolio that will now include GPU cores, vision image processors, digital signal processors, video codecs, mixed signal IP and foundry foundation IP,” said Wayne Dai, VeriSilicon chairman, president and chief executive officer. “We expect our combined technology and scale will enable us to further extend our franchises in the automotive, IoT, mobility, and consumer market segments. Additionally, we share a strong culture of innovation and creativity that will provide significant benefits to our semiconductor, system and Internet platform customers by delivering best-in-class IP, design services and turnkey ASICs. This Silicon Platform as a Service (SiPaaSTM) model enables our customers to deliver high-quality, differentiated products in the fastest and most cost-effective way possible.”

“Together, VeriSilicon and Vivante will be well positioned to achieve even greater success,” said Weijin Dai, Vivante chief executive officer. “Our technology has been instrumental in providing PC-quality performance and experience at mobile power levels to create life-like graphics across a number of key end market segments and applications. VeriSilicon shares our vision for providing exceptional technology solutions that meet the unique requirements of automotive and IoT customers, as well as mobility, consumer and gaming customers. Our complementary products and capabilities will enable the combined company to pursue significant new growth opportunities, while delivering even greater value to customers, employees and shareholders.”

According to a new market research report on the “Chemical Mechanical Planarization Marketby type (Equipment & consumables), Application(IC manufacturing, MEMS & NEM, Optics and Others), Technology (Leading edge, More Than Moore’s, and Emerging), and Geography (North America, Europe, APAC and RoW) – Global Forecast to 2020”, published by MarketsandMarkets, the market is expected to grow at a CAGR of 6.83% between 2015 and 2020, and reach $4.94 Billion by 2020.

Chemical mechanical planarization is a critical process technology step in the semiconductor wafer fabrication process. In this process step, the top surface of the wafer is polished or planarized to create a flawless flat surface that is essential to make faster and more powerful semiconductor devices with the aid of chemical slurry & mechanical movements. The CMP tool is comprised a rotating platen, slurry, pad, holding ring, brush, and pad conditioner. The mechanical element of this system applies downward pressure to a wafer surface, while the chemical reaction increases the material removal rate. The value chain of the CMP market consists of different players, including semiconductor material suppliers, CMP integrated solution providers, semiconductor wafer suppliers, semiconductor device manufacturers, slurry & pad manufacturers, technology solution providers, and CMP equipment manufacturers.

The global Chemical Mechanical Planarization Market was worth USD 3.32 Billion in 2014, and it is expected to reach USD 4.94 Billion by 2020, at an estimated CAGR of 6.83% from 2015 to 2020. Though the CMP market is at the mature stage, it still continues to evolve depending on the end users. The industry is being forced to adopt much innovation in process technologies and applications; as a result, different CMP processes have been evolved with technology nodes and newer applications such as MEMS, advanced packaging, and advanced substrates. The growing demand for consumer electronic products, increasing need of wafer planarization, and increasing use of micro-electro-mechanical systems (MEMS) is driving the global CMP market.

The CMP equipment market is expected to grow at the highest CAGR of 8.32% from 2015 to 2020. The key factors behind the high growth of the CMP equipment market is the strong growth in semiconductor equipment and capital spending. The CMP consumables market was valued at USD 2.25 Billion in 2014 and is expected to reach to USD 3.21 billion by 2020. The Applied Materials, Inc. (U.S.) and Ebara Corporation (Japan) are the major CMP equipment suppliers for different integrated device manufacturers.

This CMP consumables market is dominated by major market players such as Cabot Microelectronics Corporation (U.S.), Fujimi Incorporated (Japan), and Dow Electronic Materials (U.S.).The CMP regional market is mainly dominated by Asia-Pacific, followed by North America and Europe. The Asia-Pacific region accounted for the largest market share of ~67% and is expected to grow at the highest CAGR of 7.40% during the forecast period, followed by North America. The countries in Asia-Pacific region such as Taiwan, South Korea, Japan, and China are investing more in semiconductor manufacturing to meet the increasing demand for consumer electronic products. This detailed market research study provides detailed qualitative and quantitative analysis of the global chemical mechanical planarization market. It provides a comprehensive review of major market drivers, restraints, opportunities, challenges, and key issues in the market.

Nano-electronics research center imec and Cadence Design Systems, Inc. today announced that the companies completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography. To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence (R) Innovus (TM) Implementation System. Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.

The Innovus Implementation System is a next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with best-in-class PPA while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain. For more information on the Innovus Implementation System, please visit http://www.cadence.com/news/innovus.

“Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of Process Technology at imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-generation platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes.”

“By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “With imec technology and the Cadence Innovus Implementation System, we’ve created a working flow that can pave the way for developing innovative next-generation mobile and computer advanced-node designs.”

The 2015 market for dielectric precursors is expected to total $230M, of which over $45M is attributed to low-κ dielectrics, according to a new report from Techcet Group, “2015 Techcet Critical Materials Report on Advanced Insulating Dielectric Precursors.” The outlook is for 8.5% growth to ~$250M in 2016, continuing to almost $300M by 2020 for a 5-year CAGR of 5.1%.

With 3D structures displacing planar 2D transistors in leading edge nodes, the call for new dielectric materials and deposition processes has continued to fragment. Device films require extreme conformality, precision uniformity in atomic layer thicknesses, and aspect ratio fills of 70:1 or more at deposition temperatures below 200°C. Masking films and sacrificial layers have to meet exacting specifications for removal selectivity, edge definition and etch resistance.

DialectDataTechcet’s 2015 Dielectric Precursors Report provides strategic information on the dielectrics market including revenue by precursor type/application and market share ranking. It also includes critical information used to ensure business continuity and support category management of the CVD, ALD, and SOD dielectric markets and their supply chains. In addition to business and technology trends, supply chain and geopolitical issues that impact dielectric precursors are also discussed in this year’s report.