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Flip Chip technology is expected to reach $25 billion market value and wafer demand of 32 million (12” eq. wafers) in 2020, supported by the wider adoption of Cu pillar technology. That growth will be led by Moore’s law pushing beyond the 28nm node and “More than Moore” evolution in next generation DDR and 3DICs.

flipchip_marketfigures_yole_oct2015_433x280The “More than Moore” market research and strategy consulting company Yole Développement’s (Yole) new analysis is entitled Flip Chip Technologies & Markets Trends (October 2015, Yole Développement). In this new report, Yole proposes a deep-added value analysis of the Flip Chip markets, players’ dynamics, and key trends. The consulting company highlights the key market figures and presents future Flip Chip strategy evolution and opportunities. Strongly linked to the Cu pillar technology, Flip Chip solutions have been largely adopted towards the mobile-wireless, consumer and computing applications, including continuous growth in the LED and CMOS Image Sensor (CIS) segments.

“Flip Chip assembly technology provides various benefits such as high I/O counts, fine pitch interconnection, and superior electrical and thermal performance,” explains Thibault Buisson, Technology & Market Analyst, Advanced Packaging at Yole. And he adds: “This drives its application across specific segments.”

The maximum growth in flip-chip bumping capacity will come from Cu pillars, driven by the finer pitches, higher I/O counts, lithography nodes below 28nm, emergence of 2.5D/3D packaging, increased current density and thermal dissipation needs. In the meantime lead-free solder bumping is expected to grow at just 2% CAGR as OSATs and foundries converting their existing solder bumping lines to Cu pillar lines. With the scaling of the Flip Chip pitch, OSATs are presently pushing the envelope of C2 mass reflow bonding with capillary underfill to pitches as low as 50µm by formulating engineered materials and improving assembly processes. However, if the pitch reaches or falls below 40µm Thermo Compression Bonding (TCB) will be the key option because of its high placement accuracy.

TCB will be adopted first in high volume manufacturing by IDMs like Intel, who can bear the high cost of ownership, followed by memory suppliers for their next generation memories based on through-silicon via technology.

“Intel has recently qualified ASM’s high throughput TCB bonder for assembly of 14nm chips for their CPUs in applications such as data centers, servers, and high-end computing”, comments Santosh Kumar, Senior Technology & Market Analyst, Advanced Packaging at Yole. And he adds: “At Yole, we estimate Flip Chip bonders’ total market value will reach US$435 million in 2020, with a CAGR of 7%. Flip Chip bonders and underfill materials will become key in coming years.”

The eBeam Initiative, a forum dedicated to the education and promotion of new semiconductor manufacturing approaches based on electron beam (eBeam) technologies, today announced the completion of its fourth annual eBeam Initiative members’ perceptions survey. A record 64 industry luminaries representing 35 different companies from across the semiconductor ecosystem–including chip design, equipment, materials, and manufacturing, as well as photomasks–participated in this year’s survey. The eBeam Initiative also completed its first-ever merchant and captive mask makers’ survey. In related news, ZEISS, a company in lithography optics for semiconductor manufacturing, has joined the eBeam Initiative.

Among the results of the members’ perception survey, respondents expressed increased optimism in the implementation of EUV lithography for semiconductor high-volume manufacturing (HVM) compared to last year’s survey, while at the same time acknowledging that EUV lithography is expected to add greater complexity to photomask manufacturing. In addition, expectations on the use of multi-beam technology for advanced photomask manufacturing continue to remain strong. Results from the eBeam Initiative’s first mask makers survey–which not only provides insight into the challenges and opportunities for photomask manufacturers but also gives mask makers a way to assess their own progress relative to their peers–indicate growing mask complexity across many fronts. The complete results of both surveys will be presented and discussed by an expert panel today during the eBeam Initiative’s annual members meeting at the SPIE Photomask Technology Conference in Monterey, Calif., and are available for download at www.ebeam.org.

Highlights from eBeam Initiative Member Survey

  • 62 percent of respondents predict that multi-beam technology will begin to be used for photomask production by the end of 2016 to address the critical problem of mask write times as the industry moves to smaller geometries.
  • Mask makers appear to be the most optimistic about the availability of multi-beam mask writers, with a near-unanimous 96 percent of mask makers participating in the survey indicating that multi-beam will be used for HVM mask writing by the end of 2018, compared to 65 percent of all equipment suppliers.
  • Among five next-generation lithography (NGL) technologies being considered for advanced semiconductor fabrication, respondents predict EUV as the most likely NGL method to be used in at least one manufacturing step by 2020, with an average confidence rating of 62%.
  • At the same time, 59 percent of respondents predict that EUV will drive the need for complex mask shapes.

Highlights from Mask Makers Survey (data from Q3 2014 through Q2 2015)

  • Mask sets below the 22-nm logic node are exceeding 60 masks for the first time, while mask sets have seen a long-term growth rate of 13 percent since the 250-nm node.
  • Average mask writes times have exceeded the nine-hour mark (9.6 hours) while the longest write time reported was 72 hours.
  • A strong majority (75 percent) of mask makers predict that they will modulate exposure dose on a per-shot basis in 2017.

“eBeam technology is critical to enabling the continuation of Moore’s Law, regardless of which lithography approach is used for semiconductor design and cost scaling,” stated Dr. Markus Waiblinger, senior product manager, strategic business unit Semiconductor Metrology Systems of ZEISS. “As an innovator in the use of eBeam technology for optical and EUV mask inspection, review and repair solutions, ZEISS applauds the eBeam Initiative for educating the semiconductor supply chain about new developments in eBeam technology and for providing a forum for greater collaboration. Efforts like the annual members’ survey and now their first mask makers’ survey play an important role in fulfilling that charter, and we’re pleased to have the opportunity to participate as a new member of the eBeam Initiative.”

“On behalf of the eBeam Initiative, I wish to thank all of our members–including our newest member ZEISS–for their participation in our fourth annual members’ perception survey,” stated Aki Fujimura, CEO of D2S, the managing company sponsor of the eBeam Initiative. “2015 has truly been an exciting year for the Initiative, as members of the eBeam community continue to step forward with new solutions to solve some of the semiconductor and photomask industry’s most pressing manufacturing challenges. Interest and excitement in eBeam technology continues to grow, which is reflected in the record turnout of responses that we received for our annual survey, as well as the strong reception from the global mask community toward our inaugural mask makers’ survey. Feedback from these surveys is invaluable in helping guide our education efforts within the eBeam supply chain, and we look forward to presenting our results for both surveys at the SPIE Photomask Conference later today.”

D2S (R), a supplier of GPU-enabled software for semiconductor manufacturing, today announced that it has partnered with Advantest, the world’s largest supplier of semiconductor Automatic Test Equipment, to integrate D2S’ Wafer Plane Analysis engine into Advantest’s Mask MVM-SEM (Multi Vision Metrology Scanning Electron Microscope) systems. This new capability enables fast and highly repeatable CD metrology for complex photomask shapes, including those created by inverse lithography technology (ILT), which enables photomask manufacturers to quickly, accurately and cost-effectively identify mask-level CD uniformity (CDU) issues that will impact the wafer during subsequent lithography processing in the wafer fab.

“We’re pleased to be working with D2S on developing a joint solution to improve mask CDU analysis, which results in a better quality mask for our customers,” stated Takayuki Nakamura, Executive Officer, General Manager of Nanotechnology Business Division, Advantest. “Combining D2S’ expertise in GPU-accelerated simulation technologies with our leading-edge CD-SEM tools–such as our new E3640–allows us to provide a cost-effective platform for extremely fast lithography simulation.”

Advanced photomasks are increasingly adopting non-orthogonal patterns and complex shapes, such as curvilinear mask patterns, due to the need for aggressive optical proximity correction (OPC) and ILT to enable production of leading-edge semiconductor devices with ever-smaller feature sizes. As these mask patterns become more complex, conventional CD metrology that measures CDs on straight lines/spaces no longer works since most mask patterns do not have uniform CDs after OPC and ILT correction. In addition, the number of mask defect issues flagged during mask inspection increases. However, not all of these mask issues will actually result in yield problems on the wafer. As a result, this increases the need for photomask manufacturers to understand the wafer-level impact of mask-level issues.

Wafer plane (aerial) analysis has emerged as a solution for identifying mask-level CDU issues that will impact the wafer. However, optical-based wafer plane analysis solutions are expensive, can be slow to implement, and have difficulty providing repeatable results. Mask manufacturers need a new wafer plane analysis solution that is less expensive, faster, and highly repeatable without requiring new equipment or additions to the mask inspection process.

The D2S Wafer Plane Analysis Engine provides aerial simulation of mask contours extracted by the Advantest MVM-SEM for today’s complex mask patterns, including ILT shapes for memory and logic. It is fully integrated into the Advantest CD-SEM system, which enables mask shops to access the benefits of GPU-accelerated wafer plane analysis without adding costly iterations with a standalone optical system.

“GPU acceleration is a powerful tool for enabling fast and accurate aerial simulation of complex mask patterns. It is particularly advantageous on curvilinear mask contours, which are increasingly being populated in today’s leading-edge photomasks,” stated Dr. Linyong (Leo) Pang, chief product officer and executive vice president of D2S. “The new Wafer Plane Analysis Engine from D2S provides wafer plane analysis capability within seconds. Combining our capability with Advantest’s SEM solutions gives their customers a powerful solution for identifying which mask features truly have a CDU problem on the wafer in order to enable swift and cost-effective correction. It can also be used for mask post-inspection defect review to enable fast dispositioning of defects based on their simulated printability. “

Rudolph Technologies, Inc. announced today that it has purchased Stella Alliance, LLC, a Massachusetts-based semiconductor inspection technology intellectual property (IP) portfolio company. Stella Alliance’s patented illumination, auto-focus, and image acquisition technology significantly enhances the ability to identify certain critical defects not visible with current techniques. With this acquisition, Rudolph expects to add a next-generation, high-resolution inspection system to its portfolio of solutions in the second quarter of 2016. Additionally, the acquired technology is able to handle large rectangular substrates, extending Rudolph’s inspection portfolio footprint into growing unserved segments of microelectronic device manufacturing.

Paul McLaughlin, Rudolph’s chairman and chief executive officer, stated, “We expect the addition of this patented technology to bring a competitive advantage to our customers by addressing current inspection limitations, while helping Rudolph maintain the dominant market share in the back-end inspection arena.”

The technology was developed to overcome the challenges of detecting residue-related defects that traditional technologies can miss. These defects can have a significant impact on the interconnect quality, such as incomplete etch of bond or bump pads, faint copper bridging and stringers at the bottom of vias and high aspect ratio trenches in fan-out wafer level packaging (FOWLP), wafer-level chip scale packaging (WLCSP) and embedded die applications.

In addition, the technology provides the high resolution needed to inspect highly warped rectangular panels (larger than 500mm). This complements Rudolph’s JetStep (R) S line of steppers, which are panel-ready today. With this technology, Rudolph will offer a more comprehensive panel solution, which involves printing, inspecting and yield analysis, to quickly ramp lines and maintain high productivity.

“This new technology helps Rudolph provide configurable systems to meet current and future challenges faced by our customers,” said Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit. “As interconnect technology becomes increasingly important in back-end 3D and 2.5D applications, we anticipate this inspection technique to be a key component for our customers’ process control strategies.”

The company does not expect the transaction to have an impact on the results of operations for the 2015 third quarter. Terms of the transaction were not disclosed.

 

The official Call for Papers has been issued for the 2016 Symposia on VLSI Technology and Circuits, to be held at the Hilton Hawaiian Village June 13-16, 2016 (Technology) and June 15-17, 2016 (Circuits). The deadline for paper submissions to both conferences is January 25, 2016. The late-news paper submissions deadline for the Symposia on VLSI Technology is March 24, 2016; there is no late-news submission for the Symposium on VLSI Circuits. Complete details for paper submission can be found online at: http://www.vlsisymposium.org/authors/

For the past 28 years, the combined annual Symposia on VLSI Technology and Circuits has provided an opportunity for the world’s top device technologists, circuit and system designers to engage in an open exchange of leading edge ideas at the world’s premier mid-year conference for microelectronics technology. Held together since 1987, the Symposia on VLSI Technology and Circuits have alternated each year between sites in the US and Japan, enabling attendees to learn about new directions in the development of VLSI technology & circuit design through the industry’s leading research and development presentations.

The comprehensive technical programs at the two Symposia are augmented with short courses, invited speakers and several evening panel sessions. Since 2012, the Symposia have presented joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees.

The Symposium on VLSI Technology seeks technical innovation and advances in all aspects of IC technology, as well as the emerging IoT (Internet of Things) field, including:

  • IoT systems & technologies, including ultra-low power, heterogeneous integration, sensors, connectivity, power management, digital/analog, microcontrollers and application processors
  • Stand-alone & embedded memories, including DRAM, SRAM, non-volatile and emerging memory technologies
  • CMOS Technology, microprocessors & SoCs, including scaling, VLSI manufacturing concepts and yield optimization
  • RF / analog  /digital technologies for mixed-signal SoC, RF front end; analog, mixed-signal I/O, high voltage, imaging, MEMS, integrated sensors
  • Process & material technologies, including advanced transistor process and architecture, modeling and reliability; alternate channel; advanced lithography, high-density patterning; SOI and III-V technologies, photonics, local interconnects and Cu/optical interconnect scaling
  • Packaging technologies & System-in-Package (SiP)
  • Photonics Technology & “Beyond CMOS” devices 

The Symposium on VLSI Circuits seeks original papers showcasing technical innovations and advances in the following areas:

  • Digital circuits and processor techniques for standalone and embedded processors
  • Memory circuits, architectures & interfaces for volatile and non-volatile memories, including emerging memory technologies
  • Clock generation and distribution for high-frequency digital and mixed-signal applications
  • Analog and mixed-signal circuits, including amplifiers, filters and data converters
  • Wireline receivers & transmitters, including circuits for inter-chip and long-reach applications
  • Wireless receivers & transmitters, including circuits for WAN, LAN, PAN, BAN, inter-chip and mm-wave applications
  • Power management circuits, including battery management circuits, voltage regulators, energy harvesting circuits
  • Application-oriented circuits & VLSI systems, imagers, displays, and sensors for biomedical and healthcare applications

Joint technology and circuits focus sessions feature invited and contributed papers highlighting innovations and advances in materials, processes, devices, integration, reliability and modeling in the areas of advanced memories, 3D integration, and the impact of technology scaling on advanced circuit design. Submissions are strongly encouraged in the following areas of joint interest:

  • Design in scaled technologies: scaling of digital, memory, analog and mixed-signal circuits in advanced CMOS processes
  • Design enablement: design for manufacturing, process/design co-optimization, on-die monitoring of variability and reliability
  • Embedded memory technology & design: SRAM, DRAM, Flash, PCRAM, RRAM, MRAM and NVRAM memory technologies
  • 3D & heterogeneous integration: power and thermal management; inter-chip communications, SIP architectures and systems

Papers sought for “big integration”

Authors are encouraged to submit papers that showcase innovations that extend beyond single ICs and into the module, including focus areas in the Internet of Things (IoT), industrial electronics, “big data” management, biomedical applications, robotics and smart cars. These topics will be featured in focus sessions as part of the program.

Best Student Paper Award

Awards for best student paper at each Symposia will be chosen, based on the quality of the papers and presentations. The recipients will receive a financial award, travel cost support and a certificate at the opening session of the 2017 Symposium. For a paper to be reviewed for this award, the author must be enrolled as a full-time student at the time of submission, must be the lead author and presenter of the paper, and must indicate on the web submission form that the paper is a student paper.

Semiconductor Research Corporation (SRC), a leading global university-research consortium for semiconductor technologies, today announced that ARM has joined SRC’s Global Research Collaboration (GRC) program.

Research in the GRC program focuses on current semiconductor industry priorities, including the continued scaling of semiconductor technologies and finding diverse applications for them. The program has also expanded into new areas, including cybersecurity, technologies at the convergence of semiconductors and biology, novel approaches to energy-efficient computing, and the Internet of Things.

“We are pleased to have ARM join SRC’s Global Research Collaboration program.  GRC members are among the top semiconductor companies in the world and ARM is no exception,” said Celia Merzbacher, Vice President for Innovative Partnerships at SRC. “SRC supports a broad portfolio of innovative research driven by long-term industry needs. Members get access to the results in near real time and to the SRC-supported network of university researchers, comprising hundreds of faculty and thousands of students worldwide annually.  SRC has a record of investing in early stage research that had enormous impact industry-wide.”

“As process geometries shrink, the challenges of improving performance and energy efficiency through high levels of SoC integration are increasingly complex,” said Eric Hennenhoefer, Vice President, ARM Research. “The most effective way of addressing these challenges is through collaborative R&D. Joining SRC allows ARM to make a contribution and help drive the advancements from which the semiconductor industry as a whole can benefit.”

Semiconductor equipment manufacturer ClassOne Technology has today announced the appointment of Kevin Witt to the position of Chief Technology Officer. Part of the company’s initial executive team, Witt has served as ClassOne’s Vice President of Technology since 2013.

“I’m delighted to announce Kevin’s promotion,” said Byron Exarcos, President of ClassOne Technology. “He has more than 25 years in the industry, and the depth and breadth of his experience have contributed significantly to the rapid success we’ve enjoyed to date. His strengths will be even more important as he spearheads the development of our coming generations of cost-efficient, high-performance systems.”

Prior to joining ClassOne Technology Witt had been Director of Disruptive Technology at Semitool and was on the executive team that sold the company to Applied Materials. Witt has also held global marketing positions at Rodel and Solution Technology as well as engineering positions at AMD and Perkin Elmer. Subsequent to this, he cofounded and served as CTO/COO of Zinc Air, an energy storage company. He holds an MS degree in Materials Science and Engineering and a BS in Physics, both from the Rochester Institute of Technology.

Witt has been a key contributor in the development of ClassOne’s popular Solstice family of electroplating systems, which includes models for development and volume production. The Solstice S4 was recently given the BEST OF WEST Award at the SEMICON West 2015 Conference in San Francisco. ClassOne also provides the innovative Trident families of Spin Rinse Dryers (SRDs) and Spray Solvent Tools (SSTs). All are designed to deliver high-performance wet processing at an affordable price, aimed primarily at MEMS, Sensors, LEDs, RF, Interposers and other ≤200mm emerging markets. Described as providing “Advanced Wet Processing for the Rest of Us,” ClassOne systems are generally priced at less than half of what similarly configured tools from the larger manufacturers would cost.

Intersil Corporation, a provider of innovative power management and precision analog solutions, today announced the acquisition of Great Wall Semiconductor (GWS), a private technology company developing power metal-oxide semiconductor field-effect transistor (MOSFET) technology for cloud computing, space and consumer applications.

GWS’s design team brings valuable experience leveraging advanced design and process technology to enable power efficiency gains and footprint reduction in complex power systems. GWS’s existing and emerging FET products in combination with Intersil’s power controller portfolio, are expected to expand Intersil’s addressable market and provide compelling integration opportunities to accelerate innovation in the development of next generation power stages.

“This small but experienced team will be a great asset as we continue to expand our power management capabilities,” said Mark Downing, senior vice president of corporate strategy and infrastructure power products. “Intersil’s strategy is based on establishing market leadership through the development of highly efficient and highly integrated power management solutions. This acquisition is aligned with that effort and nicely augments our existing team with additional intellectual property and talent.”

“GWS has differentiated itself through expertise in Lateral Power MOSFET device and processing technology combined with miniature chipscale packaging,” said Sam Anderson, CEO of Great Wall Semiconductor. “We have developed important intellectual property that enables energy savings and environmental progess that can now reach a broader set of customers and markets as we become part of Intersil.”

Intersil acquired GWS for initial cash consideration of $19 million, with up to $4 million additional cash consideration based on the achievement of post-closing business metrics through 2016.  The acquisition is expected to be neutral to 2015 non-GAAP earnings.

The GaN devices market for power electronics application will explode in 2016, reaching US$300 million in 2020, Yole Développement (Yole) announced in its latest power electronic report, entitled GaN and SiC devices for power electronics applications (July 2015). The “More than Moore” market research and strategy consulting company Yole, highlights an increasing interest of numerous industrial companies already involved in this sector.

“The future GaN power devices market is also depending on the global patent landscape and coming mergers and acquisitions,” explained Dr. Nicolas Baron, CEO of KnowMade, partner of Yole.
Indeed KnowMade and Yole’s analysts are working together for a long time in order to combine their technical expertise and market knowledge. Both companies combine their vision of the industry and create a high added-value synergy through technical, market and patent analysis on the disruptive technology markets.

power GaN

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Nicolas Baron detailed: “To dominate the GaN power devices market, industrial companies will have to anticipate changes, identify business opportunities, mitigate risks and make strategic decisions to strengthen their market positioning and maximize return on IP portfolio.” But who owns these patents? To answer to these questions, KnowMade proposes today a comprehensive patent analysis dedicated to the GaN devices for power electronic applications. This report is entitled Power GaN Devices for Power Electronics patent investigation: under this report, KnowMade’s experts review the technical challenges, highlight the business opportunits and detail a comprehensive IP landscape.

Today, there are only a few players selling power GaN products: Infineon/International Rectifier, EPC, GaN Systems, Transphorm are the main companies. The market is still small, estimated at US$10 million in 2015 (Source: GaN and SiC devices for power electronics application report, July 2015, Yole Développement).

“But, the ramp-up will be quite impressive, starting in 2016, at an estimated 93 percent CAGR through 2016-2020, with an estimated 2020 device market size of more than US$300 million in the baseline ‘nominal’ scenario,” explained Dr. Hong Lin, Technology & Market Analyst at Yole.

The GaN devices for power electronics industry is consolidating in preparation for this significant growth. This can been seen in:

–  The recent acquisitions of International Rectifier (IR) by Infineon
–  The license agreements between Infineon and Panasonic and between Transphorm and Furukawa
–  And the will of several firms to move onto the mass production stage. Transphorm/Fujitsu is a good example.

Under the GaN Devices for Power Electronics patent investigation, KnowMade’s experts identified more than 1,960 worldwide patented inventions related to GaN for power electronic applications up to April 2015 and more than 200 patent applicants. Most of the major silicon power players are present in the list of the top patent applicants.

“Those figure indicate a strong interest from power electronic players in the GaN business” commented Dr. Nicolas Baron from KnowMade. And he added: “So far, only IR/Infineon has commercialized GaN devices. But other traditional power players are able to disrupt and reshape the market, armed with strong IP.”

According to this patent investigation, it can be safely assumed that IR has the best patent portfolio in power GaN, and IR/Infineon combined company has the strongest IP, putting them in position to lead GaN power market growth.

However, this IP leadership position could evolve in the future since newcomers like Transphorm, Fujitsu and Mitsubishi Electric are becoming major forces and may reshape the landscape:

– Transphorm is the most important IP challenger in the power GaN arena, ahead of other GaN start-ups like EPC and GaN Systems. Its patent portfolio and partnerships with the likes of Furukawa, Fujitsu and On Semiconductor have put it in a strong position to take a leading role in the GaN device market. Furukawa Electric has an ample IP portfolio with a significant ‘blocking potential’, but the company hasn’t been able yet to commercialize the technology on its own. By giving Transphorm exclusive licensing rights on its GaN patent portfolio, Furukawa Electric has found a strategic partner to bring its technology to market.

– In parallel, both companies, Fujitsu and Mitsubishi Electric have demonstrated an interest in power GaN technology since 2010 with a strong increase of their patenting activity these last 3 years, heralding substantial future IP portfolios.

With this new GaN patent analysis KnowMade and Yole review the power GaN technology and market trends, including technical challenges and known solutions. Both partners propose a deep understanding of the IP landscape and related key trends in IP and technology development.
This analysis lists as well the major players and relative strength of their patent portfolio. It also identifies the new players.

The analysts highlight the IP collaboration networks between the key players and propose a deep added-value synthesis of their strategic decisions.

Jason Chang, chairman of Advanced Semiconductor Engineering, Inc. has formally received the SEMI award at the 2015 SEMICON Taiwan Leadership Gala Dinner held in Taipei, Taiwan. The SEMI award recognizes Jason’s significant achievements in the development and commercialization of copper wire in the IC assembly process. This year, SEMICON also celebrates its 20th anniversary in Taiwan and Jason had the honor of receiving his award from President Ma Ying-jeou, who was the guest-of-honor at the event.

In early 2005, anticipating a steep increase in gold price, Jason embarked on a bold move to encourage the use of copper wire bonding as an alternative to gold wire bonding. When the price of gold soared in 2007 and to all-time highs in 2011 and 2012, ASE was able to offer a proven and viable alternative to customers. The transition from gold to copper, however, was not without challenge. Customers were initially skeptical about the thermal and electrical performance of copper versus gold and whether cost savings would ultimately be worthwhile. The ASE engineering team went through years of laborious studies, evaluations, and qualification lots, and with each successful production run, customers become increasingly confident with the process. By 2011, ASE was shipping more than four billion chips using copper wire bonding processes.

“It is a huge honor to receive the SEMI Award and be recognized amongst so many of our peers,” said Jason Chang. “In a dynamic industry where change and advancement is our lifeline, it is ASE’s mission to innovate and integrate the latest technologies, the newest materials, and the most advanced production methods to enable the success of our customers’ IC designs.”

The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration. The award is the highest honor conferred by SEMI. It is open to individuals or teams from industry or academia whose specific accomplishments have broad commercial impact and widespread technical significance for the entire semiconductor industry.