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Micron Technology, Inc. this week announced that the company has appointed Ernie Maddock as Chief Financial Officer and Vice President, Finance, effective June 1, 2015.

Mr. Maddock will join Micron after having served as Executive Vice President and Chief Financial Officer at Riverbed Technology, where he was also responsible for worldwide operations and information technology.

“Micron is a global leader in semiconductor memory and memory systems, focused on innovation and delivery of next-generation technology to a broad and diverse marketplace,” stated D. Mark Durcan, Chief Executive Officer. “We are extraordinarily pleased to have Ernie join the Micron team as CFO. He is extremely capable and is well prepared to drive long term value through growth, operational excellence, and effective capital allocation.”

Prior to his role at Riverbed, Maddock was with Lam Research, where he held several executive positions including Executive Vice President and Chief Financial Officer, Senior Vice President of Global Operations, and Vice President, Customer Support Business Group. Maddock’s career includes financial and operational experience in several industries ranging from commercial real estate to telecommunications.

The 61st annual IEEE International Electron Devices Meeting (IEDM) has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development. The paper submission deadline is Monday, June 22, 2015 at 23:59 p.m. Pacific Time.

Overall, the 2015 IEDM is seeking increased participation in the areas of ‘Beyond CMOS’ devices, flexible devices, neuromorphic computing, power devices, sensors for the Internet of Things (IoT) and variation/reliability.

In addition, Special Focus Sessions will be held on the following topics: neural-inspired architectures; 2D materials and applications; flexible electronics and applications; power devices and reliability on non-native substrates; and silicon-based nanodevices for detection of biomolecules.

The 2015 IEDM will take place at the Washington, DC Hilton Hotel from December 7-9, 2015, preceded by a collection of 90-minute afternoon Tutorial sessions on Saturday, Dec. 5, and a full day of Short Courses on Sunday, Dec. 6. On Wednesday the conference will continue the successful Entrepreneurs Luncheon sponsored by IEDM and EDS Women in Engineering.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics from industry, academia and government gather to participate in a technical program of more than 220 presentations, along with a special Luncheon Presentation on Tuesday, Dec. 8 and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events spotlighting more leading work in more areas of the field than any other conference.

Papers in the following areas are encouraged:
– Circuit and Device Interaction
– Characterization, Reliability and Yield
– Display and Imaging Systems
– Memory Technology
– Modeling and Simulation
– Nano Device Technology
– Power and Compound Semiconductor Devices
– Process and Manufacturing Technology
– Sensors, MEMS and BioMEMS

JSR Corporation, a materials company and imec, a nanoelectronics R&D center, today signed a Letter of Intent (LOI) to partner in enabling manufacturing and quality control of EUV lithography materials for the semiconductor industry. This partnership will be formalized by establishing a joint venture with imec as minority shareholder. The signing ceremony was held at the Embassy of the Kingdom of Belgium in Tokyo (Japan).

EUV lithography is considered as one of the main drivers to extend Moore’s law towards single digit nanometer technology nodes. Imec and JSR’s collaboration, will allow both companies to leverage their strengths when developing photoresist solutions for the semiconductor industry to manufacture the most advanced devices. JSR will provide manufacturing technology to the joint venture including upgrading the facility at its wholly-owned subsidiary in Belgium, JSR Micro NV, by installing manufacturing and analytical equipment. Imec will provide expertise and services to the joint venture for quality control on materials. In addition to the manufacturing of JSR brand photoresists, the joint venture will offer toll-manufacturing capability to other material suppliers with confidentiality secured.

“JSR has been a strategic partner of imec for a long time, and I am excited with this intensified collaboration,” stated Luc Van den hove, president and CEO at imec. “This collaboration strengthens our supplier hub concept, a neutral open innovation R&D platform that involves suppliers more deeply and at an early stage of process step and module development. The partnership enabled through close proximity between the JSR manufacturing facility and the imec technology platform will allow our partners to gain access to best-in-class materials for next-generation technologies.”

“We know that EUV lithography is required to realize Moore’s law in semiconductor manufacturing technologies and we continuously focus our R&D efforts to meet industry needs,” said Nobu Koshiba, President of JSR Corporation. “JSR has successfully developed not only chemically amplified photoresists, but also newly designed chemistries with very high sensitivity and good productivity. Our strength has also extended to peripheral materials, such as multilayer materials. The industry is requesting material suppliers to prepare manufacturing infrastructure and quality control capabilities for defect-free lithography solutions, as well as to improve photoresist performance to match EUV exposure equipment. It is by knowing those industry needs and requirements very well, that we, two world leading organizations that have supported the semiconductor industry for a long time, come to this unique idea to form a manufacturing joint venture to support those future industry needs. This is done based on our very long, trust-worthy relationship with imec. This is a very exciting challenge for us and I have great respect for imec for their brave and challenging spirits.”

Advanced Semiconductor Engineering, Inc. and TDK Corporation announced today that both companies will enter into an agreement to establish a joint venture company to manufacture IC embedded substrates using TDK’s SESUB (Semiconductor Embedded SUBstrate) technology. ASE and TDK plan to own 51 percent and 49 percent, respectively, of the newly created entity. The indicative name of the joint venture company will be ASE Embedded Electronics Incorporated, and its manufacturing facility is planned to be located in the Nantze Export Processing Zone, Kaohsiung City, Taiwan.

TDK developed its proprietary SESUB technology by harnessing its signature technologies in ultrafine processing and materials. The SESUB technology enables semiconductor chips to be thinned down to as low as 50 μm and embedded in a four-layer plastic substrate. TDK’s SESUB technology provides numerous advantages, such as enabling miniaturization by reducing the mounting area on substrates and a thinner profile by achieving a 300 μm thickness. Other advantages include excellent thermal dissipation characteristics, which offer greater design flexibility and inter-chip connection that enhances EMI performance.

ASE SiP solutions using SESUB technology will offer a robust embedded solution in enabling a wide number of applications such as PMIC, sensors and RF tuners etc. The planned joint venture business model aims to leverage on TDK’s success in delivering SESUB technology to the market with ASE’s capabilities in advanced packaging, test and module level solutions for semiconductor miniaturization.

“With the anticipated need for further miniaturization and weight reduction of smartphones and wearable devices in the future, demand for semiconductors embedded in substrates, such as SESUBs, is expected to increase globally,” says Mr. Takehiro Kamigama, CEO and President of TDK Corporation. “TDK has already been producing SESUBs at its Kofu Plant, but to meet the anticipated increase in demand, it will establish the joint company in Taiwan to add to its production capacity with ASE, which possesses technologies including assembly of IC packages and other items, and boasts a world-class performance record in product testing. The joint venture establishment will create a structure for full-scale mass production,” added Mr Takehiro Kamigama.

“ASE serves a diverse group of customers including several major players supplying to the portable and wearable consumer market and is a leader in SIP integration using its advanced packaging solutions and test expertise. TDK, on the other hand, has a proven proprietary embedded substrate technology addressing the market needs of integrating more chips and functions, higher performance, lower power consumption and better heat dissipation onto a smaller form factor,” says Dr Tien Wu, COO, ASE Group. “We see this powerful alliance as an added value to the ASE SIP ecosystem and together, catapulting TDK’s SESUB technology into the forefront as an industry standard,’’ added Dr. Tien Wu.

The proposed establishment of and capital injection into the joint venture company will be subject to various regulatory approvals or consents (including but not limited to the approvals of the Taiwan Fair Trade Commission and Export Processing Zone Administration).

BY GREG SHUTTLEWORTH, Global Product Manager at LINDE ELECTRONICS

The market expectations of modern electronics technology are changing the landscape in terms of performance and, in particular, power consumption, and new innovations are putting unprecedented demands on semiconductor devices. Internet of Things devices, for example, largely depend on a range of different sensors, and will require new architectures to handle the unprecedented levels of data and operations running through their slight form factors.

The continued shrinkage of semiconductor dimensions and the matching decreases in microchip size have corresponded to the principles of Moore’s Law with an uncanny reliability since the idea’s coining in 1965. However, the curtain is now closing on the era of predictable / conventional size reduction due to physical and material limitations.

Thus, in order to continue to deliver increased performance at lower costs and with a smaller footprint, different approaches are being explored. Companies can already combine multiple functions on a single chip–memory and logic devices, for example–or an Internet of Things device running multiple types of sensor through a single chip.

We have always known that we’d reach a point where conventional shrinking of semiconductor dimensions would begin to lose its effect, but now we are starting to tackle it head on. A leading U.S. semiconductor manufacturer got the ball rolling with their FinFET (or tri–gate) design in 2012 with its 3D transistors allowing designs that minimize current leakage; other companies look set to bring their own 3D chips to market.

At the same time, there’s a great deal of experimentation with a range of other approaches to semiconductor redesign. Memory device manufacturers, for instance, are looking to stack memory cells vertically on top of each other in order to make the most of a microchip’s limited space. Others, meanwhile, are examining the materials in the hope of using new, more efficient silicon–like materials in their chips.

Regardless of the approach taken, however, this step change in microchip creation means new material demands from chip makers and new manufacturing techniques to go with them.

The semiconductor industry has traditionally had to add new materials and process techniques to enhance the performance of the basic silicon building blocks with tungsten plugs, copper wiring / CMP, high–k metal gates, for example. Now, however, it is beginning to become impossible to extend conventional materials to meet the performance requirements. Germanium is already added to Si to introduce strain, but its high electron mobility means Germanium is also likely to become the material of the Fin itself and will be complemented by a corresponding Fin made of III–V material, in effect integrating three semiconductor materials into a single device.

Further innovation is required in the areas of lithography and etch. This is due to the delay in production suitability of the EUV lithography system proposed to print the very fine structures required for future technology nodes. Complex multi-patterning schemes using conventional lithography are already underway to compensate for this technology delay, requiring the use of carbon hard masks and the introduction of gases such as acetylene, propylene and carbonyl sulphide to the semiconductor fab. Printing the features is only half of the challenge; the structures also need to be etched. The introduction of new materials always presents some etch challenges as all materials etch at slightly different rates and the move to 3D structures, where very deep and narrow features need to be defined through a stack of different materials, will be a particularly difficult challenge to meet.

The microchip industry has continuously evolved to deliver amazing technological advances, but we are now seeing the start of a revolution in microchip design and manufacturing. The revolution will be slow but steady. Such is the pattern of the microchip industry, but it will need a succession of new materials at the ready, and, at Linde, we’re prepared to make sure the innovators have everything they need.

A new study coauthored by Wellesley economist, Professor Daniel E. Sichel, reveals that innovation in an important technology sector is happening faster than experts had previously thought, creating a backdrop for better economic times ahead.

The Producer Price Index (PPI) of the United States suggests that the prices of semiconductors have barely fallen in recent years. The slow decline in semiconductor prices stands in sharp contrast to the rapidly falling prices reported from the mid-1980s to the early 2000s, and has been interpreted as a signal of sluggish innovation in this key sector.

The apparent slowdown puzzled Sichel and his coauthors, David M. Byrne of the Federal Reserve Board, and Stephen D. Oliner, of the American Enterprise Institute and UCLA–particularly in light of evidence that the performance of microprocessor units (MPUs), which account for about half of U.S. semiconductor shipments, has continued to improve at rapid pace. After closely examining historical pricing data, the economists found that Intel, the leading producer of MPUs, dramatically changed the way it priced these chips in the mid-2000s–roughly the same time when the slowdown reported by government data occurs. Prior to this period, Intel typically lowered the list prices of older chips to remain competitive with newly introduced chips. However, after 2006, Intel began to keep chip prices relatively unchanged over their life cycle, which affected official statistics.

To obtain a more accurate assessment of the pace of innovation in this important sector, Sichel, Byrne, and Oliner developed an alternative method of measurement that evaluates changes in actual MPU performance to gauge the rate of improvement in price-performance ratios. The economists’ preferred index shows that quality-adjusted MPU prices continued to fall rapidly after the mid-2000s, contrary to what the PPI indicates–meaning that worries about a slowdown in this sector are likely unwarranted.

According to Sichel, these results have important implications, not only for understanding the rate of technological progress in the semiconductor industry but also for the broader debate about the pace of innovation in the U.S. economy.

“These findings give us reason to be optimistic,” said Sichel. “If technical change in this part of the economy is still rapid, it provides hope for better times ahead.”

Sichel and his coauthors also acknowledge that their results raise a new puzzle. “In recent years,” they write, “the price index for computing equipment has fallen quite slowly by historical standards. If MPU prices have, in fact, continued to decline rapidly, why have prices for computers–which rely on MPUs for their performance–not followed suit?” The researchers believe it is possible that the official price indexes for computers may also suffer from measurement issues, and they are investigating this possibility in further work.

“How Fast Are Semiconductor Prices Falling,” coauthored by Daniel E. Sichel, Wellesley College and NBER; David M. Byrne, Federal Reserve Board; and Stephen D. Oliner, American Enterprise Institute and UCLA, is available as an NBER working paper and is online at http://www.nber.org/papers/w21074 and https://www.aei.org/publication/how-fast-are-semiconductor-prices-falling/.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $83.1 billion during the first quarter of 2015, an increase of 6.0 percent compared to the first quarter of 2014. Global sales for the month of March 2015 were $27.7 billion, 6.0 percent higher than the March 2014 total of $26.1 billion and 0.1 percent lower than last month’s total. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Despite macroeconomic challenges, first quarter global semiconductor sales are higher than they were last year, which was a record year for semiconductor revenue,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas region posted its sixth straight month of double-digit, year-to-year growth to lead all regional markets, and DRAM and analog products continue to be key drivers of global sales growth.”

Regionally, sales were up compared to last month in Asia Pacific/All Other (3.1 percent), Europe (2.7 percent), and China (1.0 percent), which is broken out as a separate country in the sales data for the first time. Japan(-0.4 percent) and the Americas (-6.9 percent) both saw sales decrease compared to last month. Compared to March 2014, sales increased in the Americas (14.2 percent), China (13.3 percent), and Asia Pacific/All Other (3.8 percent), but decreased in Europe (-4.0 percent) and Japan (-9.6 percent).

“Congress is considering a legislative initiative called Trade Promotion Authority (TPA) that would help promote continued growth in the semiconductor sector and throughout the U.S. economy,” Neuffer continued. “Free trade is vital to the U.S. semiconductor industry. In 2014, U.S. semiconductor company sales totaled $173 billion, representing over half the global market, and 82 percent of those sales were to customers outside the United States. TPA paves the way for free trade, and Congress should swiftly enact it.”

March 2015
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 6.23 5.80 -6.9%
Europe 2.88 2.95 2.7%
Japan 2.55 2.54 -0.4%
China 7.75 7.83 1.0%
Asia Pacific/All Other 8.33 8.59 3.1%
Total 27.74 27.71 -0.1%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 5.08 5.80 14.2%
Europe 3.08 2.95 -4.0%
Japan 2.81 2.54 -9.6%
China 6.91 7.83 13.3%
Asia Pacific/All Other 8.27 8.59 3.8%
Total 26.15 27.71 6.0%
Three-Month-Moving Average Sales
Market Oct/Nov/Dec Jan/Feb/Mar % Change
Americas 6.73 5.80 -13.8%
Europe 3.01 2.95 -1.7%
Japan 2.80 2.54 -9.1%
China 8.03 7.83 -2.5%
Asia Pacific/All Other 8.57 8.59 0.2%
Total 29.13 27.71 -4.9%

About SIA

SEMATECH and Exogenesis Corp. have agreed to a strategic alliance to commercialize Exogenesis’ Accelerated Neutral Atom Beam (ANAB) technology and their nAcceltm accelerated particle beam equipment platform.

“The chip industry is in the era of atomic scale processing.  The applications of ANAB being developed will enable better controlled and more efficient manufacturing and open up new functionality for semiconductor devices,” said Ron Goldblatt, Ph.D., SEMATECH CEO and President.

SEMATECH and Exogenesis will form a new company to bring ANAB technology to market for the semiconductor industry.  Beyond the initial focus on integrated circuit manufacturing, the partners will explore ANAB applications in other nanoelectronics fields which may lead to the formation of additional companies.

ANAB technology is a unique, patented approach to modifying and controlling surfaces with atomic level control at a depth of a few nanometers.

“There is no other technology that offers the performance profile of ANAB” says Richard Svrluga, President and CEO of Exogenesis.  Chemical modification, material removal and deposition, surface smoothing and control of surface morphology are all possible with the ANAB platform.

ANAB is already being used in the biomedical field for precise control of pharmacological and biointegration properties and to enable development of more safe and efficacious implantable medical devices.  ANAB has been demonstrated to provide benefits to the surfaces of a wide range of materials including glass, metals, organic, semiconductor and polymeric materials.

“SEMATECH and Exogenesis have worked together since 2013 as part of SEMATECH’s programs to enable the semiconductor industry’s adoption of Extreme Ultraviolet Lithography (EUVL)” said Ed Barth, Ph.D., SEMATECH Director of Corporate Development.  “The partners have already demonstrated and published the value of ANAB technology for improving transparency of thin silicon membranes which was a significant performance enhancement for EUV pellicles,” said Barth.

Other work by Exogenesis and SEMATECH demonstrated that ANAB processing enabled a level of smoothing of EUV mask substrates to a quality better than conventional methods, improving the optical properties of the mask blanks created with them.   These results were published in 2014.

Ongoing development work will occur both at Exogenesis facilities and at the NanoTech Complex of SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE) in Albany, NY.   This will allow the strategic alliance to leverage SUNY Poly CNSE’s state-of-the-art resources and the NanoTech Complex’s globally recognized capabilities to rapidly bring new innovations to market which improve the quality, reliability and performance of advanced nanoelectronics.

Intel in India reinforced its commitment to the Government of India’s Digital India vision with the announcement of the Intel and DST “Innovate for Digital India Challenge,” which will focus on the creation of products to increase technology adoption in India that will eventually result in the creation of a local technology ecosystem. It will be open to aspiring and existing entrepreneurs, innovators, academia, designers, engineers and makers from diverse backgrounds. Participants will be provided mentoring by industry stalwarts and Intel experts, assistance in terms of technical know-how, access to product kits and infrastructure, and commercialization opportunities. They will also be offered market linkages and access to funds at various stages to help make their ideas a reality.

The challenge was designed in collaboration with the Department of Science and Technology (DST), with support from the Department for Electronics and Information Technology, MyGov.in and will be managed by IIM Ahmedabad’s Centre for Innovation Incubation and Entrepreneurship(CIIE).Shri R S Sharma, Secretary, Department of Electronics and Information Technology (DeitY),  Ministry of Communications and Information Technology, Government of India, led the launch event together with Shri H K Mittal, Member Secretary, National Science and Technology Entrepreneurship Development Board (NSTEDB); Shri Gaurav Dwivedi, CEO, MyGov.in; Professor Rakesh Basant, chairperson, CIIE; Vikas Jain, co-founder, Micromax Informatics; and Ms. Debjani Ghosh, vice president, Sales and Marketing Group and managing director, Intel South Asia.

Speaking at the event, Shri Ram Sewak Sharma, Secretary, Department of Electronics and Information Technology (DeitY), Ministry of Communications and Information Technology, Government of India, said, “We are delighted to see industry leaders like Intel contributing to nation building and joining forces with the government in its journey to transforming India into a knowledge economy. With this challenge, we expect to see breakthrough ideas and ingenious innovations that will solve some of India’s key challenges.”

The challenge aims to encourage the creation of intuitive, easy-to-use solutions that can increase access to critical services imperative for development. Eventually the best ideas will get help for commercialization leading to the creation of a local technology ecosystem furthering the government’s Make in India vision. The challenge will encourage the application of the principles of frugal innovation and a strong understanding of Indian lifestyles. It will focus on innovation in two broad areas. The first is innovation to create the ideal citizen’s device platform, including biometric sensing capabilities, peripherals using other sensors, intuitive user interface, gesture recognition, multilingual support and voice support. The second area is innovation to deliver eKranti*/MyGov applications to accelerate delivery of e-governance services on a mobile platform.

Shri H K Mittal, Member Secretary, National Science and Technology Entrepreneurship Development Board (NSTEDB), said, “Innovation always leads the way to finding the most creative solutions to societal challenges. Generating innovation is not the job of the government alone. Therefore it gives me great optimism to have Intel come forward – through Public Private Partnerships – to accelerate innovation and entrepreneurship in India.”

“Innovation is part of Intel’s DNA,” said Ms. Ghosh. “This challenge will combine Intel’s history of game-changing innovation and world-class technology with the government’s bold Digital India vision and the immense entrepreneurship talent in the country to create a sustainable tech ecosystem that is innovating for India. We are excited to collaborate with DST to launch the Innovate for Digital India Challenge to champion new solutions to make technology more effective in India as a channel to drive real ground-up development. Through this challenge, we aim to bring to market tangible products and solutions that will help make Digital India a reality.”

Intel recently celebrated 50 years of Moore’s Law. It remains Intel’s driving force that will enable an emerging generation of inventors, entrepreneurs and leaders to reimagine the future. Moore’s Law doesn’t just drive technological change; it also creates huge economic value and drives social advancement. Launching this challenge in the same week as the 50-year celebration of Moore’s Law reemphasizes Intel’s commitment to innovation.

Intel has been fostering innovation for more than two decades in India from school level to higher education, including Ph.D. Fellowships. More than 180 Indian school students have participated in the Intel® International Science and Engineering Fair to date, with 18 Indian winners, who have minor planets named after them. The Intel Higher Education Program bridges the gap between academia and industry standards to promote innovation and entrepreneurship and has reached more than 235,000 students and 4,500 faculty members across 550 institutions to date. Last year, Intel India announced the Intel Ph.D. Sponsorship Program to boost quality research and enhance Ph.D. programs across the country.

The Intel Innovate for Digital India Challenge in association with the Department of Science and Technology is a bold attempt from Intel to foster grassroots level innovation that will help bring technology to every household in India.

“The MyGov platform is designed to link government and citizens,” said Mr. Gaurav Dwivedi, CEO, MyGov. “We are proud to support this challenge by connecting the government with entrepreneurs and innovators to come forward with solutions made in India, for India.”

Speaking about the role of CIIE-IIMA, Professor Rakesh Basant said, “Incubation centers play a critical role in helping entrepreneurs scale up and are an essential part of the Indian ecosystem to build a digitally empowered country. We are excited to collaborate with the government and Intel to create a platform for young innovators across the nation to showcase their ideas and support them in their journey from ideas to products.”

Entegris, Inc., a provider of yield-enhancing materials and solutions for advanced manufacturing processes, announced the election of James P. Lederer as an independent director at the Company’s Annual Meeting of Shareholders held today. Mr. Lederer’s career spanned more than 32 years, with the last 18 in the semiconductor industry, including six years as an executive officer at Qualcomm.

“I am delighted to have Jim on our board,” said Bertrand Loy, president and CEO of Entegris. “Jim’s experience at Qualcomm brings an important customer and industry perspective. I look forward to his contributions and his insight as a member of our board.”

Paul Olson, chairman of the board of Entegris, added: “Through his career Jim has demonstrated a keen understanding of what it takes to succeed in a fast-paced technology industry, having played a key role in driving Qualcomm to be a technology powerhouse. I think his perspective on the industry will be an invaluable addition to the board.”

“Entegris is increasingly viewed as an indispensable partner by the semiconductor industry’s technology leaders.” says Lederer. “I look forward to working with Bertrand and his leadership team to continue to drive growth and success at Entegris.”

Mr. Lederer most recently served as Executive Vice President of Qualcomm Technologies, Inc. and General Manager of Qualcomm CDMA Technologies (QCT, semiconductor division). He retired from Qualcomm in January 2014. During his 18-year career at Qualcomm, Mr. Lederer also served in a number of senior management and finance roles. Prior to joining Qualcomm, Mr. Lederer held a variety of management positions at Motorola, General Motors and Scott Aviation. Mr. Lederer holds a B.S. degree in Business Administration (Finance/MIS) and an M.B.A. from the State University of New York at Buffalo, where he also serves on the Dean’s Advisory Council for the School of Management.